tegra-hsp.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/io.h>
  8. #include <linux/mailbox_controller.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm.h>
  13. #include <linux/slab.h>
  14. #include <soc/tegra/fuse.h>
  15. #include <dt-bindings/mailbox/tegra186-hsp.h>
  16. #include "mailbox.h"
  17. #define HSP_INT_IE(x) (0x100 + ((x) * 4))
  18. #define HSP_INT_IV 0x300
  19. #define HSP_INT_IR 0x304
  20. #define HSP_INT_EMPTY_SHIFT 0
  21. #define HSP_INT_EMPTY_MASK 0xff
  22. #define HSP_INT_FULL_SHIFT 8
  23. #define HSP_INT_FULL_MASK 0xff
  24. #define HSP_INT_DIMENSIONING 0x380
  25. #define HSP_nSM_SHIFT 0
  26. #define HSP_nSS_SHIFT 4
  27. #define HSP_nAS_SHIFT 8
  28. #define HSP_nDB_SHIFT 12
  29. #define HSP_nSI_SHIFT 16
  30. #define HSP_nINT_MASK 0xf
  31. #define HSP_DB_TRIGGER 0x0
  32. #define HSP_DB_ENABLE 0x4
  33. #define HSP_DB_RAW 0x8
  34. #define HSP_DB_PENDING 0xc
  35. #define HSP_SM_SHRD_MBOX 0x0
  36. #define HSP_SM_SHRD_MBOX_FULL BIT(31)
  37. #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
  38. #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
  39. #define HSP_DB_CCPLEX 1
  40. #define HSP_DB_BPMP 3
  41. #define HSP_DB_MAX 7
  42. struct tegra_hsp_channel;
  43. struct tegra_hsp;
  44. struct tegra_hsp_channel {
  45. struct tegra_hsp *hsp;
  46. struct mbox_chan *chan;
  47. void __iomem *regs;
  48. };
  49. struct tegra_hsp_doorbell {
  50. struct tegra_hsp_channel channel;
  51. struct list_head list;
  52. const char *name;
  53. unsigned int master;
  54. unsigned int index;
  55. };
  56. struct tegra_hsp_mailbox {
  57. struct tegra_hsp_channel channel;
  58. unsigned int index;
  59. bool producer;
  60. };
  61. struct tegra_hsp_db_map {
  62. const char *name;
  63. unsigned int master;
  64. unsigned int index;
  65. };
  66. struct tegra_hsp_soc {
  67. const struct tegra_hsp_db_map *map;
  68. bool has_per_mb_ie;
  69. };
  70. struct tegra_hsp {
  71. struct device *dev;
  72. const struct tegra_hsp_soc *soc;
  73. struct mbox_controller mbox_db;
  74. struct mbox_controller mbox_sm;
  75. void __iomem *regs;
  76. unsigned int doorbell_irq;
  77. unsigned int *shared_irqs;
  78. unsigned int shared_irq;
  79. unsigned int num_sm;
  80. unsigned int num_as;
  81. unsigned int num_ss;
  82. unsigned int num_db;
  83. unsigned int num_si;
  84. spinlock_t lock;
  85. struct list_head doorbells;
  86. struct tegra_hsp_mailbox *mailboxes;
  87. unsigned long mask;
  88. };
  89. static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
  90. {
  91. return readl(hsp->regs + offset);
  92. }
  93. static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
  94. unsigned int offset)
  95. {
  96. writel(value, hsp->regs + offset);
  97. }
  98. static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
  99. unsigned int offset)
  100. {
  101. return readl(channel->regs + offset);
  102. }
  103. static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
  104. u32 value, unsigned int offset)
  105. {
  106. writel(value, channel->regs + offset);
  107. }
  108. static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
  109. {
  110. u32 value;
  111. value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
  112. return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
  113. }
  114. static struct tegra_hsp_doorbell *
  115. __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
  116. {
  117. struct tegra_hsp_doorbell *entry;
  118. list_for_each_entry(entry, &hsp->doorbells, list)
  119. if (entry->master == master)
  120. return entry;
  121. return NULL;
  122. }
  123. static struct tegra_hsp_doorbell *
  124. tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
  125. {
  126. struct tegra_hsp_doorbell *db;
  127. unsigned long flags;
  128. spin_lock_irqsave(&hsp->lock, flags);
  129. db = __tegra_hsp_doorbell_get(hsp, master);
  130. spin_unlock_irqrestore(&hsp->lock, flags);
  131. return db;
  132. }
  133. static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
  134. {
  135. struct tegra_hsp *hsp = data;
  136. struct tegra_hsp_doorbell *db;
  137. unsigned long master, value;
  138. db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
  139. if (!db)
  140. return IRQ_NONE;
  141. value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
  142. tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
  143. spin_lock(&hsp->lock);
  144. for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
  145. struct tegra_hsp_doorbell *db;
  146. db = __tegra_hsp_doorbell_get(hsp, master);
  147. /*
  148. * Depending on the bootloader chain, the CCPLEX doorbell will
  149. * have some doorbells enabled, which means that requesting an
  150. * interrupt will immediately fire.
  151. *
  152. * In that case, db->channel.chan will still be NULL here and
  153. * cause a crash if not properly guarded.
  154. *
  155. * It remains to be seen if ignoring the doorbell in that case
  156. * is the correct solution.
  157. */
  158. if (db && db->channel.chan)
  159. mbox_chan_received_data(db->channel.chan, NULL);
  160. }
  161. spin_unlock(&hsp->lock);
  162. return IRQ_HANDLED;
  163. }
  164. static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
  165. {
  166. struct tegra_hsp *hsp = data;
  167. unsigned long bit, mask;
  168. u32 status, value;
  169. void *msg;
  170. status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
  171. /* process EMPTY interrupts first */
  172. mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
  173. for_each_set_bit(bit, &mask, hsp->num_sm) {
  174. struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
  175. if (mb->producer) {
  176. /*
  177. * Disable EMPTY interrupts until data is sent with
  178. * the next message. These interrupts are level-
  179. * triggered, so if we kept them enabled they would
  180. * constantly trigger until we next write data into
  181. * the message.
  182. */
  183. spin_lock(&hsp->lock);
  184. hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
  185. tegra_hsp_writel(hsp, hsp->mask,
  186. HSP_INT_IE(hsp->shared_irq));
  187. spin_unlock(&hsp->lock);
  188. mbox_chan_txdone(mb->channel.chan, 0);
  189. }
  190. }
  191. /* process FULL interrupts */
  192. mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
  193. for_each_set_bit(bit, &mask, hsp->num_sm) {
  194. struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
  195. if (!mb->producer) {
  196. value = tegra_hsp_channel_readl(&mb->channel,
  197. HSP_SM_SHRD_MBOX);
  198. value &= ~HSP_SM_SHRD_MBOX_FULL;
  199. msg = (void *)(unsigned long)value;
  200. mbox_chan_received_data(mb->channel.chan, msg);
  201. /*
  202. * Need to clear all bits here since some producers,
  203. * such as TCU, depend on fields in the register
  204. * getting cleared by the consumer.
  205. *
  206. * The mailbox API doesn't give the consumers a way
  207. * of doing that explicitly, so we have to make sure
  208. * we cover all possible cases.
  209. */
  210. tegra_hsp_channel_writel(&mb->channel, 0x0,
  211. HSP_SM_SHRD_MBOX);
  212. }
  213. }
  214. return IRQ_HANDLED;
  215. }
  216. static struct tegra_hsp_channel *
  217. tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
  218. unsigned int master, unsigned int index)
  219. {
  220. struct tegra_hsp_doorbell *db;
  221. unsigned int offset;
  222. unsigned long flags;
  223. db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
  224. if (!db)
  225. return ERR_PTR(-ENOMEM);
  226. offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
  227. offset += index * 0x100;
  228. db->channel.regs = hsp->regs + offset;
  229. db->channel.hsp = hsp;
  230. db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
  231. db->master = master;
  232. db->index = index;
  233. spin_lock_irqsave(&hsp->lock, flags);
  234. list_add_tail(&db->list, &hsp->doorbells);
  235. spin_unlock_irqrestore(&hsp->lock, flags);
  236. return &db->channel;
  237. }
  238. static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
  239. {
  240. struct tegra_hsp_doorbell *db = chan->con_priv;
  241. tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
  242. return 0;
  243. }
  244. static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
  245. {
  246. struct tegra_hsp_doorbell *db = chan->con_priv;
  247. struct tegra_hsp *hsp = db->channel.hsp;
  248. struct tegra_hsp_doorbell *ccplex;
  249. unsigned long flags;
  250. u32 value;
  251. if (db->master >= chan->mbox->num_chans) {
  252. dev_err(chan->mbox->dev,
  253. "invalid master ID %u for HSP channel\n",
  254. db->master);
  255. return -EINVAL;
  256. }
  257. ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
  258. if (!ccplex)
  259. return -ENODEV;
  260. /*
  261. * On simulation platforms the BPMP hasn't had a chance yet to mark
  262. * the doorbell as ringable by the CCPLEX, so we want to skip extra
  263. * checks here.
  264. */
  265. if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
  266. return -ENODEV;
  267. spin_lock_irqsave(&hsp->lock, flags);
  268. value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
  269. value |= BIT(db->master);
  270. tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
  271. spin_unlock_irqrestore(&hsp->lock, flags);
  272. return 0;
  273. }
  274. static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
  275. {
  276. struct tegra_hsp_doorbell *db = chan->con_priv;
  277. struct tegra_hsp *hsp = db->channel.hsp;
  278. struct tegra_hsp_doorbell *ccplex;
  279. unsigned long flags;
  280. u32 value;
  281. ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
  282. if (!ccplex)
  283. return;
  284. spin_lock_irqsave(&hsp->lock, flags);
  285. value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
  286. value &= ~BIT(db->master);
  287. tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
  288. spin_unlock_irqrestore(&hsp->lock, flags);
  289. }
  290. static const struct mbox_chan_ops tegra_hsp_db_ops = {
  291. .send_data = tegra_hsp_doorbell_send_data,
  292. .startup = tegra_hsp_doorbell_startup,
  293. .shutdown = tegra_hsp_doorbell_shutdown,
  294. };
  295. static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
  296. {
  297. struct tegra_hsp_mailbox *mb = chan->con_priv;
  298. struct tegra_hsp *hsp = mb->channel.hsp;
  299. unsigned long flags;
  300. u32 value;
  301. if (WARN_ON(!mb->producer))
  302. return -EPERM;
  303. /* copy data and mark mailbox full */
  304. value = (u32)(unsigned long)data;
  305. value |= HSP_SM_SHRD_MBOX_FULL;
  306. tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
  307. /* enable EMPTY interrupt for the shared mailbox */
  308. spin_lock_irqsave(&hsp->lock, flags);
  309. hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
  310. tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
  311. spin_unlock_irqrestore(&hsp->lock, flags);
  312. return 0;
  313. }
  314. static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
  315. unsigned long timeout)
  316. {
  317. struct tegra_hsp_mailbox *mb = chan->con_priv;
  318. struct tegra_hsp_channel *ch = &mb->channel;
  319. u32 value;
  320. timeout = jiffies + msecs_to_jiffies(timeout);
  321. while (time_before(jiffies, timeout)) {
  322. value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
  323. if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
  324. mbox_chan_txdone(chan, 0);
  325. /* Wait until channel is empty */
  326. if (chan->active_req != NULL)
  327. continue;
  328. return 0;
  329. }
  330. udelay(1);
  331. }
  332. return -ETIME;
  333. }
  334. static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
  335. {
  336. struct tegra_hsp_mailbox *mb = chan->con_priv;
  337. struct tegra_hsp_channel *ch = &mb->channel;
  338. struct tegra_hsp *hsp = mb->channel.hsp;
  339. unsigned long flags;
  340. chan->txdone_method = TXDONE_BY_IRQ;
  341. /*
  342. * Shared mailboxes start out as consumers by default. FULL and EMPTY
  343. * interrupts are coalesced at the same shared interrupt.
  344. *
  345. * Keep EMPTY interrupts disabled at startup and only enable them when
  346. * the mailbox is actually full. This is required because the FULL and
  347. * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
  348. * enabled all the time would cause an interrupt storm while mailboxes
  349. * are idle.
  350. */
  351. spin_lock_irqsave(&hsp->lock, flags);
  352. if (mb->producer)
  353. hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
  354. else
  355. hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
  356. tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
  357. spin_unlock_irqrestore(&hsp->lock, flags);
  358. if (hsp->soc->has_per_mb_ie) {
  359. if (mb->producer)
  360. tegra_hsp_channel_writel(ch, 0x0,
  361. HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
  362. else
  363. tegra_hsp_channel_writel(ch, 0x1,
  364. HSP_SM_SHRD_MBOX_FULL_INT_IE);
  365. }
  366. return 0;
  367. }
  368. static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
  369. {
  370. struct tegra_hsp_mailbox *mb = chan->con_priv;
  371. struct tegra_hsp_channel *ch = &mb->channel;
  372. struct tegra_hsp *hsp = mb->channel.hsp;
  373. unsigned long flags;
  374. if (hsp->soc->has_per_mb_ie) {
  375. if (mb->producer)
  376. tegra_hsp_channel_writel(ch, 0x0,
  377. HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
  378. else
  379. tegra_hsp_channel_writel(ch, 0x0,
  380. HSP_SM_SHRD_MBOX_FULL_INT_IE);
  381. }
  382. spin_lock_irqsave(&hsp->lock, flags);
  383. if (mb->producer)
  384. hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
  385. else
  386. hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
  387. tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
  388. spin_unlock_irqrestore(&hsp->lock, flags);
  389. }
  390. static const struct mbox_chan_ops tegra_hsp_sm_ops = {
  391. .send_data = tegra_hsp_mailbox_send_data,
  392. .flush = tegra_hsp_mailbox_flush,
  393. .startup = tegra_hsp_mailbox_startup,
  394. .shutdown = tegra_hsp_mailbox_shutdown,
  395. };
  396. static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
  397. const struct of_phandle_args *args)
  398. {
  399. struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
  400. unsigned int type = args->args[0], master = args->args[1];
  401. struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
  402. struct tegra_hsp_doorbell *db;
  403. struct mbox_chan *chan;
  404. unsigned long flags;
  405. unsigned int i;
  406. if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
  407. return ERR_PTR(-ENODEV);
  408. db = tegra_hsp_doorbell_get(hsp, master);
  409. if (db)
  410. channel = &db->channel;
  411. if (IS_ERR(channel))
  412. return ERR_CAST(channel);
  413. spin_lock_irqsave(&hsp->lock, flags);
  414. for (i = 0; i < mbox->num_chans; i++) {
  415. chan = &mbox->chans[i];
  416. if (!chan->con_priv) {
  417. channel->chan = chan;
  418. chan->con_priv = db;
  419. break;
  420. }
  421. chan = NULL;
  422. }
  423. spin_unlock_irqrestore(&hsp->lock, flags);
  424. return chan ?: ERR_PTR(-EBUSY);
  425. }
  426. static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
  427. const struct of_phandle_args *args)
  428. {
  429. struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
  430. unsigned int type = args->args[0], index;
  431. struct tegra_hsp_mailbox *mb;
  432. index = args->args[1] & TEGRA_HSP_SM_MASK;
  433. if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
  434. index >= hsp->num_sm)
  435. return ERR_PTR(-ENODEV);
  436. mb = &hsp->mailboxes[index];
  437. if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
  438. mb->producer = false;
  439. else
  440. mb->producer = true;
  441. return mb->channel.chan;
  442. }
  443. static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
  444. {
  445. const struct tegra_hsp_db_map *map = hsp->soc->map;
  446. struct tegra_hsp_channel *channel;
  447. while (map->name) {
  448. channel = tegra_hsp_doorbell_create(hsp, map->name,
  449. map->master, map->index);
  450. if (IS_ERR(channel))
  451. return PTR_ERR(channel);
  452. map++;
  453. }
  454. return 0;
  455. }
  456. static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
  457. {
  458. int i;
  459. hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
  460. GFP_KERNEL);
  461. if (!hsp->mailboxes)
  462. return -ENOMEM;
  463. for (i = 0; i < hsp->num_sm; i++) {
  464. struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
  465. mb->index = i;
  466. mb->channel.hsp = hsp;
  467. mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
  468. mb->channel.chan = &hsp->mbox_sm.chans[i];
  469. mb->channel.chan->con_priv = mb;
  470. }
  471. return 0;
  472. }
  473. static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
  474. {
  475. unsigned int i, irq = 0;
  476. int err;
  477. for (i = 0; i < hsp->num_si; i++) {
  478. irq = hsp->shared_irqs[i];
  479. if (irq <= 0)
  480. continue;
  481. err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
  482. dev_name(hsp->dev), hsp);
  483. if (err < 0) {
  484. dev_err(hsp->dev, "failed to request interrupt: %d\n",
  485. err);
  486. continue;
  487. }
  488. hsp->shared_irq = i;
  489. /* disable all interrupts */
  490. tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
  491. dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
  492. break;
  493. }
  494. if (i == hsp->num_si) {
  495. dev_err(hsp->dev, "failed to find available interrupt\n");
  496. return -ENOENT;
  497. }
  498. return 0;
  499. }
  500. static int tegra_hsp_probe(struct platform_device *pdev)
  501. {
  502. struct tegra_hsp *hsp;
  503. struct resource *res;
  504. unsigned int i;
  505. u32 value;
  506. int err;
  507. hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
  508. if (!hsp)
  509. return -ENOMEM;
  510. hsp->dev = &pdev->dev;
  511. hsp->soc = of_device_get_match_data(&pdev->dev);
  512. INIT_LIST_HEAD(&hsp->doorbells);
  513. spin_lock_init(&hsp->lock);
  514. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  515. hsp->regs = devm_ioremap_resource(&pdev->dev, res);
  516. if (IS_ERR(hsp->regs))
  517. return PTR_ERR(hsp->regs);
  518. value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
  519. hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
  520. hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
  521. hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
  522. hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
  523. hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
  524. err = platform_get_irq_byname_optional(pdev, "doorbell");
  525. if (err >= 0)
  526. hsp->doorbell_irq = err;
  527. if (hsp->num_si > 0) {
  528. unsigned int count = 0;
  529. hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
  530. sizeof(*hsp->shared_irqs),
  531. GFP_KERNEL);
  532. if (!hsp->shared_irqs)
  533. return -ENOMEM;
  534. for (i = 0; i < hsp->num_si; i++) {
  535. char *name;
  536. name = kasprintf(GFP_KERNEL, "shared%u", i);
  537. if (!name)
  538. return -ENOMEM;
  539. err = platform_get_irq_byname_optional(pdev, name);
  540. if (err >= 0) {
  541. hsp->shared_irqs[i] = err;
  542. count++;
  543. }
  544. kfree(name);
  545. }
  546. if (count == 0) {
  547. devm_kfree(&pdev->dev, hsp->shared_irqs);
  548. hsp->shared_irqs = NULL;
  549. }
  550. }
  551. /* setup the doorbell controller */
  552. hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
  553. hsp->mbox_db.num_chans = 32;
  554. hsp->mbox_db.dev = &pdev->dev;
  555. hsp->mbox_db.ops = &tegra_hsp_db_ops;
  556. hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
  557. sizeof(*hsp->mbox_db.chans),
  558. GFP_KERNEL);
  559. if (!hsp->mbox_db.chans)
  560. return -ENOMEM;
  561. if (hsp->doorbell_irq) {
  562. err = tegra_hsp_add_doorbells(hsp);
  563. if (err < 0) {
  564. dev_err(&pdev->dev, "failed to add doorbells: %d\n",
  565. err);
  566. return err;
  567. }
  568. }
  569. err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
  570. if (err < 0) {
  571. dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
  572. err);
  573. return err;
  574. }
  575. /* setup the shared mailbox controller */
  576. hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
  577. hsp->mbox_sm.num_chans = hsp->num_sm;
  578. hsp->mbox_sm.dev = &pdev->dev;
  579. hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
  580. hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
  581. sizeof(*hsp->mbox_sm.chans),
  582. GFP_KERNEL);
  583. if (!hsp->mbox_sm.chans)
  584. return -ENOMEM;
  585. if (hsp->shared_irqs) {
  586. err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
  587. if (err < 0) {
  588. dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
  589. err);
  590. return err;
  591. }
  592. }
  593. err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
  594. if (err < 0) {
  595. dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
  596. err);
  597. return err;
  598. }
  599. platform_set_drvdata(pdev, hsp);
  600. if (hsp->doorbell_irq) {
  601. err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
  602. tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
  603. dev_name(&pdev->dev), hsp);
  604. if (err < 0) {
  605. dev_err(&pdev->dev,
  606. "failed to request doorbell IRQ#%u: %d\n",
  607. hsp->doorbell_irq, err);
  608. return err;
  609. }
  610. }
  611. if (hsp->shared_irqs) {
  612. err = tegra_hsp_request_shared_irq(hsp);
  613. if (err < 0)
  614. return err;
  615. }
  616. return 0;
  617. }
  618. static int __maybe_unused tegra_hsp_resume(struct device *dev)
  619. {
  620. struct tegra_hsp *hsp = dev_get_drvdata(dev);
  621. unsigned int i;
  622. struct tegra_hsp_doorbell *db;
  623. list_for_each_entry(db, &hsp->doorbells, list) {
  624. if (db && db->channel.chan)
  625. tegra_hsp_doorbell_startup(db->channel.chan);
  626. }
  627. if (hsp->mailboxes) {
  628. for (i = 0; i < hsp->num_sm; i++) {
  629. struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
  630. if (mb->channel.chan->cl)
  631. tegra_hsp_mailbox_startup(mb->channel.chan);
  632. }
  633. }
  634. return 0;
  635. }
  636. static const struct dev_pm_ops tegra_hsp_pm_ops = {
  637. .resume_noirq = tegra_hsp_resume,
  638. };
  639. static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
  640. { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
  641. { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
  642. { /* sentinel */ }
  643. };
  644. static const struct tegra_hsp_soc tegra186_hsp_soc = {
  645. .map = tegra186_hsp_db_map,
  646. .has_per_mb_ie = false,
  647. };
  648. static const struct tegra_hsp_soc tegra194_hsp_soc = {
  649. .map = tegra186_hsp_db_map,
  650. .has_per_mb_ie = true,
  651. };
  652. static const struct of_device_id tegra_hsp_match[] = {
  653. { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
  654. { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
  655. { }
  656. };
  657. static struct platform_driver tegra_hsp_driver = {
  658. .driver = {
  659. .name = "tegra-hsp",
  660. .of_match_table = tegra_hsp_match,
  661. .pm = &tegra_hsp_pm_ops,
  662. },
  663. .probe = tegra_hsp_probe,
  664. };
  665. static int __init tegra_hsp_init(void)
  666. {
  667. return platform_driver_register(&tegra_hsp_driver);
  668. }
  669. core_initcall(tegra_hsp_init);