rockchip-mailbox.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/mailbox_controller.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #define MAILBOX_A2B_INTEN 0x00
  14. #define MAILBOX_A2B_STATUS 0x04
  15. #define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
  16. #define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
  17. #define MAILBOX_B2A_INTEN 0x28
  18. #define MAILBOX_B2A_STATUS 0x2C
  19. #define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
  20. #define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
  21. struct rockchip_mbox_msg {
  22. u32 cmd;
  23. int rx_size;
  24. };
  25. struct rockchip_mbox_data {
  26. int num_chans;
  27. };
  28. struct rockchip_mbox_chan {
  29. int idx;
  30. int irq;
  31. struct rockchip_mbox_msg *msg;
  32. struct rockchip_mbox *mb;
  33. };
  34. struct rockchip_mbox {
  35. struct mbox_controller mbox;
  36. struct clk *pclk;
  37. void __iomem *mbox_base;
  38. /* The maximum size of buf for each channel */
  39. u32 buf_size;
  40. struct rockchip_mbox_chan *chans;
  41. };
  42. static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
  43. {
  44. struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
  45. struct rockchip_mbox_msg *msg = data;
  46. struct rockchip_mbox_chan *chans = mb->chans;
  47. if (!msg)
  48. return -EINVAL;
  49. if (msg->rx_size > mb->buf_size) {
  50. dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
  51. mb->buf_size);
  52. return -EINVAL;
  53. }
  54. dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
  55. chans->idx, msg->cmd);
  56. mb->chans[chans->idx].msg = msg;
  57. writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
  58. writel_relaxed(msg->rx_size, mb->mbox_base +
  59. MAILBOX_A2B_DAT(chans->idx));
  60. return 0;
  61. }
  62. static int rockchip_mbox_startup(struct mbox_chan *chan)
  63. {
  64. struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
  65. /* Enable all B2A interrupts */
  66. writel_relaxed((1 << mb->mbox.num_chans) - 1,
  67. mb->mbox_base + MAILBOX_B2A_INTEN);
  68. return 0;
  69. }
  70. static void rockchip_mbox_shutdown(struct mbox_chan *chan)
  71. {
  72. struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
  73. struct rockchip_mbox_chan *chans = mb->chans;
  74. /* Disable all B2A interrupts */
  75. writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
  76. mb->chans[chans->idx].msg = NULL;
  77. }
  78. static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
  79. .send_data = rockchip_mbox_send_data,
  80. .startup = rockchip_mbox_startup,
  81. .shutdown = rockchip_mbox_shutdown,
  82. };
  83. static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
  84. {
  85. int idx;
  86. struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
  87. u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
  88. for (idx = 0; idx < mb->mbox.num_chans; idx++) {
  89. if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
  90. /* Clear mbox interrupt */
  91. writel_relaxed(1 << idx,
  92. mb->mbox_base + MAILBOX_B2A_STATUS);
  93. return IRQ_WAKE_THREAD;
  94. }
  95. }
  96. return IRQ_NONE;
  97. }
  98. static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
  99. {
  100. int idx;
  101. struct rockchip_mbox_msg *msg = NULL;
  102. struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
  103. for (idx = 0; idx < mb->mbox.num_chans; idx++) {
  104. if (irq != mb->chans[idx].irq)
  105. continue;
  106. msg = mb->chans[idx].msg;
  107. if (!msg) {
  108. dev_err(mb->mbox.dev,
  109. "Chan[%d]: B2A message is NULL\n", idx);
  110. break; /* spurious */
  111. }
  112. mbox_chan_received_data(&mb->mbox.chans[idx], msg);
  113. mb->chans[idx].msg = NULL;
  114. dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
  115. idx, msg->cmd);
  116. break;
  117. }
  118. return IRQ_HANDLED;
  119. }
  120. static const struct rockchip_mbox_data rk3368_drv_data = {
  121. .num_chans = 4,
  122. };
  123. static const struct of_device_id rockchip_mbox_of_match[] = {
  124. { .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
  125. { },
  126. };
  127. MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
  128. static int rockchip_mbox_probe(struct platform_device *pdev)
  129. {
  130. struct rockchip_mbox *mb;
  131. const struct of_device_id *match;
  132. const struct rockchip_mbox_data *drv_data;
  133. struct resource *res;
  134. int ret, irq, i;
  135. if (!pdev->dev.of_node)
  136. return -ENODEV;
  137. match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
  138. drv_data = (const struct rockchip_mbox_data *)match->data;
  139. mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
  140. if (!mb)
  141. return -ENOMEM;
  142. mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
  143. sizeof(*mb->chans), GFP_KERNEL);
  144. if (!mb->chans)
  145. return -ENOMEM;
  146. mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
  147. sizeof(*mb->mbox.chans), GFP_KERNEL);
  148. if (!mb->mbox.chans)
  149. return -ENOMEM;
  150. platform_set_drvdata(pdev, mb);
  151. mb->mbox.dev = &pdev->dev;
  152. mb->mbox.num_chans = drv_data->num_chans;
  153. mb->mbox.ops = &rockchip_mbox_chan_ops;
  154. mb->mbox.txdone_irq = true;
  155. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  156. if (!res)
  157. return -ENODEV;
  158. mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
  159. if (IS_ERR(mb->mbox_base))
  160. return PTR_ERR(mb->mbox_base);
  161. /* Each channel has two buffers for A2B and B2A */
  162. mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2);
  163. mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
  164. if (IS_ERR(mb->pclk)) {
  165. ret = PTR_ERR(mb->pclk);
  166. dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
  167. ret);
  168. return ret;
  169. }
  170. ret = clk_prepare_enable(mb->pclk);
  171. if (ret) {
  172. dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
  173. return ret;
  174. }
  175. for (i = 0; i < mb->mbox.num_chans; i++) {
  176. irq = platform_get_irq(pdev, i);
  177. if (irq < 0)
  178. return irq;
  179. ret = devm_request_threaded_irq(&pdev->dev, irq,
  180. rockchip_mbox_irq,
  181. rockchip_mbox_isr, IRQF_ONESHOT,
  182. dev_name(&pdev->dev), mb);
  183. if (ret < 0)
  184. return ret;
  185. mb->chans[i].idx = i;
  186. mb->chans[i].irq = irq;
  187. mb->chans[i].mb = mb;
  188. mb->chans[i].msg = NULL;
  189. }
  190. ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
  191. if (ret < 0)
  192. dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
  193. return ret;
  194. }
  195. static struct platform_driver rockchip_mbox_driver = {
  196. .probe = rockchip_mbox_probe,
  197. .driver = {
  198. .name = "rockchip-mailbox",
  199. .of_match_table = of_match_ptr(rockchip_mbox_of_match),
  200. },
  201. };
  202. module_platform_driver(rockchip_mbox_driver);
  203. MODULE_LICENSE("GPL v2");
  204. MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
  205. MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
  206. MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");