platform_mhu.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2016 BayLibre SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Synchronised with arm_mhu.c from :
  6. * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
  7. * Copyright (C) 2015 Linaro Ltd.
  8. * Author: Jassi Brar <jaswinder.singh@linaro.org>
  9. */
  10. #include <linux/interrupt.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/mutex.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/mailbox_controller.h>
  20. #define INTR_SET_OFS 0x0
  21. #define INTR_STAT_OFS 0x4
  22. #define INTR_CLR_OFS 0x8
  23. #define MHU_SEC_OFFSET 0x0
  24. #define MHU_LP_OFFSET 0xc
  25. #define MHU_HP_OFFSET 0x18
  26. #define TX_REG_OFFSET 0x24
  27. #define MHU_CHANS 3
  28. struct platform_mhu_link {
  29. int irq;
  30. void __iomem *tx_reg;
  31. void __iomem *rx_reg;
  32. };
  33. struct platform_mhu {
  34. void __iomem *base;
  35. struct platform_mhu_link mlink[MHU_CHANS];
  36. struct mbox_chan chan[MHU_CHANS];
  37. struct mbox_controller mbox;
  38. };
  39. static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
  40. {
  41. struct mbox_chan *chan = p;
  42. struct platform_mhu_link *mlink = chan->con_priv;
  43. u32 val;
  44. val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
  45. if (!val)
  46. return IRQ_NONE;
  47. mbox_chan_received_data(chan, (void *)&val);
  48. writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
  49. return IRQ_HANDLED;
  50. }
  51. static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
  52. {
  53. struct platform_mhu_link *mlink = chan->con_priv;
  54. u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  55. return (val == 0);
  56. }
  57. static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
  58. {
  59. struct platform_mhu_link *mlink = chan->con_priv;
  60. u32 *arg = data;
  61. writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
  62. return 0;
  63. }
  64. static int platform_mhu_startup(struct mbox_chan *chan)
  65. {
  66. struct platform_mhu_link *mlink = chan->con_priv;
  67. u32 val;
  68. int ret;
  69. val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  70. writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
  71. ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
  72. IRQF_SHARED, "platform_mhu_link", chan);
  73. if (ret) {
  74. dev_err(chan->mbox->dev,
  75. "Unable to acquire IRQ %d\n", mlink->irq);
  76. return ret;
  77. }
  78. return 0;
  79. }
  80. static void platform_mhu_shutdown(struct mbox_chan *chan)
  81. {
  82. struct platform_mhu_link *mlink = chan->con_priv;
  83. free_irq(mlink->irq, chan);
  84. }
  85. static const struct mbox_chan_ops platform_mhu_ops = {
  86. .send_data = platform_mhu_send_data,
  87. .startup = platform_mhu_startup,
  88. .shutdown = platform_mhu_shutdown,
  89. .last_tx_done = platform_mhu_last_tx_done,
  90. };
  91. static int platform_mhu_probe(struct platform_device *pdev)
  92. {
  93. int i, err;
  94. struct platform_mhu *mhu;
  95. struct device *dev = &pdev->dev;
  96. struct resource *res;
  97. int platform_mhu_reg[MHU_CHANS] = {
  98. MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
  99. };
  100. /* Allocate memory for device */
  101. mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
  102. if (!mhu)
  103. return -ENOMEM;
  104. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  105. mhu->base = devm_ioremap_resource(dev, res);
  106. if (IS_ERR(mhu->base)) {
  107. dev_err(dev, "ioremap failed\n");
  108. return PTR_ERR(mhu->base);
  109. }
  110. for (i = 0; i < MHU_CHANS; i++) {
  111. mhu->chan[i].con_priv = &mhu->mlink[i];
  112. mhu->mlink[i].irq = platform_get_irq(pdev, i);
  113. if (mhu->mlink[i].irq < 0) {
  114. dev_err(dev, "failed to get irq%d\n", i);
  115. return mhu->mlink[i].irq;
  116. }
  117. mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
  118. mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
  119. }
  120. mhu->mbox.dev = dev;
  121. mhu->mbox.chans = &mhu->chan[0];
  122. mhu->mbox.num_chans = MHU_CHANS;
  123. mhu->mbox.ops = &platform_mhu_ops;
  124. mhu->mbox.txdone_irq = false;
  125. mhu->mbox.txdone_poll = true;
  126. mhu->mbox.txpoll_period = 1;
  127. platform_set_drvdata(pdev, mhu);
  128. err = devm_mbox_controller_register(dev, &mhu->mbox);
  129. if (err) {
  130. dev_err(dev, "Failed to register mailboxes %d\n", err);
  131. return err;
  132. }
  133. dev_info(dev, "Platform MHU Mailbox registered\n");
  134. return 0;
  135. }
  136. static const struct of_device_id platform_mhu_dt_ids[] = {
  137. { .compatible = "amlogic,meson-gxbb-mhu", },
  138. { /* sentinel */ },
  139. };
  140. MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
  141. static struct platform_driver platform_mhu_driver = {
  142. .probe = platform_mhu_probe,
  143. .driver = {
  144. .name = "platform-mhu",
  145. .of_match_table = platform_mhu_dt_ids,
  146. },
  147. };
  148. module_platform_driver(platform_mhu_driver);
  149. MODULE_LICENSE("GPL v2");
  150. MODULE_ALIAS("platform:platform-mhu");
  151. MODULE_DESCRIPTION("Platform MHU Driver");
  152. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");