leds-ss4200.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SS4200-E Hardware API
  4. * Copyright (c) 2009, Intel Corporation.
  5. * Copyright IBM Corporation, 2009
  6. *
  7. * Author: Dave Hansen <dave@sr71.net>
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/dmi.h>
  11. #include <linux/init.h>
  12. #include <linux/ioport.h>
  13. #include <linux/kernel.h>
  14. #include <linux/leds.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/types.h>
  18. #include <linux/uaccess.h>
  19. MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");
  20. MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");
  21. MODULE_LICENSE("GPL");
  22. /*
  23. * ICH7 LPC/GPIO PCI Config register offsets
  24. */
  25. #define PMBASE 0x040
  26. #define GPIO_BASE 0x048
  27. #define GPIO_CTRL 0x04c
  28. #define GPIO_EN 0x010
  29. /*
  30. * The ICH7 GPIO register block is 64 bytes in size.
  31. */
  32. #define ICH7_GPIO_SIZE 64
  33. /*
  34. * Define register offsets within the ICH7 register block.
  35. */
  36. #define GPIO_USE_SEL 0x000
  37. #define GP_IO_SEL 0x004
  38. #define GP_LVL 0x00c
  39. #define GPO_BLINK 0x018
  40. #define GPI_INV 0x030
  41. #define GPIO_USE_SEL2 0x034
  42. #define GP_IO_SEL2 0x038
  43. #define GP_LVL2 0x03c
  44. /*
  45. * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
  46. */
  47. static const struct pci_device_id ich7_lpc_pci_id[] = {
  48. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },
  49. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },
  50. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },
  51. { } /* NULL entry */
  52. };
  53. MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);
  54. static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)
  55. {
  56. pr_info("detected '%s'\n", id->ident);
  57. return 1;
  58. }
  59. static bool nodetect;
  60. module_param_named(nodetect, nodetect, bool, 0);
  61. MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");
  62. /*
  63. * struct nas_led_whitelist - List of known good models
  64. *
  65. * Contains the known good models this driver is compatible with.
  66. * When adding a new model try to be as strict as possible. This
  67. * makes it possible to keep the false positives (the model is
  68. * detected as working, but in reality it is not) as low as
  69. * possible.
  70. */
  71. static const struct dmi_system_id nas_led_whitelist[] __initconst = {
  72. {
  73. .callback = ss4200_led_dmi_callback,
  74. .ident = "Intel SS4200-E",
  75. .matches = {
  76. DMI_MATCH(DMI_SYS_VENDOR, "Intel"),
  77. DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),
  78. DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
  79. }
  80. },
  81. {
  82. /*
  83. * FUJITSU SIEMENS SCALEO Home Server/SS4200-E
  84. * BIOS V090L 12/19/2007
  85. */
  86. .callback = ss4200_led_dmi_callback,
  87. .ident = "Fujitsu Siemens SCALEO Home Server",
  88. .matches = {
  89. DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
  90. DMI_MATCH(DMI_PRODUCT_NAME, "SCALEO Home Server"),
  91. DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
  92. }
  93. },
  94. {}
  95. };
  96. /*
  97. * Base I/O address assigned to the Power Management register block
  98. */
  99. static u32 g_pm_io_base;
  100. /*
  101. * Base I/O address assigned to the ICH7 GPIO register block
  102. */
  103. static u32 nas_gpio_io_base;
  104. /*
  105. * When we successfully register a region, we are returned a resource.
  106. * We use these to identify which regions we need to release on our way
  107. * back out.
  108. */
  109. static struct resource *gp_gpio_resource;
  110. struct nasgpio_led {
  111. char *name;
  112. u32 gpio_bit;
  113. struct led_classdev led_cdev;
  114. };
  115. /*
  116. * gpio_bit(s) are the ICH7 GPIO bit assignments
  117. */
  118. static struct nasgpio_led nasgpio_leds[] = {
  119. { .name = "hdd1:blue:sata", .gpio_bit = 0 },
  120. { .name = "hdd1:amber:sata", .gpio_bit = 1 },
  121. { .name = "hdd2:blue:sata", .gpio_bit = 2 },
  122. { .name = "hdd2:amber:sata", .gpio_bit = 3 },
  123. { .name = "hdd3:blue:sata", .gpio_bit = 4 },
  124. { .name = "hdd3:amber:sata", .gpio_bit = 5 },
  125. { .name = "hdd4:blue:sata", .gpio_bit = 6 },
  126. { .name = "hdd4:amber:sata", .gpio_bit = 7 },
  127. { .name = "power:blue:power", .gpio_bit = 27},
  128. { .name = "power:amber:power", .gpio_bit = 28},
  129. };
  130. #define NAS_RECOVERY 0x00000400 /* GPIO10 */
  131. static struct nasgpio_led *
  132. led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)
  133. {
  134. return container_of(led_cdev, struct nasgpio_led, led_cdev);
  135. }
  136. static struct nasgpio_led *get_led_named(char *name)
  137. {
  138. int i;
  139. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
  140. if (strcmp(nasgpio_leds[i].name, name))
  141. continue;
  142. return &nasgpio_leds[i];
  143. }
  144. return NULL;
  145. }
  146. /*
  147. * This protects access to the gpio ports.
  148. */
  149. static DEFINE_SPINLOCK(nasgpio_gpio_lock);
  150. /*
  151. * There are two gpio ports, one for blinking and the other
  152. * for power. @port tells us if we're doing blinking or
  153. * power control.
  154. *
  155. * Caller must hold nasgpio_gpio_lock
  156. */
  157. static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,
  158. u32 port, u32 value)
  159. {
  160. struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
  161. u32 gpio_out;
  162. gpio_out = inl(nas_gpio_io_base + port);
  163. if (value)
  164. gpio_out |= (1<<led->gpio_bit);
  165. else
  166. gpio_out &= ~(1<<led->gpio_bit);
  167. outl(gpio_out, nas_gpio_io_base + port);
  168. }
  169. static void nasgpio_led_set_attr(struct led_classdev *led_cdev,
  170. u32 port, u32 value)
  171. {
  172. spin_lock(&nasgpio_gpio_lock);
  173. __nasgpio_led_set_attr(led_cdev, port, value);
  174. spin_unlock(&nasgpio_gpio_lock);
  175. }
  176. static u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)
  177. {
  178. struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
  179. u32 gpio_in;
  180. spin_lock(&nasgpio_gpio_lock);
  181. gpio_in = inl(nas_gpio_io_base + port);
  182. spin_unlock(&nasgpio_gpio_lock);
  183. if (gpio_in & (1<<led->gpio_bit))
  184. return 1;
  185. return 0;
  186. }
  187. /*
  188. * There is actual brightness control in the hardware,
  189. * but it is via smbus commands and not implemented
  190. * in this driver.
  191. */
  192. static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,
  193. enum led_brightness brightness)
  194. {
  195. u32 setting = 0;
  196. if (brightness >= LED_HALF)
  197. setting = 1;
  198. /*
  199. * Hold the lock across both operations. This ensures
  200. * consistency so that both the "turn off blinking"
  201. * and "turn light off" operations complete as a set.
  202. */
  203. spin_lock(&nasgpio_gpio_lock);
  204. /*
  205. * LED class documentation asks that past blink state
  206. * be disabled when brightness is turned to zero.
  207. */
  208. if (brightness == 0)
  209. __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);
  210. __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);
  211. spin_unlock(&nasgpio_gpio_lock);
  212. }
  213. static int nasgpio_led_set_blink(struct led_classdev *led_cdev,
  214. unsigned long *delay_on,
  215. unsigned long *delay_off)
  216. {
  217. u32 setting = 1;
  218. if (!(*delay_on == 0 && *delay_off == 0) &&
  219. !(*delay_on == 500 && *delay_off == 500))
  220. return -EINVAL;
  221. /*
  222. * These are very approximate.
  223. */
  224. *delay_on = 500;
  225. *delay_off = 500;
  226. nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);
  227. return 0;
  228. }
  229. /*
  230. * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have
  231. * already taken care of this, but we will do so in a non destructive manner
  232. * so that we have what we need whether the BIOS did it or not.
  233. */
  234. static int ich7_gpio_init(struct device *dev)
  235. {
  236. int i;
  237. u32 config_data = 0;
  238. u32 all_nas_led = 0;
  239. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
  240. all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);
  241. spin_lock(&nasgpio_gpio_lock);
  242. /*
  243. * We need to enable all of the GPIO lines used by the NAS box,
  244. * so we will read the current Use Selection and add our usage
  245. * to it. This should be benign with regard to the original
  246. * BIOS configuration.
  247. */
  248. config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
  249. dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);
  250. config_data |= all_nas_led + NAS_RECOVERY;
  251. outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);
  252. config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
  253. dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);
  254. /*
  255. * The LED GPIO outputs need to be configured for output, so we
  256. * will ensure that all LED lines are cleared for output and the
  257. * RECOVERY line ready for input. This too should be benign with
  258. * regard to BIOS configuration.
  259. */
  260. config_data = inl(nas_gpio_io_base + GP_IO_SEL);
  261. dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",
  262. config_data);
  263. config_data &= ~all_nas_led;
  264. config_data |= NAS_RECOVERY;
  265. outl(config_data, nas_gpio_io_base + GP_IO_SEL);
  266. config_data = inl(nas_gpio_io_base + GP_IO_SEL);
  267. dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);
  268. /*
  269. * In our final system, the BIOS will initialize the state of all
  270. * of the LEDs. For now, we turn them all off (or Low).
  271. */
  272. config_data = inl(nas_gpio_io_base + GP_LVL);
  273. dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);
  274. /*
  275. * In our final system, the BIOS will initialize the blink state of all
  276. * of the LEDs. For now, we turn blink off for all of them.
  277. */
  278. config_data = inl(nas_gpio_io_base + GPO_BLINK);
  279. dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);
  280. /*
  281. * At this moment, I am unsure if anything needs to happen with GPI_INV
  282. */
  283. config_data = inl(nas_gpio_io_base + GPI_INV);
  284. dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);
  285. spin_unlock(&nasgpio_gpio_lock);
  286. return 0;
  287. }
  288. static void ich7_lpc_cleanup(struct device *dev)
  289. {
  290. /*
  291. * If we were given exclusive use of the GPIO
  292. * I/O Address range, we must return it.
  293. */
  294. if (gp_gpio_resource) {
  295. dev_dbg(dev, ": Releasing GPIO I/O addresses\n");
  296. release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);
  297. gp_gpio_resource = NULL;
  298. }
  299. }
  300. /*
  301. * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
  302. * so we can retrive the required operational information and prepare the GPIO.
  303. */
  304. static struct pci_dev *nas_gpio_pci_dev;
  305. static int ich7_lpc_probe(struct pci_dev *dev,
  306. const struct pci_device_id *id)
  307. {
  308. int status;
  309. u32 gc = 0;
  310. status = pci_enable_device(dev);
  311. if (status) {
  312. dev_err(&dev->dev, "pci_enable_device failed\n");
  313. return -EIO;
  314. }
  315. nas_gpio_pci_dev = dev;
  316. status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);
  317. if (status)
  318. goto out;
  319. g_pm_io_base &= 0x00000ff80;
  320. status = pci_read_config_dword(dev, GPIO_CTRL, &gc);
  321. if (!(GPIO_EN & gc)) {
  322. status = -EEXIST;
  323. dev_info(&dev->dev,
  324. "ERROR: The LPC GPIO Block has not been enabled.\n");
  325. goto out;
  326. }
  327. status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
  328. if (0 > status) {
  329. dev_info(&dev->dev, "Unable to read GPIOBASE.\n");
  330. goto out;
  331. }
  332. dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);
  333. nas_gpio_io_base &= 0x00000ffc0;
  334. /*
  335. * Insure that we have exclusive access to the GPIO I/O address range.
  336. */
  337. gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,
  338. KBUILD_MODNAME);
  339. if (NULL == gp_gpio_resource) {
  340. dev_info(&dev->dev,
  341. "ERROR Unable to register GPIO I/O addresses.\n");
  342. status = -1;
  343. goto out;
  344. }
  345. /*
  346. * Initialize the GPIO for NAS/Home Server Use
  347. */
  348. ich7_gpio_init(&dev->dev);
  349. out:
  350. if (status) {
  351. ich7_lpc_cleanup(&dev->dev);
  352. pci_disable_device(dev);
  353. }
  354. return status;
  355. }
  356. static void ich7_lpc_remove(struct pci_dev *dev)
  357. {
  358. ich7_lpc_cleanup(&dev->dev);
  359. pci_disable_device(dev);
  360. }
  361. /*
  362. * pci_driver structure passed to the PCI modules
  363. */
  364. static struct pci_driver nas_gpio_pci_driver = {
  365. .name = KBUILD_MODNAME,
  366. .id_table = ich7_lpc_pci_id,
  367. .probe = ich7_lpc_probe,
  368. .remove = ich7_lpc_remove,
  369. };
  370. static struct led_classdev *get_classdev_for_led_nr(int nr)
  371. {
  372. struct nasgpio_led *nas_led = &nasgpio_leds[nr];
  373. struct led_classdev *led = &nas_led->led_cdev;
  374. return led;
  375. }
  376. static void set_power_light_amber_noblink(void)
  377. {
  378. struct nasgpio_led *amber = get_led_named("power:amber:power");
  379. struct nasgpio_led *blue = get_led_named("power:blue:power");
  380. if (!amber || !blue)
  381. return;
  382. /*
  383. * LED_OFF implies disabling future blinking
  384. */
  385. pr_debug("setting blue off and amber on\n");
  386. nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);
  387. nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);
  388. }
  389. static ssize_t nas_led_blink_show(struct device *dev,
  390. struct device_attribute *attr, char *buf)
  391. {
  392. struct led_classdev *led = dev_get_drvdata(dev);
  393. int blinking = 0;
  394. if (nasgpio_led_get_attr(led, GPO_BLINK))
  395. blinking = 1;
  396. return sprintf(buf, "%u\n", blinking);
  397. }
  398. static ssize_t nas_led_blink_store(struct device *dev,
  399. struct device_attribute *attr,
  400. const char *buf, size_t size)
  401. {
  402. int ret;
  403. struct led_classdev *led = dev_get_drvdata(dev);
  404. unsigned long blink_state;
  405. ret = kstrtoul(buf, 10, &blink_state);
  406. if (ret)
  407. return ret;
  408. nasgpio_led_set_attr(led, GPO_BLINK, blink_state);
  409. return size;
  410. }
  411. static DEVICE_ATTR(blink, 0644, nas_led_blink_show, nas_led_blink_store);
  412. static struct attribute *nasgpio_led_attrs[] = {
  413. &dev_attr_blink.attr,
  414. NULL
  415. };
  416. ATTRIBUTE_GROUPS(nasgpio_led);
  417. static int register_nasgpio_led(int led_nr)
  418. {
  419. int ret;
  420. struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];
  421. struct led_classdev *led = get_classdev_for_led_nr(led_nr);
  422. led->name = nas_led->name;
  423. led->brightness = LED_OFF;
  424. if (nasgpio_led_get_attr(led, GP_LVL))
  425. led->brightness = LED_FULL;
  426. led->brightness_set = nasgpio_led_set_brightness;
  427. led->blink_set = nasgpio_led_set_blink;
  428. led->groups = nasgpio_led_groups;
  429. ret = led_classdev_register(&nas_gpio_pci_dev->dev, led);
  430. if (ret)
  431. return ret;
  432. return 0;
  433. }
  434. static void unregister_nasgpio_led(int led_nr)
  435. {
  436. struct led_classdev *led = get_classdev_for_led_nr(led_nr);
  437. led_classdev_unregister(led);
  438. }
  439. /*
  440. * module load/initialization
  441. */
  442. static int __init nas_gpio_init(void)
  443. {
  444. int i;
  445. int ret = 0;
  446. int nr_devices = 0;
  447. nr_devices = dmi_check_system(nas_led_whitelist);
  448. if (nodetect) {
  449. pr_info("skipping hardware autodetection\n");
  450. pr_info("Please send 'dmidecode' output to dave@sr71.net\n");
  451. nr_devices++;
  452. }
  453. if (nr_devices <= 0) {
  454. pr_info("no LED devices found\n");
  455. return -ENODEV;
  456. }
  457. pr_info("registering PCI driver\n");
  458. ret = pci_register_driver(&nas_gpio_pci_driver);
  459. if (ret)
  460. return ret;
  461. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
  462. ret = register_nasgpio_led(i);
  463. if (ret)
  464. goto out_err;
  465. }
  466. /*
  467. * When the system powers on, the BIOS leaves the power
  468. * light blue and blinking. This will turn it solid
  469. * amber once the driver is loaded.
  470. */
  471. set_power_light_amber_noblink();
  472. return 0;
  473. out_err:
  474. for (i--; i >= 0; i--)
  475. unregister_nasgpio_led(i);
  476. pci_unregister_driver(&nas_gpio_pci_driver);
  477. return ret;
  478. }
  479. /*
  480. * module unload
  481. */
  482. static void __exit nas_gpio_exit(void)
  483. {
  484. int i;
  485. pr_info("Unregistering driver\n");
  486. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
  487. unregister_nasgpio_led(i);
  488. pci_unregister_driver(&nas_gpio_pci_driver);
  489. }
  490. module_init(nas_gpio_init);
  491. module_exit(nas_gpio_exit);