spear-shirq.c 7.3 KB

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  1. /*
  2. * SPEAr platform shared irq layer source file
  3. *
  4. * Copyright (C) 2009-2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * Copyright (C) 2012 ST Microelectronics
  8. * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/err.h>
  16. #include <linux/export.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqchip.h>
  21. #include <linux/irqdomain.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/spinlock.h>
  26. /*
  27. * struct spear_shirq: shared irq structure
  28. *
  29. * base: Base register address
  30. * status_reg: Status register offset for chained interrupt handler
  31. * mask_reg: Mask register offset for irq chip
  32. * mask: Mask to apply to the status register
  33. * virq_base: Base virtual interrupt number
  34. * nr_irqs: Number of interrupts handled by this block
  35. * offset: Bit offset of the first interrupt
  36. * irq_chip: Interrupt controller chip used for this instance,
  37. * if NULL group is disabled, but accounted
  38. */
  39. struct spear_shirq {
  40. void __iomem *base;
  41. u32 status_reg;
  42. u32 mask_reg;
  43. u32 mask;
  44. u32 virq_base;
  45. u32 nr_irqs;
  46. u32 offset;
  47. struct irq_chip *irq_chip;
  48. };
  49. /* spear300 shared irq registers offsets and masks */
  50. #define SPEAR300_INT_ENB_MASK_REG 0x54
  51. #define SPEAR300_INT_STS_MASK_REG 0x58
  52. static DEFINE_RAW_SPINLOCK(shirq_lock);
  53. static void shirq_irq_mask(struct irq_data *d)
  54. {
  55. struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
  56. u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
  57. u32 __iomem *reg = shirq->base + shirq->mask_reg;
  58. raw_spin_lock(&shirq_lock);
  59. val = readl(reg) & ~(0x1 << shift);
  60. writel(val, reg);
  61. raw_spin_unlock(&shirq_lock);
  62. }
  63. static void shirq_irq_unmask(struct irq_data *d)
  64. {
  65. struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
  66. u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
  67. u32 __iomem *reg = shirq->base + shirq->mask_reg;
  68. raw_spin_lock(&shirq_lock);
  69. val = readl(reg) | (0x1 << shift);
  70. writel(val, reg);
  71. raw_spin_unlock(&shirq_lock);
  72. }
  73. static struct irq_chip shirq_chip = {
  74. .name = "spear-shirq",
  75. .irq_mask = shirq_irq_mask,
  76. .irq_unmask = shirq_irq_unmask,
  77. };
  78. static struct spear_shirq spear300_shirq_ras1 = {
  79. .offset = 0,
  80. .nr_irqs = 9,
  81. .mask = ((0x1 << 9) - 1) << 0,
  82. .irq_chip = &shirq_chip,
  83. .status_reg = SPEAR300_INT_STS_MASK_REG,
  84. .mask_reg = SPEAR300_INT_ENB_MASK_REG,
  85. };
  86. static struct spear_shirq *spear300_shirq_blocks[] = {
  87. &spear300_shirq_ras1,
  88. };
  89. /* spear310 shared irq registers offsets and masks */
  90. #define SPEAR310_INT_STS_MASK_REG 0x04
  91. static struct spear_shirq spear310_shirq_ras1 = {
  92. .offset = 0,
  93. .nr_irqs = 8,
  94. .mask = ((0x1 << 8) - 1) << 0,
  95. .irq_chip = &dummy_irq_chip,
  96. .status_reg = SPEAR310_INT_STS_MASK_REG,
  97. };
  98. static struct spear_shirq spear310_shirq_ras2 = {
  99. .offset = 8,
  100. .nr_irqs = 5,
  101. .mask = ((0x1 << 5) - 1) << 8,
  102. .irq_chip = &dummy_irq_chip,
  103. .status_reg = SPEAR310_INT_STS_MASK_REG,
  104. };
  105. static struct spear_shirq spear310_shirq_ras3 = {
  106. .offset = 13,
  107. .nr_irqs = 1,
  108. .mask = ((0x1 << 1) - 1) << 13,
  109. .irq_chip = &dummy_irq_chip,
  110. .status_reg = SPEAR310_INT_STS_MASK_REG,
  111. };
  112. static struct spear_shirq spear310_shirq_intrcomm_ras = {
  113. .offset = 14,
  114. .nr_irqs = 3,
  115. .mask = ((0x1 << 3) - 1) << 14,
  116. .irq_chip = &dummy_irq_chip,
  117. .status_reg = SPEAR310_INT_STS_MASK_REG,
  118. };
  119. static struct spear_shirq *spear310_shirq_blocks[] = {
  120. &spear310_shirq_ras1,
  121. &spear310_shirq_ras2,
  122. &spear310_shirq_ras3,
  123. &spear310_shirq_intrcomm_ras,
  124. };
  125. /* spear320 shared irq registers offsets and masks */
  126. #define SPEAR320_INT_STS_MASK_REG 0x04
  127. #define SPEAR320_INT_CLR_MASK_REG 0x04
  128. #define SPEAR320_INT_ENB_MASK_REG 0x08
  129. static struct spear_shirq spear320_shirq_ras3 = {
  130. .offset = 0,
  131. .nr_irqs = 7,
  132. .mask = ((0x1 << 7) - 1) << 0,
  133. };
  134. static struct spear_shirq spear320_shirq_ras1 = {
  135. .offset = 7,
  136. .nr_irqs = 3,
  137. .mask = ((0x1 << 3) - 1) << 7,
  138. .irq_chip = &dummy_irq_chip,
  139. .status_reg = SPEAR320_INT_STS_MASK_REG,
  140. };
  141. static struct spear_shirq spear320_shirq_ras2 = {
  142. .offset = 10,
  143. .nr_irqs = 1,
  144. .mask = ((0x1 << 1) - 1) << 10,
  145. .irq_chip = &dummy_irq_chip,
  146. .status_reg = SPEAR320_INT_STS_MASK_REG,
  147. };
  148. static struct spear_shirq spear320_shirq_intrcomm_ras = {
  149. .offset = 11,
  150. .nr_irqs = 11,
  151. .mask = ((0x1 << 11) - 1) << 11,
  152. .irq_chip = &dummy_irq_chip,
  153. .status_reg = SPEAR320_INT_STS_MASK_REG,
  154. };
  155. static struct spear_shirq *spear320_shirq_blocks[] = {
  156. &spear320_shirq_ras3,
  157. &spear320_shirq_ras1,
  158. &spear320_shirq_ras2,
  159. &spear320_shirq_intrcomm_ras,
  160. };
  161. static void shirq_handler(struct irq_desc *desc)
  162. {
  163. struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
  164. u32 pend;
  165. pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
  166. pend >>= shirq->offset;
  167. while (pend) {
  168. int irq = __ffs(pend);
  169. pend &= ~(0x1 << irq);
  170. generic_handle_irq(shirq->virq_base + irq);
  171. }
  172. }
  173. static void __init spear_shirq_register(struct spear_shirq *shirq,
  174. int parent_irq)
  175. {
  176. int i;
  177. if (!shirq->irq_chip)
  178. return;
  179. irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
  180. for (i = 0; i < shirq->nr_irqs; i++) {
  181. irq_set_chip_and_handler(shirq->virq_base + i,
  182. shirq->irq_chip, handle_simple_irq);
  183. irq_set_chip_data(shirq->virq_base + i, shirq);
  184. }
  185. }
  186. static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
  187. struct device_node *np)
  188. {
  189. int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
  190. struct irq_domain *shirq_domain;
  191. void __iomem *base;
  192. base = of_iomap(np, 0);
  193. if (!base) {
  194. pr_err("%s: failed to map shirq registers\n", __func__);
  195. return -ENXIO;
  196. }
  197. for (i = 0; i < block_nr; i++)
  198. nr_irqs += shirq_blocks[i]->nr_irqs;
  199. virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
  200. if (virq_base < 0) {
  201. pr_err("%s: irq desc alloc failed\n", __func__);
  202. goto err_unmap;
  203. }
  204. shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
  205. &irq_domain_simple_ops, NULL);
  206. if (WARN_ON(!shirq_domain)) {
  207. pr_warn("%s: irq domain init failed\n", __func__);
  208. goto err_free_desc;
  209. }
  210. for (i = 0; i < block_nr; i++) {
  211. shirq_blocks[i]->base = base;
  212. shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
  213. hwirq);
  214. parent_irq = irq_of_parse_and_map(np, i);
  215. spear_shirq_register(shirq_blocks[i], parent_irq);
  216. hwirq += shirq_blocks[i]->nr_irqs;
  217. }
  218. return 0;
  219. err_free_desc:
  220. irq_free_descs(virq_base, nr_irqs);
  221. err_unmap:
  222. iounmap(base);
  223. return -ENXIO;
  224. }
  225. static int __init spear300_shirq_of_init(struct device_node *np,
  226. struct device_node *parent)
  227. {
  228. return shirq_init(spear300_shirq_blocks,
  229. ARRAY_SIZE(spear300_shirq_blocks), np);
  230. }
  231. IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
  232. static int __init spear310_shirq_of_init(struct device_node *np,
  233. struct device_node *parent)
  234. {
  235. return shirq_init(spear310_shirq_blocks,
  236. ARRAY_SIZE(spear310_shirq_blocks), np);
  237. }
  238. IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
  239. static int __init spear320_shirq_of_init(struct device_node *np,
  240. struct device_node *parent)
  241. {
  242. return shirq_init(spear320_shirq_blocks,
  243. ARRAY_SIZE(spear320_shirq_blocks), np);
  244. }
  245. IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);