qcom-pdc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/err.h>
  6. #include <linux/init.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_device.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/soc/qcom/irq.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/slab.h>
  21. #include <linux/types.h>
  22. #include <linux/qcom_scm.h>
  23. #define PDC_MAX_IRQS 168
  24. #define PDC_MAX_GPIO_IRQS 256
  25. #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
  26. #define ENABLE_INTR(reg, intr) (reg | (1 << intr))
  27. #define IRQ_ENABLE_BANK 0x10
  28. #define IRQ_i_CFG 0x110
  29. #define PDC_NO_PARENT_IRQ ~0UL
  30. struct pdc_pin_region {
  31. u32 pin_base;
  32. u32 parent_base;
  33. u32 cnt;
  34. };
  35. struct spi_cfg_regs {
  36. union {
  37. u64 start;
  38. void __iomem *base;
  39. };
  40. resource_size_t size;
  41. bool scm_io;
  42. };
  43. static DEFINE_RAW_SPINLOCK(pdc_lock);
  44. static void __iomem *pdc_base;
  45. static struct pdc_pin_region *pdc_region;
  46. static int pdc_region_cnt;
  47. static struct spi_cfg_regs *spi_cfg;
  48. static void pdc_reg_write(int reg, u32 i, u32 val)
  49. {
  50. writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  51. }
  52. static u32 pdc_reg_read(int reg, u32 i)
  53. {
  54. return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  55. }
  56. static void pdc_enable_intr(struct irq_data *d, bool on)
  57. {
  58. int pin_out = d->hwirq;
  59. unsigned long flags;
  60. u32 index, mask;
  61. u32 enable;
  62. index = pin_out / 32;
  63. mask = pin_out % 32;
  64. raw_spin_lock_irqsave(&pdc_lock, flags);
  65. enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  66. enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
  67. pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  68. raw_spin_unlock_irqrestore(&pdc_lock, flags);
  69. }
  70. static void qcom_pdc_gic_disable(struct irq_data *d)
  71. {
  72. pdc_enable_intr(d, false);
  73. irq_chip_disable_parent(d);
  74. }
  75. static void qcom_pdc_gic_enable(struct irq_data *d)
  76. {
  77. pdc_enable_intr(d, true);
  78. irq_chip_enable_parent(d);
  79. }
  80. static u32 __spi_pin_read(unsigned int pin)
  81. {
  82. void __iomem *cfg_reg = spi_cfg->base + pin * 4;
  83. u64 scm_cfg_reg = spi_cfg->start + pin * 4;
  84. if (spi_cfg->scm_io) {
  85. unsigned int val;
  86. qcom_scm_io_readl(scm_cfg_reg, &val);
  87. return val;
  88. } else {
  89. return readl(cfg_reg);
  90. }
  91. }
  92. static void __spi_pin_write(unsigned int pin, unsigned int val)
  93. {
  94. void __iomem *cfg_reg = spi_cfg->base + pin * 4;
  95. u64 scm_cfg_reg = spi_cfg->start + pin * 4;
  96. if (spi_cfg->scm_io)
  97. qcom_scm_io_writel(scm_cfg_reg, val);
  98. else
  99. writel(val, cfg_reg);
  100. }
  101. static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
  102. {
  103. int spi = hwirq - 32;
  104. u32 pin = spi / 32;
  105. u32 mask = BIT(spi % 32);
  106. u32 val;
  107. unsigned long flags;
  108. if (!spi_cfg)
  109. return 0;
  110. if (pin * 4 > spi_cfg->size)
  111. return -EFAULT;
  112. raw_spin_lock_irqsave(&pdc_lock, flags);
  113. val = __spi_pin_read(pin);
  114. val &= ~mask;
  115. if (type & IRQ_TYPE_LEVEL_MASK)
  116. val |= mask;
  117. __spi_pin_write(pin, val);
  118. raw_spin_unlock_irqrestore(&pdc_lock, flags);
  119. return 0;
  120. }
  121. /*
  122. * GIC does not handle falling edge or active low. To allow falling edge and
  123. * active low interrupts to be handled at GIC, PDC has an inverter that inverts
  124. * falling edge into a rising edge and active low into an active high.
  125. * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
  126. * set as per the table below.
  127. * Level sensitive active low LOW
  128. * Rising edge sensitive NOT USED
  129. * Falling edge sensitive LOW
  130. * Dual Edge sensitive NOT USED
  131. * Level sensitive active High HIGH
  132. * Falling Edge sensitive NOT USED
  133. * Rising edge sensitive HIGH
  134. * Dual Edge sensitive HIGH
  135. */
  136. enum pdc_irq_config_bits {
  137. PDC_LEVEL_LOW = 0b000,
  138. PDC_EDGE_FALLING = 0b010,
  139. PDC_LEVEL_HIGH = 0b100,
  140. PDC_EDGE_RISING = 0b110,
  141. PDC_EDGE_DUAL = 0b111,
  142. };
  143. /**
  144. * qcom_pdc_gic_set_type: Configure PDC for the interrupt
  145. *
  146. * @d: the interrupt data
  147. * @type: the interrupt type
  148. *
  149. * If @type is edge triggered, forward that as Rising edge as PDC
  150. * takes care of converting falling edge to rising edge signal
  151. * If @type is level, then forward that as level high as PDC
  152. * takes care of converting falling edge to rising edge signal
  153. */
  154. static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
  155. {
  156. int parent_hwirq = d->parent_data->hwirq;
  157. enum pdc_irq_config_bits pdc_type;
  158. enum pdc_irq_config_bits old_pdc_type;
  159. int ret;
  160. switch (type) {
  161. case IRQ_TYPE_EDGE_RISING:
  162. pdc_type = PDC_EDGE_RISING;
  163. break;
  164. case IRQ_TYPE_EDGE_FALLING:
  165. pdc_type = PDC_EDGE_FALLING;
  166. type = IRQ_TYPE_EDGE_RISING;
  167. break;
  168. case IRQ_TYPE_EDGE_BOTH:
  169. pdc_type = PDC_EDGE_DUAL;
  170. type = IRQ_TYPE_EDGE_RISING;
  171. break;
  172. case IRQ_TYPE_LEVEL_HIGH:
  173. pdc_type = PDC_LEVEL_HIGH;
  174. break;
  175. case IRQ_TYPE_LEVEL_LOW:
  176. pdc_type = PDC_LEVEL_LOW;
  177. type = IRQ_TYPE_LEVEL_HIGH;
  178. break;
  179. default:
  180. WARN_ON(1);
  181. return -EINVAL;
  182. }
  183. old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
  184. pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
  185. /* Additionally, configure (only) the GPIO in the f/w */
  186. ret = spi_configure_type(parent_hwirq, type);
  187. if (ret)
  188. return ret;
  189. ret = irq_chip_set_type_parent(d, type);
  190. if (ret)
  191. return ret;
  192. /*
  193. * When we change types the PDC can give a phantom interrupt.
  194. * Clear it. Specifically the phantom shows up when reconfiguring
  195. * polarity of interrupt without changing the state of the signal
  196. * but let's be consistent and clear it always.
  197. *
  198. * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
  199. * interrupt will be cleared before the rest of the system sees it.
  200. */
  201. if (old_pdc_type != pdc_type)
  202. irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
  203. return 0;
  204. }
  205. static struct irq_chip qcom_pdc_gic_chip = {
  206. .name = "PDC",
  207. .irq_eoi = irq_chip_eoi_parent,
  208. .irq_mask = irq_chip_mask_parent,
  209. .irq_unmask = irq_chip_unmask_parent,
  210. .irq_disable = qcom_pdc_gic_disable,
  211. .irq_enable = qcom_pdc_gic_enable,
  212. .irq_get_irqchip_state = irq_chip_get_parent_state,
  213. .irq_set_irqchip_state = irq_chip_set_parent_state,
  214. .irq_retrigger = irq_chip_retrigger_hierarchy,
  215. .irq_set_type = qcom_pdc_gic_set_type,
  216. .flags = IRQCHIP_MASK_ON_SUSPEND |
  217. IRQCHIP_SET_TYPE_MASKED |
  218. IRQCHIP_SKIP_SET_WAKE |
  219. IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
  220. .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
  221. .irq_set_affinity = irq_chip_set_affinity_parent,
  222. };
  223. static irq_hw_number_t get_parent_hwirq(int pin)
  224. {
  225. int i;
  226. struct pdc_pin_region *region;
  227. for (i = 0; i < pdc_region_cnt; i++) {
  228. region = &pdc_region[i];
  229. if (pin >= region->pin_base &&
  230. pin < region->pin_base + region->cnt)
  231. return (region->parent_base + pin - region->pin_base);
  232. }
  233. return PDC_NO_PARENT_IRQ;
  234. }
  235. static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
  236. unsigned long *hwirq, unsigned int *type)
  237. {
  238. if (is_of_node(fwspec->fwnode)) {
  239. if (fwspec->param_count != 2)
  240. return -EINVAL;
  241. *hwirq = fwspec->param[0];
  242. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  243. return 0;
  244. }
  245. return -EINVAL;
  246. }
  247. static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
  248. unsigned int nr_irqs, void *data)
  249. {
  250. struct irq_fwspec *fwspec = data;
  251. struct irq_fwspec parent_fwspec;
  252. irq_hw_number_t hwirq, parent_hwirq;
  253. unsigned int type;
  254. int ret;
  255. ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
  256. if (ret)
  257. return ret;
  258. ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  259. &qcom_pdc_gic_chip, NULL);
  260. if (ret)
  261. return ret;
  262. parent_hwirq = get_parent_hwirq(hwirq);
  263. if (parent_hwirq == PDC_NO_PARENT_IRQ)
  264. return irq_domain_disconnect_hierarchy(domain->parent, virq);
  265. if (type & IRQ_TYPE_EDGE_BOTH)
  266. type = IRQ_TYPE_EDGE_RISING;
  267. if (type & IRQ_TYPE_LEVEL_MASK)
  268. type = IRQ_TYPE_LEVEL_HIGH;
  269. parent_fwspec.fwnode = domain->parent->fwnode;
  270. parent_fwspec.param_count = 3;
  271. parent_fwspec.param[0] = 0;
  272. parent_fwspec.param[1] = parent_hwirq;
  273. parent_fwspec.param[2] = type;
  274. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  275. &parent_fwspec);
  276. }
  277. static const struct irq_domain_ops qcom_pdc_ops = {
  278. .translate = qcom_pdc_translate,
  279. .alloc = qcom_pdc_alloc,
  280. .free = irq_domain_free_irqs_common,
  281. };
  282. static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
  283. unsigned int nr_irqs, void *data)
  284. {
  285. struct irq_fwspec *fwspec = data;
  286. struct irq_fwspec parent_fwspec;
  287. irq_hw_number_t hwirq, parent_hwirq;
  288. unsigned int type;
  289. int ret;
  290. ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
  291. if (ret)
  292. return ret;
  293. if (hwirq == GPIO_NO_WAKE_IRQ)
  294. return irq_domain_disconnect_hierarchy(domain, virq);
  295. ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  296. &qcom_pdc_gic_chip, NULL);
  297. if (ret)
  298. return ret;
  299. parent_hwirq = get_parent_hwirq(hwirq);
  300. if (parent_hwirq == PDC_NO_PARENT_IRQ)
  301. return irq_domain_disconnect_hierarchy(domain->parent, virq);
  302. if (type & IRQ_TYPE_EDGE_BOTH)
  303. type = IRQ_TYPE_EDGE_RISING;
  304. if (type & IRQ_TYPE_LEVEL_MASK)
  305. type = IRQ_TYPE_LEVEL_HIGH;
  306. parent_fwspec.fwnode = domain->parent->fwnode;
  307. parent_fwspec.param_count = 3;
  308. parent_fwspec.param[0] = 0;
  309. parent_fwspec.param[1] = parent_hwirq;
  310. parent_fwspec.param[2] = type;
  311. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  312. &parent_fwspec);
  313. }
  314. static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
  315. struct irq_fwspec *fwspec,
  316. enum irq_domain_bus_token bus_token)
  317. {
  318. return bus_token == DOMAIN_BUS_WAKEUP;
  319. }
  320. static const struct irq_domain_ops qcom_pdc_gpio_ops = {
  321. .select = qcom_pdc_gpio_domain_select,
  322. .alloc = qcom_pdc_gpio_alloc,
  323. .free = irq_domain_free_irqs_common,
  324. };
  325. static int pdc_setup_pin_mapping(struct device_node *np)
  326. {
  327. int ret, n, i;
  328. u32 irq_index, reg_index, val;
  329. n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
  330. if (n <= 0 || n % 3)
  331. return -EINVAL;
  332. pdc_region_cnt = n / 3;
  333. pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
  334. if (!pdc_region) {
  335. pdc_region_cnt = 0;
  336. return -ENOMEM;
  337. }
  338. for (n = 0; n < pdc_region_cnt; n++) {
  339. ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
  340. n * 3 + 0,
  341. &pdc_region[n].pin_base);
  342. if (ret)
  343. return ret;
  344. ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
  345. n * 3 + 1,
  346. &pdc_region[n].parent_base);
  347. if (ret)
  348. return ret;
  349. ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
  350. n * 3 + 2,
  351. &pdc_region[n].cnt);
  352. if (ret)
  353. return ret;
  354. for (i = 0; i < pdc_region[n].cnt; i++) {
  355. reg_index = (i + pdc_region[n].pin_base) >> 5;
  356. irq_index = (i + pdc_region[n].pin_base) & 0x1f;
  357. val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
  358. val &= ~BIT(irq_index);
  359. pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
  360. }
  361. }
  362. return 0;
  363. }
  364. static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
  365. {
  366. struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
  367. struct resource res;
  368. int ret;
  369. pdc_base = of_iomap(node, 0);
  370. if (!pdc_base) {
  371. pr_err("%pOF: unable to map PDC registers\n", node);
  372. return -ENXIO;
  373. }
  374. parent_domain = irq_find_host(parent);
  375. if (!parent_domain) {
  376. pr_err("%pOF: unable to find PDC's parent domain\n", node);
  377. ret = -ENXIO;
  378. goto fail;
  379. }
  380. ret = pdc_setup_pin_mapping(node);
  381. if (ret) {
  382. pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
  383. goto fail;
  384. }
  385. pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
  386. of_fwnode_handle(node),
  387. &qcom_pdc_ops, NULL);
  388. if (!pdc_domain) {
  389. pr_err("%pOF: GIC domain add failed\n", node);
  390. ret = -ENOMEM;
  391. goto fail;
  392. }
  393. ret = of_address_to_resource(node, 1, &res);
  394. if (!ret) {
  395. spi_cfg = kcalloc(1, sizeof(*spi_cfg), GFP_KERNEL);
  396. if (!spi_cfg) {
  397. ret = -ENOMEM;
  398. goto remove;
  399. }
  400. spi_cfg->scm_io = of_find_property(node,
  401. "qcom,scm-spi-cfg", NULL);
  402. spi_cfg->size = resource_size(&res);
  403. if (spi_cfg->scm_io) {
  404. spi_cfg->start = res.start;
  405. } else {
  406. spi_cfg->base = ioremap(res.start, spi_cfg->size);
  407. if (!spi_cfg->base) {
  408. ret = -ENOMEM;
  409. goto remove;
  410. }
  411. }
  412. }
  413. pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
  414. IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
  415. PDC_MAX_GPIO_IRQS,
  416. of_fwnode_handle(node),
  417. &qcom_pdc_gpio_ops, NULL);
  418. if (!pdc_gpio_domain) {
  419. pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
  420. ret = -ENOMEM;
  421. goto remove;
  422. }
  423. irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
  424. return 0;
  425. remove:
  426. irq_domain_remove(pdc_domain);
  427. kfree(spi_cfg);
  428. fail:
  429. kfree(pdc_region);
  430. iounmap(pdc_base);
  431. return ret;
  432. }
  433. static int qcom_pdc_probe(struct platform_device *pdev)
  434. {
  435. struct device_node *np = pdev->dev.of_node;
  436. struct device_node *parent = of_irq_find_parent(np);
  437. return qcom_pdc_init(np, parent);
  438. }
  439. static const struct of_device_id qcom_pdc_match_table[] = {
  440. { .compatible = "qcom,pdc" },
  441. {}
  442. };
  443. MODULE_DEVICE_TABLE(of, qcom_pdc_match_table);
  444. static struct platform_driver qcom_pdc_driver = {
  445. .probe = qcom_pdc_probe,
  446. .driver = {
  447. .name = "qcom-pdc",
  448. .of_match_table = qcom_pdc_match_table,
  449. .suppress_bind_attrs = true,
  450. },
  451. };
  452. module_platform_driver(qcom_pdc_driver);
  453. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
  454. MODULE_LICENSE("GPL v2");