irq-vt8500.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/arm/mach-vt8500/irq.c
  4. *
  5. * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  6. * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  7. */
  8. /*
  9. * This file is copied and modified from the original irq.c provided by
  10. * Alexey Charkov. Minor changes have been made for Device Tree Support.
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/bitops.h>
  19. #include <linux/of.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_address.h>
  22. #include <asm/irq.h>
  23. #include <asm/exception.h>
  24. #include <asm/mach/irq.h>
  25. #define VT8500_ICPC_IRQ 0x20
  26. #define VT8500_ICPC_FIQ 0x24
  27. #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
  28. #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
  29. /* ICPC */
  30. #define ICPC_MASK 0x3F
  31. #define ICPC_ROTATE BIT(6)
  32. /* IC_DCTR */
  33. #define ICDC_IRQ 0x00
  34. #define ICDC_FIQ 0x01
  35. #define ICDC_DSS0 0x02
  36. #define ICDC_DSS1 0x03
  37. #define ICDC_DSS2 0x04
  38. #define ICDC_DSS3 0x05
  39. #define ICDC_DSS4 0x06
  40. #define ICDC_DSS5 0x07
  41. #define VT8500_INT_DISABLE 0
  42. #define VT8500_INT_ENABLE BIT(3)
  43. #define VT8500_TRIGGER_HIGH 0
  44. #define VT8500_TRIGGER_RISING BIT(5)
  45. #define VT8500_TRIGGER_FALLING BIT(6)
  46. #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
  47. | VT8500_TRIGGER_FALLING)
  48. /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
  49. #define VT8500_INTC_MAX 2
  50. struct vt8500_irq_data {
  51. void __iomem *base; /* IO Memory base address */
  52. struct irq_domain *domain; /* Domain for this controller */
  53. };
  54. /* Global variable for accessing io-mem addresses */
  55. static struct vt8500_irq_data intc[VT8500_INTC_MAX];
  56. static u32 active_cnt = 0;
  57. static void vt8500_irq_mask(struct irq_data *d)
  58. {
  59. struct vt8500_irq_data *priv = d->domain->host_data;
  60. void __iomem *base = priv->base;
  61. void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
  62. u8 edge, dctr;
  63. u32 status;
  64. edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
  65. if (edge) {
  66. status = readl(stat_reg);
  67. status |= (1 << (d->hwirq & 0x1f));
  68. writel(status, stat_reg);
  69. } else {
  70. dctr = readb(base + VT8500_ICDC + d->hwirq);
  71. dctr &= ~VT8500_INT_ENABLE;
  72. writeb(dctr, base + VT8500_ICDC + d->hwirq);
  73. }
  74. }
  75. static void vt8500_irq_unmask(struct irq_data *d)
  76. {
  77. struct vt8500_irq_data *priv = d->domain->host_data;
  78. void __iomem *base = priv->base;
  79. u8 dctr;
  80. dctr = readb(base + VT8500_ICDC + d->hwirq);
  81. dctr |= VT8500_INT_ENABLE;
  82. writeb(dctr, base + VT8500_ICDC + d->hwirq);
  83. }
  84. static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
  85. {
  86. struct vt8500_irq_data *priv = d->domain->host_data;
  87. void __iomem *base = priv->base;
  88. u8 dctr;
  89. dctr = readb(base + VT8500_ICDC + d->hwirq);
  90. dctr &= ~VT8500_EDGE;
  91. switch (flow_type) {
  92. case IRQF_TRIGGER_LOW:
  93. return -EINVAL;
  94. case IRQF_TRIGGER_HIGH:
  95. dctr |= VT8500_TRIGGER_HIGH;
  96. irq_set_handler_locked(d, handle_level_irq);
  97. break;
  98. case IRQF_TRIGGER_FALLING:
  99. dctr |= VT8500_TRIGGER_FALLING;
  100. irq_set_handler_locked(d, handle_edge_irq);
  101. break;
  102. case IRQF_TRIGGER_RISING:
  103. dctr |= VT8500_TRIGGER_RISING;
  104. irq_set_handler_locked(d, handle_edge_irq);
  105. break;
  106. }
  107. writeb(dctr, base + VT8500_ICDC + d->hwirq);
  108. return 0;
  109. }
  110. static struct irq_chip vt8500_irq_chip = {
  111. .name = "vt8500",
  112. .irq_ack = vt8500_irq_mask,
  113. .irq_mask = vt8500_irq_mask,
  114. .irq_unmask = vt8500_irq_unmask,
  115. .irq_set_type = vt8500_irq_set_type,
  116. };
  117. static void __init vt8500_init_irq_hw(void __iomem *base)
  118. {
  119. u32 i;
  120. /* Enable rotating priority for IRQ */
  121. writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
  122. writel(0x00, base + VT8500_ICPC_FIQ);
  123. /* Disable all interrupts and route them to IRQ */
  124. for (i = 0; i < 64; i++)
  125. writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
  126. }
  127. static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
  128. irq_hw_number_t hw)
  129. {
  130. irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
  131. return 0;
  132. }
  133. static const struct irq_domain_ops vt8500_irq_domain_ops = {
  134. .map = vt8500_irq_map,
  135. .xlate = irq_domain_xlate_onecell,
  136. };
  137. static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
  138. {
  139. u32 stat, i;
  140. int irqnr;
  141. void __iomem *base;
  142. /* Loop through each active controller */
  143. for (i=0; i<active_cnt; i++) {
  144. base = intc[i].base;
  145. irqnr = readl_relaxed(base) & 0x3F;
  146. /*
  147. Highest Priority register default = 63, so check that this
  148. is a real interrupt by checking the status register
  149. */
  150. if (irqnr == 63) {
  151. stat = readl_relaxed(base + VT8500_ICIS + 4);
  152. if (!(stat & BIT(31)))
  153. continue;
  154. }
  155. handle_domain_irq(intc[i].domain, irqnr, regs);
  156. }
  157. }
  158. static int __init vt8500_irq_init(struct device_node *node,
  159. struct device_node *parent)
  160. {
  161. int irq, i;
  162. struct device_node *np = node;
  163. if (active_cnt == VT8500_INTC_MAX) {
  164. pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
  165. __func__);
  166. goto out;
  167. }
  168. intc[active_cnt].base = of_iomap(np, 0);
  169. intc[active_cnt].domain = irq_domain_add_linear(node, 64,
  170. &vt8500_irq_domain_ops, &intc[active_cnt]);
  171. if (!intc[active_cnt].base) {
  172. pr_err("%s: Unable to map IO memory\n", __func__);
  173. goto out;
  174. }
  175. if (!intc[active_cnt].domain) {
  176. pr_err("%s: Unable to add irq domain!\n", __func__);
  177. goto out;
  178. }
  179. set_handle_irq(vt8500_handle_irq);
  180. vt8500_init_irq_hw(intc[active_cnt].base);
  181. pr_info("vt8500-irq: Added interrupt controller\n");
  182. active_cnt++;
  183. /* check if this is a slaved controller */
  184. if (of_irq_count(np) != 0) {
  185. /* check that we have the correct number of interrupts */
  186. if (of_irq_count(np) != 8) {
  187. pr_err("%s: Incorrect IRQ map for slaved controller\n",
  188. __func__);
  189. return -EINVAL;
  190. }
  191. for (i = 0; i < 8; i++) {
  192. irq = irq_of_parse_and_map(np, i);
  193. enable_irq(irq);
  194. }
  195. pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
  196. }
  197. out:
  198. return 0;
  199. }
  200. IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);