irq-vic.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * linux/arch/arm/common/vic.c
  4. *
  5. * Copyright (C) 1999 - 2003 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd
  7. */
  8. #include <linux/export.h>
  9. #include <linux/init.h>
  10. #include <linux/list.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/irqchip/chained_irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/syscore_ops.h>
  20. #include <linux/device.h>
  21. #include <linux/amba/bus.h>
  22. #include <linux/irqchip/arm-vic.h>
  23. #include <asm/exception.h>
  24. #include <asm/irq.h>
  25. #define VIC_IRQ_STATUS 0x00
  26. #define VIC_FIQ_STATUS 0x04
  27. #define VIC_RAW_STATUS 0x08
  28. #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
  29. #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
  30. #define VIC_INT_ENABLE_CLEAR 0x14
  31. #define VIC_INT_SOFT 0x18
  32. #define VIC_INT_SOFT_CLEAR 0x1c
  33. #define VIC_PROTECT 0x20
  34. #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
  35. #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
  36. #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
  37. #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
  38. #define VIC_ITCR 0x300 /* VIC test control register */
  39. #define VIC_VECT_CNTL_ENABLE (1 << 5)
  40. #define VIC_PL192_VECT_ADDR 0xF00
  41. /**
  42. * struct vic_device - VIC PM device
  43. * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
  44. * @irq: The IRQ number for the base of the VIC.
  45. * @base: The register base for the VIC.
  46. * @valid_sources: A bitmask of valid interrupts
  47. * @resume_sources: A bitmask of interrupts for resume.
  48. * @resume_irqs: The IRQs enabled for resume.
  49. * @int_select: Save for VIC_INT_SELECT.
  50. * @int_enable: Save for VIC_INT_ENABLE.
  51. * @soft_int: Save for VIC_INT_SOFT.
  52. * @protect: Save for VIC_PROTECT.
  53. * @domain: The IRQ domain for the VIC.
  54. */
  55. struct vic_device {
  56. void __iomem *base;
  57. int irq;
  58. u32 valid_sources;
  59. u32 resume_sources;
  60. u32 resume_irqs;
  61. u32 int_select;
  62. u32 int_enable;
  63. u32 soft_int;
  64. u32 protect;
  65. struct irq_domain *domain;
  66. };
  67. /* we cannot allocate memory when VICs are initially registered */
  68. static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  69. static int vic_id;
  70. static void vic_handle_irq(struct pt_regs *regs);
  71. /**
  72. * vic_init2 - common initialisation code
  73. * @base: Base of the VIC.
  74. *
  75. * Common initialisation code for registration
  76. * and resume.
  77. */
  78. static void vic_init2(void __iomem *base)
  79. {
  80. int i;
  81. for (i = 0; i < 16; i++) {
  82. void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  83. writel(VIC_VECT_CNTL_ENABLE | i, reg);
  84. }
  85. writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  86. }
  87. #ifdef CONFIG_PM
  88. static void resume_one_vic(struct vic_device *vic)
  89. {
  90. void __iomem *base = vic->base;
  91. printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
  92. /* re-initialise static settings */
  93. vic_init2(base);
  94. writel(vic->int_select, base + VIC_INT_SELECT);
  95. writel(vic->protect, base + VIC_PROTECT);
  96. /* set the enabled ints and then clear the non-enabled */
  97. writel(vic->int_enable, base + VIC_INT_ENABLE);
  98. writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
  99. /* and the same for the soft-int register */
  100. writel(vic->soft_int, base + VIC_INT_SOFT);
  101. writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
  102. }
  103. static void vic_resume(void)
  104. {
  105. int id;
  106. for (id = vic_id - 1; id >= 0; id--)
  107. resume_one_vic(vic_devices + id);
  108. }
  109. static void suspend_one_vic(struct vic_device *vic)
  110. {
  111. void __iomem *base = vic->base;
  112. printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
  113. vic->int_select = readl(base + VIC_INT_SELECT);
  114. vic->int_enable = readl(base + VIC_INT_ENABLE);
  115. vic->soft_int = readl(base + VIC_INT_SOFT);
  116. vic->protect = readl(base + VIC_PROTECT);
  117. /* set the interrupts (if any) that are used for
  118. * resuming the system */
  119. writel(vic->resume_irqs, base + VIC_INT_ENABLE);
  120. writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
  121. }
  122. static int vic_suspend(void)
  123. {
  124. int id;
  125. for (id = 0; id < vic_id; id++)
  126. suspend_one_vic(vic_devices + id);
  127. return 0;
  128. }
  129. static struct syscore_ops vic_syscore_ops = {
  130. .suspend = vic_suspend,
  131. .resume = vic_resume,
  132. };
  133. /**
  134. * vic_pm_init - initicall to register VIC pm
  135. *
  136. * This is called via late_initcall() to register
  137. * the resources for the VICs due to the early
  138. * nature of the VIC's registration.
  139. */
  140. static int __init vic_pm_init(void)
  141. {
  142. if (vic_id > 0)
  143. register_syscore_ops(&vic_syscore_ops);
  144. return 0;
  145. }
  146. late_initcall(vic_pm_init);
  147. #endif /* CONFIG_PM */
  148. static struct irq_chip vic_chip;
  149. static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
  150. irq_hw_number_t hwirq)
  151. {
  152. struct vic_device *v = d->host_data;
  153. /* Skip invalid IRQs, only register handlers for the real ones */
  154. if (!(v->valid_sources & (1 << hwirq)))
  155. return -EPERM;
  156. irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
  157. irq_set_chip_data(irq, v->base);
  158. irq_set_probe(irq);
  159. return 0;
  160. }
  161. /*
  162. * Handle each interrupt in a single VIC. Returns non-zero if we've
  163. * handled at least one interrupt. This reads the status register
  164. * before handling each interrupt, which is necessary given that
  165. * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
  166. */
  167. static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
  168. {
  169. u32 stat, irq;
  170. int handled = 0;
  171. while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
  172. irq = ffs(stat) - 1;
  173. handle_domain_irq(vic->domain, irq, regs);
  174. handled = 1;
  175. }
  176. return handled;
  177. }
  178. static void vic_handle_irq_cascaded(struct irq_desc *desc)
  179. {
  180. u32 stat, hwirq;
  181. struct irq_chip *host_chip = irq_desc_get_chip(desc);
  182. struct vic_device *vic = irq_desc_get_handler_data(desc);
  183. chained_irq_enter(host_chip, desc);
  184. while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
  185. hwirq = ffs(stat) - 1;
  186. generic_handle_irq(irq_find_mapping(vic->domain, hwirq));
  187. }
  188. chained_irq_exit(host_chip, desc);
  189. }
  190. /*
  191. * Keep iterating over all registered VIC's until there are no pending
  192. * interrupts.
  193. */
  194. static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
  195. {
  196. int i, handled;
  197. do {
  198. for (i = 0, handled = 0; i < vic_id; ++i)
  199. handled |= handle_one_vic(&vic_devices[i], regs);
  200. } while (handled);
  201. }
  202. static const struct irq_domain_ops vic_irqdomain_ops = {
  203. .map = vic_irqdomain_map,
  204. .xlate = irq_domain_xlate_onetwocell,
  205. };
  206. /**
  207. * vic_register() - Register a VIC.
  208. * @base: The base address of the VIC.
  209. * @parent_irq: The parent IRQ if cascaded, else 0.
  210. * @irq: The base IRQ for the VIC.
  211. * @valid_sources: bitmask of valid interrupts
  212. * @resume_sources: bitmask of interrupts allowed for resume sources.
  213. * @node: The device tree node associated with the VIC.
  214. *
  215. * Register the VIC with the system device tree so that it can be notified
  216. * of suspend and resume requests and ensure that the correct actions are
  217. * taken to re-instate the settings on resume.
  218. *
  219. * This also configures the IRQ domain for the VIC.
  220. */
  221. static void __init vic_register(void __iomem *base, unsigned int parent_irq,
  222. unsigned int irq,
  223. u32 valid_sources, u32 resume_sources,
  224. struct device_node *node)
  225. {
  226. struct vic_device *v;
  227. int i;
  228. if (vic_id >= ARRAY_SIZE(vic_devices)) {
  229. printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
  230. return;
  231. }
  232. v = &vic_devices[vic_id];
  233. v->base = base;
  234. v->valid_sources = valid_sources;
  235. v->resume_sources = resume_sources;
  236. set_handle_irq(vic_handle_irq);
  237. vic_id++;
  238. if (parent_irq) {
  239. irq_set_chained_handler_and_data(parent_irq,
  240. vic_handle_irq_cascaded, v);
  241. }
  242. v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
  243. &vic_irqdomain_ops, v);
  244. /* create an IRQ mapping for each valid IRQ */
  245. for (i = 0; i < fls(valid_sources); i++)
  246. if (valid_sources & (1 << i))
  247. irq_create_mapping(v->domain, i);
  248. /* If no base IRQ was passed, figure out our allocated base */
  249. if (irq)
  250. v->irq = irq;
  251. else
  252. v->irq = irq_find_mapping(v->domain, 0);
  253. }
  254. static void vic_ack_irq(struct irq_data *d)
  255. {
  256. void __iomem *base = irq_data_get_irq_chip_data(d);
  257. unsigned int irq = d->hwirq;
  258. writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
  259. /* moreover, clear the soft-triggered, in case it was the reason */
  260. writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
  261. }
  262. static void vic_mask_irq(struct irq_data *d)
  263. {
  264. void __iomem *base = irq_data_get_irq_chip_data(d);
  265. unsigned int irq = d->hwirq;
  266. writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
  267. }
  268. static void vic_unmask_irq(struct irq_data *d)
  269. {
  270. void __iomem *base = irq_data_get_irq_chip_data(d);
  271. unsigned int irq = d->hwirq;
  272. writel(1 << irq, base + VIC_INT_ENABLE);
  273. }
  274. #if defined(CONFIG_PM)
  275. static struct vic_device *vic_from_irq(unsigned int irq)
  276. {
  277. struct vic_device *v = vic_devices;
  278. unsigned int base_irq = irq & ~31;
  279. int id;
  280. for (id = 0; id < vic_id; id++, v++) {
  281. if (v->irq == base_irq)
  282. return v;
  283. }
  284. return NULL;
  285. }
  286. static int vic_set_wake(struct irq_data *d, unsigned int on)
  287. {
  288. struct vic_device *v = vic_from_irq(d->irq);
  289. unsigned int off = d->hwirq;
  290. u32 bit = 1 << off;
  291. if (!v)
  292. return -EINVAL;
  293. if (!(bit & v->resume_sources))
  294. return -EINVAL;
  295. if (on)
  296. v->resume_irqs |= bit;
  297. else
  298. v->resume_irqs &= ~bit;
  299. return 0;
  300. }
  301. #else
  302. #define vic_set_wake NULL
  303. #endif /* CONFIG_PM */
  304. static struct irq_chip vic_chip = {
  305. .name = "VIC",
  306. .irq_ack = vic_ack_irq,
  307. .irq_mask = vic_mask_irq,
  308. .irq_unmask = vic_unmask_irq,
  309. .irq_set_wake = vic_set_wake,
  310. };
  311. static void __init vic_disable(void __iomem *base)
  312. {
  313. writel(0, base + VIC_INT_SELECT);
  314. writel(0, base + VIC_INT_ENABLE);
  315. writel(~0, base + VIC_INT_ENABLE_CLEAR);
  316. writel(0, base + VIC_ITCR);
  317. writel(~0, base + VIC_INT_SOFT_CLEAR);
  318. }
  319. static void __init vic_clear_interrupts(void __iomem *base)
  320. {
  321. unsigned int i;
  322. writel(0, base + VIC_PL190_VECT_ADDR);
  323. for (i = 0; i < 19; i++) {
  324. unsigned int value;
  325. value = readl(base + VIC_PL190_VECT_ADDR);
  326. writel(value, base + VIC_PL190_VECT_ADDR);
  327. }
  328. }
  329. /*
  330. * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
  331. * The original cell has 32 interrupts, while the modified one has 64,
  332. * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
  333. * the probe function is called twice, with base set to offset 000
  334. * and 020 within the page. We call this "second block".
  335. */
  336. static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
  337. u32 vic_sources, struct device_node *node)
  338. {
  339. unsigned int i;
  340. int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
  341. /* Disable all interrupts initially. */
  342. vic_disable(base);
  343. /*
  344. * Make sure we clear all existing interrupts. The vector registers
  345. * in this cell are after the second block of general registers,
  346. * so we can address them using standard offsets, but only from
  347. * the second base address, which is 0x20 in the page
  348. */
  349. if (vic_2nd_block) {
  350. vic_clear_interrupts(base);
  351. /* ST has 16 vectors as well, but we don't enable them by now */
  352. for (i = 0; i < 16; i++) {
  353. void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  354. writel(0, reg);
  355. }
  356. writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  357. }
  358. vic_register(base, 0, irq_start, vic_sources, 0, node);
  359. }
  360. static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
  361. u32 vic_sources, u32 resume_sources,
  362. struct device_node *node)
  363. {
  364. unsigned int i;
  365. u32 cellid = 0;
  366. enum amba_vendor vendor;
  367. /* Identify which VIC cell this one is, by reading the ID */
  368. for (i = 0; i < 4; i++) {
  369. void __iomem *addr;
  370. addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
  371. cellid |= (readl(addr) & 0xff) << (8 * i);
  372. }
  373. vendor = (cellid >> 12) & 0xff;
  374. printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
  375. base, cellid, vendor);
  376. switch(vendor) {
  377. case AMBA_VENDOR_ST:
  378. vic_init_st(base, irq_start, vic_sources, node);
  379. return;
  380. default:
  381. printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
  382. fallthrough;
  383. case AMBA_VENDOR_ARM:
  384. break;
  385. }
  386. /* Disable all interrupts initially. */
  387. vic_disable(base);
  388. /* Make sure we clear all existing interrupts */
  389. vic_clear_interrupts(base);
  390. vic_init2(base);
  391. vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
  392. }
  393. /**
  394. * vic_init() - initialise a vectored interrupt controller
  395. * @base: iomem base address
  396. * @irq_start: starting interrupt number, must be muliple of 32
  397. * @vic_sources: bitmask of interrupt sources to allow
  398. * @resume_sources: bitmask of interrupt sources to allow for resume
  399. */
  400. void __init vic_init(void __iomem *base, unsigned int irq_start,
  401. u32 vic_sources, u32 resume_sources)
  402. {
  403. __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
  404. }
  405. #ifdef CONFIG_OF
  406. static int __init vic_of_init(struct device_node *node,
  407. struct device_node *parent)
  408. {
  409. void __iomem *regs;
  410. u32 interrupt_mask = ~0;
  411. u32 wakeup_mask = ~0;
  412. int parent_irq;
  413. regs = of_iomap(node, 0);
  414. if (WARN_ON(!regs))
  415. return -EIO;
  416. of_property_read_u32(node, "valid-mask", &interrupt_mask);
  417. of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
  418. parent_irq = of_irq_get(node, 0);
  419. if (parent_irq < 0)
  420. parent_irq = 0;
  421. /*
  422. * Passing 0 as first IRQ makes the simple domain allocate descriptors
  423. */
  424. __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node);
  425. return 0;
  426. }
  427. IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
  428. IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
  429. IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
  430. #endif /* CONFIG OF */