irq-versatile-fpga.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support for Versatile FPGA-based IRQ controllers
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/irq.h>
  7. #include <linux/io.h>
  8. #include <linux/irqchip.h>
  9. #include <linux/irqchip/chained_irq.h>
  10. #include <linux/irqchip/versatile-fpga.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <asm/exception.h>
  17. #include <asm/mach/irq.h>
  18. #define IRQ_STATUS 0x00
  19. #define IRQ_RAW_STATUS 0x04
  20. #define IRQ_ENABLE_SET 0x08
  21. #define IRQ_ENABLE_CLEAR 0x0c
  22. #define INT_SOFT_SET 0x10
  23. #define INT_SOFT_CLEAR 0x14
  24. #define FIQ_STATUS 0x20
  25. #define FIQ_RAW_STATUS 0x24
  26. #define FIQ_ENABLE 0x28
  27. #define FIQ_ENABLE_SET 0x28
  28. #define FIQ_ENABLE_CLEAR 0x2C
  29. #define PIC_ENABLES 0x20 /* set interrupt pass through bits */
  30. /**
  31. * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  32. * @base: memory offset in virtual memory
  33. * @chip: chip container for this instance
  34. * @domain: IRQ domain for this instance
  35. * @valid: mask for valid IRQs on this controller
  36. * @used_irqs: number of active IRQs on this controller
  37. */
  38. struct fpga_irq_data {
  39. void __iomem *base;
  40. struct irq_chip chip;
  41. u32 valid;
  42. struct irq_domain *domain;
  43. u8 used_irqs;
  44. };
  45. /* we cannot allocate memory when the controllers are initially registered */
  46. static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
  47. static int fpga_irq_id;
  48. static void fpga_irq_mask(struct irq_data *d)
  49. {
  50. struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  51. u32 mask = 1 << d->hwirq;
  52. writel(mask, f->base + IRQ_ENABLE_CLEAR);
  53. }
  54. static void fpga_irq_unmask(struct irq_data *d)
  55. {
  56. struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  57. u32 mask = 1 << d->hwirq;
  58. writel(mask, f->base + IRQ_ENABLE_SET);
  59. }
  60. static void fpga_irq_handle(struct irq_desc *desc)
  61. {
  62. struct irq_chip *chip = irq_desc_get_chip(desc);
  63. struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
  64. u32 status;
  65. chained_irq_enter(chip, desc);
  66. status = readl(f->base + IRQ_STATUS);
  67. if (status == 0) {
  68. do_bad_IRQ(desc);
  69. goto out;
  70. }
  71. do {
  72. unsigned int irq = ffs(status) - 1;
  73. status &= ~(1 << irq);
  74. generic_handle_irq(irq_find_mapping(f->domain, irq));
  75. } while (status);
  76. out:
  77. chained_irq_exit(chip, desc);
  78. }
  79. /*
  80. * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
  81. * if we've handled at least one interrupt. This does a single read of the
  82. * status register and handles all interrupts in order from LSB first.
  83. */
  84. static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
  85. {
  86. int handled = 0;
  87. int irq;
  88. u32 status;
  89. while ((status = readl(f->base + IRQ_STATUS))) {
  90. irq = ffs(status) - 1;
  91. handle_domain_irq(f->domain, irq, regs);
  92. handled = 1;
  93. }
  94. return handled;
  95. }
  96. /*
  97. * Keep iterating over all registered FPGA IRQ controllers until there are
  98. * no pending interrupts.
  99. */
  100. asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
  101. {
  102. int i, handled;
  103. do {
  104. for (i = 0, handled = 0; i < fpga_irq_id; ++i)
  105. handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
  106. } while (handled);
  107. }
  108. static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
  109. irq_hw_number_t hwirq)
  110. {
  111. struct fpga_irq_data *f = d->host_data;
  112. /* Skip invalid IRQs, only register handlers for the real ones */
  113. if (!(f->valid & BIT(hwirq)))
  114. return -EPERM;
  115. irq_set_chip_data(irq, f);
  116. irq_set_chip_and_handler(irq, &f->chip,
  117. handle_level_irq);
  118. irq_set_probe(irq);
  119. return 0;
  120. }
  121. static const struct irq_domain_ops fpga_irqdomain_ops = {
  122. .map = fpga_irqdomain_map,
  123. .xlate = irq_domain_xlate_onetwocell,
  124. };
  125. void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
  126. int parent_irq, u32 valid, struct device_node *node)
  127. {
  128. struct fpga_irq_data *f;
  129. int i;
  130. if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
  131. pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
  132. return;
  133. }
  134. f = &fpga_irq_devices[fpga_irq_id];
  135. f->base = base;
  136. f->chip.name = name;
  137. f->chip.irq_ack = fpga_irq_mask;
  138. f->chip.irq_mask = fpga_irq_mask;
  139. f->chip.irq_unmask = fpga_irq_unmask;
  140. f->valid = valid;
  141. if (parent_irq != -1) {
  142. irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
  143. f);
  144. }
  145. /* This will also allocate irq descriptors */
  146. f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
  147. &fpga_irqdomain_ops, f);
  148. /* This will allocate all valid descriptors in the linear case */
  149. for (i = 0; i < fls(valid); i++)
  150. if (valid & BIT(i)) {
  151. if (!irq_start)
  152. irq_create_mapping(f->domain, i);
  153. f->used_irqs++;
  154. }
  155. pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
  156. fpga_irq_id, name, base, f->used_irqs);
  157. if (parent_irq != -1)
  158. pr_cont(", parent IRQ: %d\n", parent_irq);
  159. else
  160. pr_cont("\n");
  161. fpga_irq_id++;
  162. }
  163. #ifdef CONFIG_OF
  164. int __init fpga_irq_of_init(struct device_node *node,
  165. struct device_node *parent)
  166. {
  167. void __iomem *base;
  168. u32 clear_mask;
  169. u32 valid_mask;
  170. int parent_irq;
  171. if (WARN_ON(!node))
  172. return -ENODEV;
  173. base = of_iomap(node, 0);
  174. WARN(!base, "unable to map fpga irq registers\n");
  175. if (of_property_read_u32(node, "clear-mask", &clear_mask))
  176. clear_mask = 0;
  177. if (of_property_read_u32(node, "valid-mask", &valid_mask))
  178. valid_mask = 0;
  179. writel(clear_mask, base + IRQ_ENABLE_CLEAR);
  180. writel(clear_mask, base + FIQ_ENABLE_CLEAR);
  181. /* Some chips are cascaded from a parent IRQ */
  182. parent_irq = irq_of_parse_and_map(node, 0);
  183. if (!parent_irq) {
  184. set_handle_irq(fpga_handle_irq);
  185. parent_irq = -1;
  186. }
  187. fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
  188. /*
  189. * On Versatile AB/PB, some secondary interrupts have a direct
  190. * pass-thru to the primary controller for IRQs 20 and 22-31 which need
  191. * to be enabled. See section 3.10 of the Versatile AB user guide.
  192. */
  193. if (of_device_is_compatible(node, "arm,versatile-sic"))
  194. writel(0xffd00000, base + PIC_ENABLES);
  195. return 0;
  196. }
  197. IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
  198. IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
  199. IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
  200. #endif