irq-sirfsoc.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * interrupt controller support for CSR SiRFprimaII
  4. *
  5. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  6. */
  7. #include <linux/init.h>
  8. #include <linux/io.h>
  9. #include <linux/irq.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/syscore_ops.h>
  15. #include <asm/mach/irq.h>
  16. #include <asm/exception.h>
  17. #define SIRFSOC_INT_RISC_MASK0 0x0018
  18. #define SIRFSOC_INT_RISC_MASK1 0x001C
  19. #define SIRFSOC_INT_RISC_LEVEL0 0x0020
  20. #define SIRFSOC_INT_RISC_LEVEL1 0x0024
  21. #define SIRFSOC_INIT_IRQ_ID 0x0038
  22. #define SIRFSOC_INT_BASE_OFFSET 0x0004
  23. #define SIRFSOC_NUM_IRQS 64
  24. #define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
  25. static struct irq_domain *sirfsoc_irqdomain;
  26. static void __iomem *sirfsoc_irq_get_regbase(void)
  27. {
  28. return (void __iomem __force *)sirfsoc_irqdomain->host_data;
  29. }
  30. static __init void sirfsoc_alloc_gc(void __iomem *base)
  31. {
  32. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  33. unsigned int set = IRQ_LEVEL;
  34. struct irq_chip_generic *gc;
  35. struct irq_chip_type *ct;
  36. int i;
  37. irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
  38. handle_level_irq, clr, set,
  39. IRQ_GC_INIT_MASK_CACHE);
  40. for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
  41. gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
  42. gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
  43. ct = gc->chip_types;
  44. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  45. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  46. ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  47. }
  48. }
  49. static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
  50. {
  51. void __iomem *base = sirfsoc_irq_get_regbase();
  52. u32 irqstat;
  53. irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
  54. handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
  55. }
  56. static int __init sirfsoc_irq_init(struct device_node *np,
  57. struct device_node *parent)
  58. {
  59. void __iomem *base = of_iomap(np, 0);
  60. if (!base)
  61. panic("unable to map intc cpu registers\n");
  62. sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
  63. &irq_generic_chip_ops, base);
  64. sirfsoc_alloc_gc(base);
  65. writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
  66. writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
  67. writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
  68. writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
  69. set_handle_irq(sirfsoc_handle_irq);
  70. return 0;
  71. }
  72. IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
  73. struct sirfsoc_irq_status {
  74. u32 mask0;
  75. u32 mask1;
  76. u32 level0;
  77. u32 level1;
  78. };
  79. static struct sirfsoc_irq_status sirfsoc_irq_st;
  80. static int sirfsoc_irq_suspend(void)
  81. {
  82. void __iomem *base = sirfsoc_irq_get_regbase();
  83. sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
  84. sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
  85. sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
  86. sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
  87. return 0;
  88. }
  89. static void sirfsoc_irq_resume(void)
  90. {
  91. void __iomem *base = sirfsoc_irq_get_regbase();
  92. writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
  93. writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
  94. writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
  95. writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
  96. }
  97. static struct syscore_ops sirfsoc_irq_syscore_ops = {
  98. .suspend = sirfsoc_irq_suspend,
  99. .resume = sirfsoc_irq_resume,
  100. };
  101. static int __init sirfsoc_irq_pm_init(void)
  102. {
  103. if (!sirfsoc_irqdomain)
  104. return 0;
  105. register_syscore_ops(&sirfsoc_irq_syscore_ops);
  106. return 0;
  107. }
  108. device_initcall(sirfsoc_irq_pm_init);