irq-sa11x0.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Dmitry Eremin-Solenikov
  4. * Copyright (C) 1999-2001 Nicolas Pitre
  5. *
  6. * Generic IRQ handling for the SA11x0.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/syscore_ops.h>
  15. #include <linux/irqchip/irq-sa11x0.h>
  16. #include <soc/sa1100/pwer.h>
  17. #include <asm/exception.h>
  18. #define ICIP 0x00 /* IC IRQ Pending reg. */
  19. #define ICMR 0x04 /* IC Mask Reg. */
  20. #define ICLR 0x08 /* IC Level Reg. */
  21. #define ICCR 0x0C /* IC Control Reg. */
  22. #define ICFP 0x10 /* IC FIQ Pending reg. */
  23. #define ICPR 0x20 /* IC Pending Reg. */
  24. static void __iomem *iobase;
  25. /*
  26. * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  27. * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
  28. */
  29. static void sa1100_mask_irq(struct irq_data *d)
  30. {
  31. u32 reg;
  32. reg = readl_relaxed(iobase + ICMR);
  33. reg &= ~BIT(d->hwirq);
  34. writel_relaxed(reg, iobase + ICMR);
  35. }
  36. static void sa1100_unmask_irq(struct irq_data *d)
  37. {
  38. u32 reg;
  39. reg = readl_relaxed(iobase + ICMR);
  40. reg |= BIT(d->hwirq);
  41. writel_relaxed(reg, iobase + ICMR);
  42. }
  43. static int sa1100_set_wake(struct irq_data *d, unsigned int on)
  44. {
  45. return sa11x0_sc_set_wake(d->hwirq, on);
  46. }
  47. static struct irq_chip sa1100_normal_chip = {
  48. .name = "SC",
  49. .irq_ack = sa1100_mask_irq,
  50. .irq_mask = sa1100_mask_irq,
  51. .irq_unmask = sa1100_unmask_irq,
  52. .irq_set_wake = sa1100_set_wake,
  53. };
  54. static int sa1100_normal_irqdomain_map(struct irq_domain *d,
  55. unsigned int irq, irq_hw_number_t hwirq)
  56. {
  57. irq_set_chip_and_handler(irq, &sa1100_normal_chip,
  58. handle_level_irq);
  59. return 0;
  60. }
  61. static const struct irq_domain_ops sa1100_normal_irqdomain_ops = {
  62. .map = sa1100_normal_irqdomain_map,
  63. .xlate = irq_domain_xlate_onetwocell,
  64. };
  65. static struct irq_domain *sa1100_normal_irqdomain;
  66. static struct sa1100irq_state {
  67. unsigned int saved;
  68. unsigned int icmr;
  69. unsigned int iclr;
  70. unsigned int iccr;
  71. } sa1100irq_state;
  72. static int sa1100irq_suspend(void)
  73. {
  74. struct sa1100irq_state *st = &sa1100irq_state;
  75. st->saved = 1;
  76. st->icmr = readl_relaxed(iobase + ICMR);
  77. st->iclr = readl_relaxed(iobase + ICLR);
  78. st->iccr = readl_relaxed(iobase + ICCR);
  79. /*
  80. * Disable all GPIO-based interrupts.
  81. */
  82. writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
  83. return 0;
  84. }
  85. static void sa1100irq_resume(void)
  86. {
  87. struct sa1100irq_state *st = &sa1100irq_state;
  88. if (st->saved) {
  89. writel_relaxed(st->iccr, iobase + ICCR);
  90. writel_relaxed(st->iclr, iobase + ICLR);
  91. writel_relaxed(st->icmr, iobase + ICMR);
  92. }
  93. }
  94. static struct syscore_ops sa1100irq_syscore_ops = {
  95. .suspend = sa1100irq_suspend,
  96. .resume = sa1100irq_resume,
  97. };
  98. static int __init sa1100irq_init_devicefs(void)
  99. {
  100. register_syscore_ops(&sa1100irq_syscore_ops);
  101. return 0;
  102. }
  103. device_initcall(sa1100irq_init_devicefs);
  104. static asmlinkage void __exception_irq_entry
  105. sa1100_handle_irq(struct pt_regs *regs)
  106. {
  107. uint32_t icip, icmr, mask;
  108. do {
  109. icip = readl_relaxed(iobase + ICIP);
  110. icmr = readl_relaxed(iobase + ICMR);
  111. mask = icip & icmr;
  112. if (mask == 0)
  113. break;
  114. handle_domain_irq(sa1100_normal_irqdomain,
  115. ffs(mask) - 1, regs);
  116. } while (1);
  117. }
  118. void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
  119. {
  120. iobase = ioremap(io_start, SZ_64K);
  121. if (WARN_ON(!iobase))
  122. return;
  123. /* disable all IRQs */
  124. writel_relaxed(0, iobase + ICMR);
  125. /* all IRQs are IRQ, not FIQ */
  126. writel_relaxed(0, iobase + ICLR);
  127. /*
  128. * Whatever the doc says, this has to be set for the wait-on-irq
  129. * instruction to work... on a SA1100 rev 9 at least.
  130. */
  131. writel_relaxed(1, iobase + ICCR);
  132. sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
  133. 32, irq_start,
  134. &sa1100_normal_irqdomain_ops, NULL);
  135. set_handle_irq(sa1100_handle_irq);
  136. }