irq-pruss-intc.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PRU-ICSS INTC IRQChip driver for various TI SoCs
  4. *
  5. * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. * Author(s):
  8. * Andrew F. Davis <afd@ti.com>
  9. * Suman Anna <s-anna@ti.com>
  10. * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
  11. *
  12. * Copyright (C) 2019 David Lechner <david@lechnology.com>
  13. */
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/module.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. /*
  22. * Number of host interrupts reaching the main MPU sub-system. Note that this
  23. * is not the same as the total number of host interrupts supported by the PRUSS
  24. * INTC instance
  25. */
  26. #define MAX_NUM_HOST_IRQS 8
  27. /* minimum starting host interrupt number for MPU */
  28. #define FIRST_PRU_HOST_INT 2
  29. /* PRU_ICSS_INTC registers */
  30. #define PRU_INTC_REVID 0x0000
  31. #define PRU_INTC_CR 0x0004
  32. #define PRU_INTC_GER 0x0010
  33. #define PRU_INTC_GNLR 0x001c
  34. #define PRU_INTC_SISR 0x0020
  35. #define PRU_INTC_SICR 0x0024
  36. #define PRU_INTC_EISR 0x0028
  37. #define PRU_INTC_EICR 0x002c
  38. #define PRU_INTC_HIEISR 0x0034
  39. #define PRU_INTC_HIDISR 0x0038
  40. #define PRU_INTC_GPIR 0x0080
  41. #define PRU_INTC_SRSR(x) (0x0200 + (x) * 4)
  42. #define PRU_INTC_SECR(x) (0x0280 + (x) * 4)
  43. #define PRU_INTC_ESR(x) (0x0300 + (x) * 4)
  44. #define PRU_INTC_ECR(x) (0x0380 + (x) * 4)
  45. #define PRU_INTC_CMR(x) (0x0400 + (x) * 4)
  46. #define PRU_INTC_HMR(x) (0x0800 + (x) * 4)
  47. #define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4)
  48. #define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4)
  49. #define PRU_INTC_SITR(x) (0x0d80 + (x) * 4)
  50. #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
  51. #define PRU_INTC_HIER 0x1500
  52. /* CMR register bit-field macros */
  53. #define CMR_EVT_MAP_MASK 0xf
  54. #define CMR_EVT_MAP_BITS 8
  55. #define CMR_EVT_PER_REG 4
  56. /* HMR register bit-field macros */
  57. #define HMR_CH_MAP_MASK 0xf
  58. #define HMR_CH_MAP_BITS 8
  59. #define HMR_CH_PER_REG 4
  60. /* HIPIR register bit-fields */
  61. #define INTC_HIPIR_NONE_HINT 0x80000000
  62. #define MAX_PRU_SYS_EVENTS 160
  63. #define MAX_PRU_CHANNELS 20
  64. /**
  65. * struct pruss_intc_map_record - keeps track of actual mapping state
  66. * @value: The currently mapped value (channel or host)
  67. * @ref_count: Keeps track of number of current users of this resource
  68. */
  69. struct pruss_intc_map_record {
  70. u8 value;
  71. u8 ref_count;
  72. };
  73. /**
  74. * struct pruss_intc_match_data - match data to handle SoC variations
  75. * @num_system_events: number of input system events handled by the PRUSS INTC
  76. * @num_host_events: number of host events (which is equal to number of
  77. * channels) supported by the PRUSS INTC
  78. */
  79. struct pruss_intc_match_data {
  80. u8 num_system_events;
  81. u8 num_host_events;
  82. };
  83. /**
  84. * struct pruss_intc - PRUSS interrupt controller structure
  85. * @event_channel: current state of system event to channel mappings
  86. * @channel_host: current state of channel to host mappings
  87. * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
  88. * @base: base virtual address of INTC register space
  89. * @domain: irq domain for this interrupt controller
  90. * @soc_config: cached PRUSS INTC IP configuration data
  91. * @dev: PRUSS INTC device pointer
  92. * @lock: mutex to serialize interrupts mapping
  93. */
  94. struct pruss_intc {
  95. struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
  96. struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
  97. unsigned int irqs[MAX_NUM_HOST_IRQS];
  98. void __iomem *base;
  99. struct irq_domain *domain;
  100. const struct pruss_intc_match_data *soc_config;
  101. struct device *dev;
  102. struct mutex lock; /* PRUSS INTC lock */
  103. };
  104. /**
  105. * struct pruss_host_irq_data - PRUSS host irq data structure
  106. * @intc: PRUSS interrupt controller pointer
  107. * @host_irq: host irq number
  108. */
  109. struct pruss_host_irq_data {
  110. struct pruss_intc *intc;
  111. u8 host_irq;
  112. };
  113. static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
  114. {
  115. return readl_relaxed(intc->base + reg);
  116. }
  117. static inline void pruss_intc_write_reg(struct pruss_intc *intc,
  118. unsigned int reg, u32 val)
  119. {
  120. writel_relaxed(val, intc->base + reg);
  121. }
  122. static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt,
  123. u8 ch)
  124. {
  125. u32 idx, offset, val;
  126. idx = evt / CMR_EVT_PER_REG;
  127. offset = (evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS;
  128. val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
  129. val &= ~(CMR_EVT_MAP_MASK << offset);
  130. val |= ch << offset;
  131. pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
  132. dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch,
  133. idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
  134. }
  135. static void pruss_intc_update_hmr(struct pruss_intc *intc, u8 ch, u8 host)
  136. {
  137. u32 idx, offset, val;
  138. idx = ch / HMR_CH_PER_REG;
  139. offset = (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS;
  140. val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
  141. val &= ~(HMR_CH_MAP_MASK << offset);
  142. val |= host << offset;
  143. pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
  144. dev_dbg(intc->dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
  145. pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
  146. }
  147. /**
  148. * pruss_intc_map() - configure the PRUSS INTC
  149. * @intc: PRUSS interrupt controller pointer
  150. * @hwirq: the system event number
  151. *
  152. * Configures the PRUSS INTC with the provided configuration from the one parsed
  153. * in the xlate function.
  154. */
  155. static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq)
  156. {
  157. struct device *dev = intc->dev;
  158. u8 ch, host, reg_idx;
  159. u32 val;
  160. mutex_lock(&intc->lock);
  161. intc->event_channel[hwirq].ref_count++;
  162. ch = intc->event_channel[hwirq].value;
  163. host = intc->channel_host[ch].value;
  164. pruss_intc_update_cmr(intc, hwirq, ch);
  165. reg_idx = hwirq / 32;
  166. val = BIT(hwirq % 32);
  167. /* clear and enable system event */
  168. pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val);
  169. pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
  170. if (++intc->channel_host[ch].ref_count == 1) {
  171. pruss_intc_update_hmr(intc, ch, host);
  172. /* enable host interrupts */
  173. pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
  174. }
  175. dev_dbg(dev, "mapped system_event = %lu channel = %d host = %d",
  176. hwirq, ch, host);
  177. mutex_unlock(&intc->lock);
  178. }
  179. /**
  180. * pruss_intc_unmap() - unconfigure the PRUSS INTC
  181. * @intc: PRUSS interrupt controller pointer
  182. * @hwirq: the system event number
  183. *
  184. * Undo whatever was done in pruss_intc_map() for a PRU core.
  185. * Mappings are reference counted, so resources are only disabled when there
  186. * are no longer any users.
  187. */
  188. static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq)
  189. {
  190. u8 ch, host, reg_idx;
  191. u32 val;
  192. mutex_lock(&intc->lock);
  193. ch = intc->event_channel[hwirq].value;
  194. host = intc->channel_host[ch].value;
  195. if (--intc->channel_host[ch].ref_count == 0) {
  196. /* disable host interrupts */
  197. pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
  198. /* clear the map using reset value 0 */
  199. pruss_intc_update_hmr(intc, ch, 0);
  200. }
  201. intc->event_channel[hwirq].ref_count--;
  202. reg_idx = hwirq / 32;
  203. val = BIT(hwirq % 32);
  204. /* disable system events */
  205. pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val);
  206. /* clear any pending status */
  207. pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
  208. /* clear the map using reset value 0 */
  209. pruss_intc_update_cmr(intc, hwirq, 0);
  210. dev_dbg(intc->dev, "unmapped system_event = %lu channel = %d host = %d\n",
  211. hwirq, ch, host);
  212. mutex_unlock(&intc->lock);
  213. }
  214. static void pruss_intc_init(struct pruss_intc *intc)
  215. {
  216. const struct pruss_intc_match_data *soc_config = intc->soc_config;
  217. int num_chnl_map_regs, num_host_intr_regs, num_event_type_regs, i;
  218. num_chnl_map_regs = DIV_ROUND_UP(soc_config->num_system_events,
  219. CMR_EVT_PER_REG);
  220. num_host_intr_regs = DIV_ROUND_UP(soc_config->num_host_events,
  221. HMR_CH_PER_REG);
  222. num_event_type_regs = DIV_ROUND_UP(soc_config->num_system_events, 32);
  223. /*
  224. * configure polarity (SIPR register) to active high and
  225. * type (SITR register) to level interrupt for all system events
  226. */
  227. for (i = 0; i < num_event_type_regs; i++) {
  228. pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
  229. pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
  230. }
  231. /* clear all interrupt channel map registers, 4 events per register */
  232. for (i = 0; i < num_chnl_map_regs; i++)
  233. pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
  234. /* clear all host interrupt map registers, 4 channels per register */
  235. for (i = 0; i < num_host_intr_regs; i++)
  236. pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
  237. /* global interrupt enable */
  238. pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
  239. }
  240. static void pruss_intc_irq_ack(struct irq_data *data)
  241. {
  242. struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
  243. unsigned int hwirq = data->hwirq;
  244. pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
  245. }
  246. static void pruss_intc_irq_mask(struct irq_data *data)
  247. {
  248. struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
  249. unsigned int hwirq = data->hwirq;
  250. pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
  251. }
  252. static void pruss_intc_irq_unmask(struct irq_data *data)
  253. {
  254. struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
  255. unsigned int hwirq = data->hwirq;
  256. pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
  257. }
  258. static int pruss_intc_irq_reqres(struct irq_data *data)
  259. {
  260. if (!try_module_get(THIS_MODULE))
  261. return -ENODEV;
  262. return 0;
  263. }
  264. static void pruss_intc_irq_relres(struct irq_data *data)
  265. {
  266. module_put(THIS_MODULE);
  267. }
  268. static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
  269. enum irqchip_irq_state which,
  270. bool *state)
  271. {
  272. struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
  273. u32 reg, mask, srsr;
  274. if (which != IRQCHIP_STATE_PENDING)
  275. return -EINVAL;
  276. reg = PRU_INTC_SRSR(data->hwirq / 32);
  277. mask = BIT(data->hwirq % 32);
  278. srsr = pruss_intc_read_reg(intc, reg);
  279. *state = !!(srsr & mask);
  280. return 0;
  281. }
  282. static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
  283. enum irqchip_irq_state which,
  284. bool state)
  285. {
  286. struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
  287. if (which != IRQCHIP_STATE_PENDING)
  288. return -EINVAL;
  289. if (state)
  290. pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq);
  291. else
  292. pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq);
  293. return 0;
  294. }
  295. static struct irq_chip pruss_irqchip = {
  296. .name = "pruss-intc",
  297. .irq_ack = pruss_intc_irq_ack,
  298. .irq_mask = pruss_intc_irq_mask,
  299. .irq_unmask = pruss_intc_irq_unmask,
  300. .irq_request_resources = pruss_intc_irq_reqres,
  301. .irq_release_resources = pruss_intc_irq_relres,
  302. .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state,
  303. .irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state,
  304. };
  305. static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event,
  306. int channel, int host)
  307. {
  308. struct device *dev = intc->dev;
  309. int ret = 0;
  310. mutex_lock(&intc->lock);
  311. /* check if sysevent already assigned */
  312. if (intc->event_channel[event].ref_count > 0 &&
  313. intc->event_channel[event].value != channel) {
  314. dev_err(dev, "event %d (req. ch %d) already assigned to channel %d\n",
  315. event, channel, intc->event_channel[event].value);
  316. ret = -EBUSY;
  317. goto unlock;
  318. }
  319. /* check if channel already assigned */
  320. if (intc->channel_host[channel].ref_count > 0 &&
  321. intc->channel_host[channel].value != host) {
  322. dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n",
  323. channel, host, intc->channel_host[channel].value);
  324. ret = -EBUSY;
  325. goto unlock;
  326. }
  327. intc->event_channel[event].value = channel;
  328. intc->channel_host[channel].value = host;
  329. unlock:
  330. mutex_unlock(&intc->lock);
  331. return ret;
  332. }
  333. static int
  334. pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
  335. const u32 *intspec, unsigned int intsize,
  336. unsigned long *out_hwirq, unsigned int *out_type)
  337. {
  338. struct pruss_intc *intc = d->host_data;
  339. struct device *dev = intc->dev;
  340. int ret, sys_event, channel, host;
  341. if (intsize < 3)
  342. return -EINVAL;
  343. sys_event = intspec[0];
  344. if (sys_event < 0 || sys_event >= intc->soc_config->num_system_events) {
  345. dev_err(dev, "%d is not valid event number\n", sys_event);
  346. return -EINVAL;
  347. }
  348. channel = intspec[1];
  349. if (channel < 0 || channel >= intc->soc_config->num_host_events) {
  350. dev_err(dev, "%d is not valid channel number", channel);
  351. return -EINVAL;
  352. }
  353. host = intspec[2];
  354. if (host < 0 || host >= intc->soc_config->num_host_events) {
  355. dev_err(dev, "%d is not valid host irq number\n", host);
  356. return -EINVAL;
  357. }
  358. /* check if requested sys_event was already mapped, if so validate it */
  359. ret = pruss_intc_validate_mapping(intc, sys_event, channel, host);
  360. if (ret)
  361. return ret;
  362. *out_hwirq = sys_event;
  363. *out_type = IRQ_TYPE_LEVEL_HIGH;
  364. return 0;
  365. }
  366. static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
  367. irq_hw_number_t hw)
  368. {
  369. struct pruss_intc *intc = d->host_data;
  370. pruss_intc_map(intc, hw);
  371. irq_set_chip_data(virq, intc);
  372. irq_set_chip_and_handler(virq, &pruss_irqchip, handle_level_irq);
  373. return 0;
  374. }
  375. static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
  376. {
  377. struct pruss_intc *intc = d->host_data;
  378. unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
  379. irq_set_chip_and_handler(virq, NULL, NULL);
  380. irq_set_chip_data(virq, NULL);
  381. pruss_intc_unmap(intc, hwirq);
  382. }
  383. static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
  384. .xlate = pruss_intc_irq_domain_xlate,
  385. .map = pruss_intc_irq_domain_map,
  386. .unmap = pruss_intc_irq_domain_unmap,
  387. };
  388. static void pruss_intc_irq_handler(struct irq_desc *desc)
  389. {
  390. unsigned int irq = irq_desc_get_irq(desc);
  391. struct irq_chip *chip = irq_desc_get_chip(desc);
  392. struct pruss_host_irq_data *host_irq_data = irq_get_handler_data(irq);
  393. struct pruss_intc *intc = host_irq_data->intc;
  394. u8 host_irq = host_irq_data->host_irq + FIRST_PRU_HOST_INT;
  395. chained_irq_enter(chip, desc);
  396. while (true) {
  397. u32 hipir;
  398. unsigned int virq;
  399. int hwirq;
  400. /* get highest priority pending PRUSS system event */
  401. hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(host_irq));
  402. if (hipir & INTC_HIPIR_NONE_HINT)
  403. break;
  404. hwirq = hipir & GENMASK(9, 0);
  405. virq = irq_find_mapping(intc->domain, hwirq);
  406. /*
  407. * NOTE: manually ACK any system events that do not have a
  408. * handler mapped yet
  409. */
  410. if (WARN_ON_ONCE(!virq))
  411. pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
  412. else
  413. generic_handle_irq(virq);
  414. }
  415. chained_irq_exit(chip, desc);
  416. }
  417. static const char * const irq_names[MAX_NUM_HOST_IRQS] = {
  418. "host_intr0", "host_intr1", "host_intr2", "host_intr3",
  419. "host_intr4", "host_intr5", "host_intr6", "host_intr7",
  420. };
  421. static int pruss_intc_probe(struct platform_device *pdev)
  422. {
  423. const struct pruss_intc_match_data *data;
  424. struct device *dev = &pdev->dev;
  425. struct pruss_intc *intc;
  426. struct pruss_host_irq_data *host_data;
  427. int i, irq, ret;
  428. u8 max_system_events, irqs_reserved = 0;
  429. data = of_device_get_match_data(dev);
  430. if (!data)
  431. return -ENODEV;
  432. max_system_events = data->num_system_events;
  433. intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
  434. if (!intc)
  435. return -ENOMEM;
  436. intc->soc_config = data;
  437. intc->dev = dev;
  438. platform_set_drvdata(pdev, intc);
  439. intc->base = devm_platform_ioremap_resource(pdev, 0);
  440. if (IS_ERR(intc->base))
  441. return PTR_ERR(intc->base);
  442. ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved",
  443. &irqs_reserved);
  444. /*
  445. * The irqs-reserved is used only for some SoC's therefore not having
  446. * this property is still valid
  447. */
  448. if (ret < 0 && ret != -EINVAL)
  449. return ret;
  450. pruss_intc_init(intc);
  451. mutex_init(&intc->lock);
  452. intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
  453. &pruss_intc_irq_domain_ops, intc);
  454. if (!intc->domain)
  455. return -ENOMEM;
  456. for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
  457. if (irqs_reserved & BIT(i))
  458. continue;
  459. irq = platform_get_irq_byname(pdev, irq_names[i]);
  460. if (irq <= 0) {
  461. ret = (irq == 0) ? -EINVAL : irq;
  462. goto fail_irq;
  463. }
  464. intc->irqs[i] = irq;
  465. host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
  466. if (!host_data) {
  467. ret = -ENOMEM;
  468. goto fail_irq;
  469. }
  470. host_data->intc = intc;
  471. host_data->host_irq = i;
  472. irq_set_handler_data(irq, host_data);
  473. irq_set_chained_handler(irq, pruss_intc_irq_handler);
  474. }
  475. return 0;
  476. fail_irq:
  477. while (--i >= 0) {
  478. if (intc->irqs[i])
  479. irq_set_chained_handler_and_data(intc->irqs[i], NULL,
  480. NULL);
  481. }
  482. irq_domain_remove(intc->domain);
  483. return ret;
  484. }
  485. static int pruss_intc_remove(struct platform_device *pdev)
  486. {
  487. struct pruss_intc *intc = platform_get_drvdata(pdev);
  488. u8 max_system_events = intc->soc_config->num_system_events;
  489. unsigned int hwirq;
  490. int i;
  491. for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
  492. if (intc->irqs[i])
  493. irq_set_chained_handler_and_data(intc->irqs[i], NULL,
  494. NULL);
  495. }
  496. for (hwirq = 0; hwirq < max_system_events; hwirq++)
  497. irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
  498. irq_domain_remove(intc->domain);
  499. return 0;
  500. }
  501. static const struct pruss_intc_match_data pruss_intc_data = {
  502. .num_system_events = 64,
  503. .num_host_events = 10,
  504. };
  505. static const struct pruss_intc_match_data icssg_intc_data = {
  506. .num_system_events = 160,
  507. .num_host_events = 20,
  508. };
  509. static const struct of_device_id pruss_intc_of_match[] = {
  510. {
  511. .compatible = "ti,pruss-intc",
  512. .data = &pruss_intc_data,
  513. },
  514. {
  515. .compatible = "ti,icssg-intc",
  516. .data = &icssg_intc_data,
  517. },
  518. { /* sentinel */ },
  519. };
  520. MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
  521. static struct platform_driver pruss_intc_driver = {
  522. .driver = {
  523. .name = "pruss-intc",
  524. .of_match_table = pruss_intc_of_match,
  525. .suppress_bind_attrs = true,
  526. },
  527. .probe = pruss_intc_probe,
  528. .remove = pruss_intc_remove,
  529. };
  530. module_platform_driver(pruss_intc_driver);
  531. MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
  532. MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
  533. MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
  534. MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
  535. MODULE_LICENSE("GPL v2");