irq-pic32-evic.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Cristian Birsan <cristian.birsan@microchip.com>
  4. * Joshua Henderson <joshua.henderson@microchip.com>
  5. * Copyright (C) 2016 Microchip Technology Inc. All rights reserved.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/of_address.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/irqchip.h>
  15. #include <linux/irq.h>
  16. #include <asm/irq.h>
  17. #include <asm/traps.h>
  18. #include <asm/mach-pic32/pic32.h>
  19. #define REG_INTCON 0x0000
  20. #define REG_INTSTAT 0x0020
  21. #define REG_IFS_OFFSET 0x0040
  22. #define REG_IEC_OFFSET 0x00C0
  23. #define REG_IPC_OFFSET 0x0140
  24. #define REG_OFF_OFFSET 0x0540
  25. #define MAJPRI_MASK 0x07
  26. #define SUBPRI_MASK 0x03
  27. #define PRIORITY_MASK 0x1F
  28. #define PIC32_INT_PRI(pri, subpri) \
  29. ((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK))
  30. struct evic_chip_data {
  31. u32 irq_types[NR_IRQS];
  32. u32 ext_irqs[8];
  33. };
  34. static struct irq_domain *evic_irq_domain;
  35. static void __iomem *evic_base;
  36. asmlinkage void __weak plat_irq_dispatch(void)
  37. {
  38. unsigned int irq, hwirq;
  39. hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
  40. irq = irq_linear_revmap(evic_irq_domain, hwirq);
  41. do_IRQ(irq);
  42. }
  43. static struct evic_chip_data *irqd_to_priv(struct irq_data *data)
  44. {
  45. return (struct evic_chip_data *)data->domain->host_data;
  46. }
  47. static int pic32_set_ext_polarity(int bit, u32 type)
  48. {
  49. /*
  50. * External interrupts can be either edge rising or edge falling,
  51. * but not both.
  52. */
  53. switch (type) {
  54. case IRQ_TYPE_EDGE_RISING:
  55. writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
  56. break;
  57. case IRQ_TYPE_EDGE_FALLING:
  58. writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
  59. break;
  60. default:
  61. return -EINVAL;
  62. }
  63. return 0;
  64. }
  65. static int pic32_set_type_edge(struct irq_data *data,
  66. unsigned int flow_type)
  67. {
  68. struct evic_chip_data *priv = irqd_to_priv(data);
  69. int ret;
  70. int i;
  71. if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
  72. return -EBADR;
  73. /* set polarity for external interrupts only */
  74. for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
  75. if (priv->ext_irqs[i] == data->hwirq) {
  76. ret = pic32_set_ext_polarity(i, flow_type);
  77. if (ret)
  78. return ret;
  79. }
  80. }
  81. irqd_set_trigger_type(data, flow_type);
  82. return IRQ_SET_MASK_OK;
  83. }
  84. static void pic32_bind_evic_interrupt(int irq, int set)
  85. {
  86. writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
  87. }
  88. static void pic32_set_irq_priority(int irq, int priority)
  89. {
  90. u32 reg, shift;
  91. reg = irq / 4;
  92. shift = (irq % 4) * 8;
  93. writel(PRIORITY_MASK << shift,
  94. evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
  95. writel(priority << shift,
  96. evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
  97. }
  98. #define IRQ_REG_MASK(_hwirq, _reg, _mask) \
  99. do { \
  100. _reg = _hwirq / 32; \
  101. _mask = 1 << (_hwirq % 32); \
  102. } while (0)
  103. static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
  104. irq_hw_number_t hw)
  105. {
  106. struct evic_chip_data *priv = d->host_data;
  107. struct irq_data *data;
  108. int ret;
  109. u32 iecclr, ifsclr;
  110. u32 reg, mask;
  111. ret = irq_map_generic_chip(d, virq, hw);
  112. if (ret)
  113. return ret;
  114. /*
  115. * Piggyback on xlate function to move to an alternate chip as necessary
  116. * at time of mapping instead of allowing the flow handler/chip to be
  117. * changed later. This requires all interrupts to be configured through
  118. * DT.
  119. */
  120. if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
  121. data = irq_domain_get_irq_data(d, virq);
  122. irqd_set_trigger_type(data, priv->irq_types[hw]);
  123. irq_setup_alt_chip(data, priv->irq_types[hw]);
  124. }
  125. IRQ_REG_MASK(hw, reg, mask);
  126. iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
  127. ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);
  128. /* mask and clear flag */
  129. writel(mask, evic_base + iecclr);
  130. writel(mask, evic_base + ifsclr);
  131. /* default priority is required */
  132. pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));
  133. return ret;
  134. }
  135. int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
  136. const u32 *intspec, unsigned int intsize,
  137. irq_hw_number_t *out_hwirq, unsigned int *out_type)
  138. {
  139. struct evic_chip_data *priv = d->host_data;
  140. if (WARN_ON(intsize < 2))
  141. return -EINVAL;
  142. if (WARN_ON(intspec[0] >= NR_IRQS))
  143. return -EINVAL;
  144. *out_hwirq = intspec[0];
  145. *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
  146. priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;
  147. return 0;
  148. }
  149. static const struct irq_domain_ops pic32_irq_domain_ops = {
  150. .map = pic32_irq_domain_map,
  151. .xlate = pic32_irq_domain_xlate,
  152. };
  153. static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
  154. {
  155. struct device_node *node = irq_domain_get_of_node(domain);
  156. struct evic_chip_data *priv = domain->host_data;
  157. struct property *prop;
  158. const __le32 *p;
  159. u32 hwirq;
  160. int i = 0;
  161. const char *pname = "microchip,external-irqs";
  162. of_property_for_each_u32(node, pname, prop, p, hwirq) {
  163. if (i >= ARRAY_SIZE(priv->ext_irqs)) {
  164. pr_warn("More than %d external irq, skip rest\n",
  165. ARRAY_SIZE(priv->ext_irqs));
  166. break;
  167. }
  168. priv->ext_irqs[i] = hwirq;
  169. i++;
  170. }
  171. }
  172. static int __init pic32_of_init(struct device_node *node,
  173. struct device_node *parent)
  174. {
  175. struct irq_chip_generic *gc;
  176. struct evic_chip_data *priv;
  177. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  178. int nchips, ret;
  179. int i;
  180. nchips = DIV_ROUND_UP(NR_IRQS, 32);
  181. evic_base = of_iomap(node, 0);
  182. if (!evic_base)
  183. return -ENOMEM;
  184. priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
  185. if (!priv) {
  186. ret = -ENOMEM;
  187. goto err_iounmap;
  188. }
  189. evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
  190. &pic32_irq_domain_ops,
  191. priv);
  192. if (!evic_irq_domain) {
  193. ret = -ENOMEM;
  194. goto err_free_priv;
  195. }
  196. /*
  197. * The PIC32 EVIC has a linear list of irqs and the type of each
  198. * irq is determined by the hardware peripheral the EVIC is arbitrating.
  199. * These irq types are defined in the datasheet as "persistent" and
  200. * "non-persistent" which are mapped here to level and edge
  201. * respectively. To manage the different flow handler requirements of
  202. * each irq type, different chip_types are used.
  203. */
  204. ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
  205. "evic-level", handle_level_irq,
  206. clr, 0, 0);
  207. if (ret)
  208. goto err_domain_remove;
  209. board_bind_eic_interrupt = &pic32_bind_evic_interrupt;
  210. for (i = 0; i < nchips; i++) {
  211. u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
  212. u32 iec = REG_IEC_OFFSET + (i * 0x10);
  213. gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);
  214. gc->reg_base = evic_base;
  215. gc->unused = 0;
  216. /*
  217. * Level/persistent interrupts have a special requirement that
  218. * the condition generating the interrupt be cleared before the
  219. * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
  220. * complete the interrupt with an ack.
  221. */
  222. gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
  223. gc->chip_types[0].handler = handle_fasteoi_irq;
  224. gc->chip_types[0].regs.ack = ifsclr;
  225. gc->chip_types[0].regs.mask = iec;
  226. gc->chip_types[0].chip.name = "evic-level";
  227. gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
  228. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  229. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  230. gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE;
  231. /* Edge interrupts */
  232. gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
  233. gc->chip_types[1].handler = handle_edge_irq;
  234. gc->chip_types[1].regs.ack = ifsclr;
  235. gc->chip_types[1].regs.mask = iec;
  236. gc->chip_types[1].chip.name = "evic-edge";
  237. gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
  238. gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
  239. gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
  240. gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge;
  241. gc->chip_types[1].chip.flags = IRQCHIP_SKIP_SET_WAKE;
  242. gc->private = &priv[i];
  243. }
  244. irq_set_default_host(evic_irq_domain);
  245. /*
  246. * External interrupts have software configurable edge polarity. These
  247. * interrupts are defined in DT allowing polarity to be configured only
  248. * for these interrupts when requested.
  249. */
  250. pic32_ext_irq_of_init(evic_irq_domain);
  251. return 0;
  252. err_domain_remove:
  253. irq_domain_remove(evic_irq_domain);
  254. err_free_priv:
  255. kfree(priv);
  256. err_iounmap:
  257. iounmap(evic_base);
  258. return ret;
  259. }
  260. IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);