irq-or1k-pic.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  4. * Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>
  5. */
  6. #include <linux/irq.h>
  7. #include <linux/irqchip.h>
  8. #include <linux/of.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/of_address.h>
  11. /* OR1K PIC implementation */
  12. struct or1k_pic_dev {
  13. struct irq_chip chip;
  14. irq_flow_handler_t handle;
  15. unsigned long flags;
  16. };
  17. /*
  18. * We're a couple of cycles faster than the generic implementations with
  19. * these 'fast' versions.
  20. */
  21. static void or1k_pic_mask(struct irq_data *data)
  22. {
  23. mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
  24. }
  25. static void or1k_pic_unmask(struct irq_data *data)
  26. {
  27. mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
  28. }
  29. static void or1k_pic_ack(struct irq_data *data)
  30. {
  31. mtspr(SPR_PICSR, (1UL << data->hwirq));
  32. }
  33. static void or1k_pic_mask_ack(struct irq_data *data)
  34. {
  35. mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
  36. mtspr(SPR_PICSR, (1UL << data->hwirq));
  37. }
  38. /*
  39. * There are two oddities with the OR1200 PIC implementation:
  40. * i) LEVEL-triggered interrupts are latched and need to be cleared
  41. * ii) the interrupt latch is cleared by writing a 0 to the bit,
  42. * as opposed to a 1 as mandated by the spec
  43. */
  44. static void or1k_pic_or1200_ack(struct irq_data *data)
  45. {
  46. mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
  47. }
  48. static void or1k_pic_or1200_mask_ack(struct irq_data *data)
  49. {
  50. mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
  51. mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
  52. }
  53. static struct or1k_pic_dev or1k_pic_level = {
  54. .chip = {
  55. .name = "or1k-PIC-level",
  56. .irq_unmask = or1k_pic_unmask,
  57. .irq_mask = or1k_pic_mask,
  58. .irq_mask_ack = or1k_pic_mask_ack,
  59. },
  60. .handle = handle_level_irq,
  61. .flags = IRQ_LEVEL | IRQ_NOPROBE,
  62. };
  63. static struct or1k_pic_dev or1k_pic_edge = {
  64. .chip = {
  65. .name = "or1k-PIC-edge",
  66. .irq_unmask = or1k_pic_unmask,
  67. .irq_mask = or1k_pic_mask,
  68. .irq_ack = or1k_pic_ack,
  69. .irq_mask_ack = or1k_pic_mask_ack,
  70. },
  71. .handle = handle_edge_irq,
  72. .flags = IRQ_LEVEL | IRQ_NOPROBE,
  73. };
  74. static struct or1k_pic_dev or1k_pic_or1200 = {
  75. .chip = {
  76. .name = "or1200-PIC",
  77. .irq_unmask = or1k_pic_unmask,
  78. .irq_mask = or1k_pic_mask,
  79. .irq_ack = or1k_pic_or1200_ack,
  80. .irq_mask_ack = or1k_pic_or1200_mask_ack,
  81. },
  82. .handle = handle_level_irq,
  83. .flags = IRQ_LEVEL | IRQ_NOPROBE,
  84. };
  85. static struct irq_domain *root_domain;
  86. static inline int pic_get_irq(int first)
  87. {
  88. int hwirq;
  89. hwirq = ffs(mfspr(SPR_PICSR) >> first);
  90. if (!hwirq)
  91. return NO_IRQ;
  92. else
  93. hwirq = hwirq + first - 1;
  94. return hwirq;
  95. }
  96. static void or1k_pic_handle_irq(struct pt_regs *regs)
  97. {
  98. int irq = -1;
  99. while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
  100. handle_domain_irq(root_domain, irq, regs);
  101. }
  102. static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  103. {
  104. struct or1k_pic_dev *pic = d->host_data;
  105. irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
  106. irq_set_status_flags(irq, pic->flags);
  107. return 0;
  108. }
  109. static const struct irq_domain_ops or1k_irq_domain_ops = {
  110. .xlate = irq_domain_xlate_onecell,
  111. .map = or1k_map,
  112. };
  113. /*
  114. * This sets up the IRQ domain for the PIC built in to the OpenRISC
  115. * 1000 CPU. This is the "root" domain as these are the interrupts
  116. * that directly trigger an exception in the CPU.
  117. */
  118. static int __init or1k_pic_init(struct device_node *node,
  119. struct or1k_pic_dev *pic)
  120. {
  121. /* Disable all interrupts until explicitly requested */
  122. mtspr(SPR_PICMR, (0UL));
  123. root_domain = irq_domain_add_linear(node, 32, &or1k_irq_domain_ops,
  124. pic);
  125. set_handle_irq(or1k_pic_handle_irq);
  126. return 0;
  127. }
  128. static int __init or1k_pic_or1200_init(struct device_node *node,
  129. struct device_node *parent)
  130. {
  131. return or1k_pic_init(node, &or1k_pic_or1200);
  132. }
  133. IRQCHIP_DECLARE(or1k_pic_or1200, "opencores,or1200-pic", or1k_pic_or1200_init);
  134. IRQCHIP_DECLARE(or1k_pic, "opencores,or1k-pic", or1k_pic_or1200_init);
  135. static int __init or1k_pic_level_init(struct device_node *node,
  136. struct device_node *parent)
  137. {
  138. return or1k_pic_init(node, &or1k_pic_level);
  139. }
  140. IRQCHIP_DECLARE(or1k_pic_level, "opencores,or1k-pic-level",
  141. or1k_pic_level_init);
  142. static int __init or1k_pic_edge_init(struct device_node *node,
  143. struct device_node *parent)
  144. {
  145. return or1k_pic_init(node, &or1k_pic_edge);
  146. }
  147. IRQCHIP_DECLARE(or1k_pic_edge, "opencores,or1k-pic-edge", or1k_pic_edge_init);