irq-omap-intc.c 9.5 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/irq.c
  3. *
  4. * Interrupt handler for OMAP2 boards.
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Author: Paul Mundt <paul.mundt@nokia.com>
  8. *
  9. * This file is subject to the terms and conditions of the GNU General Public
  10. * License. See the file "COPYING" in the main directory of this archive
  11. * for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <asm/exception.h>
  19. #include <linux/irqchip.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/irqchip/irq-omap-intc.h>
  25. /* selected INTC register offsets */
  26. #define INTC_REVISION 0x0000
  27. #define INTC_SYSCONFIG 0x0010
  28. #define INTC_SYSSTATUS 0x0014
  29. #define INTC_SIR 0x0040
  30. #define INTC_CONTROL 0x0048
  31. #define INTC_PROTECTION 0x004C
  32. #define INTC_IDLE 0x0050
  33. #define INTC_THRESHOLD 0x0068
  34. #define INTC_MIR0 0x0084
  35. #define INTC_MIR_CLEAR0 0x0088
  36. #define INTC_MIR_SET0 0x008c
  37. #define INTC_PENDING_IRQ0 0x0098
  38. #define INTC_PENDING_IRQ1 0x00b8
  39. #define INTC_PENDING_IRQ2 0x00d8
  40. #define INTC_PENDING_IRQ3 0x00f8
  41. #define INTC_ILR0 0x0100
  42. #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
  43. #define SPURIOUSIRQ_MASK (0x1ffffff << 7)
  44. #define INTCPS_NR_ILR_REGS 128
  45. #define INTCPS_NR_MIR_REGS 4
  46. #define INTC_IDLE_FUNCIDLE (1 << 0)
  47. #define INTC_IDLE_TURBO (1 << 1)
  48. #define INTC_PROTECTION_ENABLE (1 << 0)
  49. struct omap_intc_regs {
  50. u32 sysconfig;
  51. u32 protection;
  52. u32 idle;
  53. u32 threshold;
  54. u32 ilr[INTCPS_NR_ILR_REGS];
  55. u32 mir[INTCPS_NR_MIR_REGS];
  56. };
  57. static struct omap_intc_regs intc_context;
  58. static struct irq_domain *domain;
  59. static void __iomem *omap_irq_base;
  60. static int omap_nr_pending;
  61. static int omap_nr_irqs;
  62. static void intc_writel(u32 reg, u32 val)
  63. {
  64. writel_relaxed(val, omap_irq_base + reg);
  65. }
  66. static u32 intc_readl(u32 reg)
  67. {
  68. return readl_relaxed(omap_irq_base + reg);
  69. }
  70. void omap_intc_save_context(void)
  71. {
  72. int i;
  73. intc_context.sysconfig =
  74. intc_readl(INTC_SYSCONFIG);
  75. intc_context.protection =
  76. intc_readl(INTC_PROTECTION);
  77. intc_context.idle =
  78. intc_readl(INTC_IDLE);
  79. intc_context.threshold =
  80. intc_readl(INTC_THRESHOLD);
  81. for (i = 0; i < omap_nr_irqs; i++)
  82. intc_context.ilr[i] =
  83. intc_readl((INTC_ILR0 + 0x4 * i));
  84. for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
  85. intc_context.mir[i] =
  86. intc_readl(INTC_MIR0 + (0x20 * i));
  87. }
  88. void omap_intc_restore_context(void)
  89. {
  90. int i;
  91. intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
  92. intc_writel(INTC_PROTECTION, intc_context.protection);
  93. intc_writel(INTC_IDLE, intc_context.idle);
  94. intc_writel(INTC_THRESHOLD, intc_context.threshold);
  95. for (i = 0; i < omap_nr_irqs; i++)
  96. intc_writel(INTC_ILR0 + 0x4 * i,
  97. intc_context.ilr[i]);
  98. for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
  99. intc_writel(INTC_MIR0 + 0x20 * i,
  100. intc_context.mir[i]);
  101. /* MIRs are saved and restore with other PRCM registers */
  102. }
  103. void omap3_intc_prepare_idle(void)
  104. {
  105. /*
  106. * Disable autoidle as it can stall interrupt controller,
  107. * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
  108. */
  109. intc_writel(INTC_SYSCONFIG, 0);
  110. intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
  111. }
  112. void omap3_intc_resume_idle(void)
  113. {
  114. /* Re-enable autoidle */
  115. intc_writel(INTC_SYSCONFIG, 1);
  116. intc_writel(INTC_IDLE, 0);
  117. }
  118. /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  119. static void omap_ack_irq(struct irq_data *d)
  120. {
  121. intc_writel(INTC_CONTROL, 0x1);
  122. }
  123. static void omap_mask_ack_irq(struct irq_data *d)
  124. {
  125. irq_gc_mask_disable_reg(d);
  126. omap_ack_irq(d);
  127. }
  128. static void __init omap_irq_soft_reset(void)
  129. {
  130. unsigned long tmp;
  131. tmp = intc_readl(INTC_REVISION) & 0xff;
  132. pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
  133. omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
  134. tmp = intc_readl(INTC_SYSCONFIG);
  135. tmp |= 1 << 1; /* soft reset */
  136. intc_writel(INTC_SYSCONFIG, tmp);
  137. while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
  138. /* Wait for reset to complete */;
  139. /* Enable autoidle */
  140. intc_writel(INTC_SYSCONFIG, 1 << 0);
  141. }
  142. int omap_irq_pending(void)
  143. {
  144. int i;
  145. for (i = 0; i < omap_nr_pending; i++)
  146. if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
  147. return 1;
  148. return 0;
  149. }
  150. void omap3_intc_suspend(void)
  151. {
  152. /* A pending interrupt would prevent OMAP from entering suspend */
  153. omap_ack_irq(NULL);
  154. }
  155. static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
  156. {
  157. int ret;
  158. int i;
  159. ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
  160. handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
  161. IRQ_LEVEL, 0);
  162. if (ret) {
  163. pr_warn("Failed to allocate irq chips\n");
  164. return ret;
  165. }
  166. for (i = 0; i < omap_nr_pending; i++) {
  167. struct irq_chip_generic *gc;
  168. struct irq_chip_type *ct;
  169. gc = irq_get_domain_generic_chip(d, 32 * i);
  170. gc->reg_base = base;
  171. ct = gc->chip_types;
  172. ct->type = IRQ_TYPE_LEVEL_MASK;
  173. ct->chip.irq_ack = omap_mask_ack_irq;
  174. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  175. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  176. ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
  177. ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
  178. ct->regs.disable = INTC_MIR_SET0 + 32 * i;
  179. }
  180. return 0;
  181. }
  182. static void __init omap_alloc_gc_legacy(void __iomem *base,
  183. unsigned int irq_start, unsigned int num)
  184. {
  185. struct irq_chip_generic *gc;
  186. struct irq_chip_type *ct;
  187. gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
  188. handle_level_irq);
  189. ct = gc->chip_types;
  190. ct->chip.irq_ack = omap_mask_ack_irq;
  191. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  192. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  193. ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
  194. ct->regs.enable = INTC_MIR_CLEAR0;
  195. ct->regs.disable = INTC_MIR_SET0;
  196. irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  197. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  198. }
  199. static int __init omap_init_irq_of(struct device_node *node)
  200. {
  201. int ret;
  202. omap_irq_base = of_iomap(node, 0);
  203. if (WARN_ON(!omap_irq_base))
  204. return -ENOMEM;
  205. domain = irq_domain_add_linear(node, omap_nr_irqs,
  206. &irq_generic_chip_ops, NULL);
  207. omap_irq_soft_reset();
  208. ret = omap_alloc_gc_of(domain, omap_irq_base);
  209. if (ret < 0)
  210. irq_domain_remove(domain);
  211. return ret;
  212. }
  213. static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
  214. {
  215. int j, irq_base;
  216. omap_irq_base = ioremap(base, SZ_4K);
  217. if (WARN_ON(!omap_irq_base))
  218. return -ENOMEM;
  219. irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
  220. if (irq_base < 0) {
  221. pr_warn("Couldn't allocate IRQ numbers\n");
  222. irq_base = 0;
  223. }
  224. domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
  225. &irq_domain_simple_ops, NULL);
  226. omap_irq_soft_reset();
  227. for (j = 0; j < omap_nr_irqs; j += 32)
  228. omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
  229. return 0;
  230. }
  231. static void __init omap_irq_enable_protection(void)
  232. {
  233. u32 reg;
  234. reg = intc_readl(INTC_PROTECTION);
  235. reg |= INTC_PROTECTION_ENABLE;
  236. intc_writel(INTC_PROTECTION, reg);
  237. }
  238. static int __init omap_init_irq(u32 base, struct device_node *node)
  239. {
  240. int ret;
  241. /*
  242. * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
  243. * depends is still not ready for linear IRQ domains; because of that
  244. * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
  245. * linear IRQ Domain until that driver is finally fixed.
  246. */
  247. if (of_device_is_compatible(node, "ti,omap2-intc") ||
  248. of_device_is_compatible(node, "ti,omap3-intc")) {
  249. struct resource res;
  250. if (of_address_to_resource(node, 0, &res))
  251. return -ENOMEM;
  252. base = res.start;
  253. ret = omap_init_irq_legacy(base, node);
  254. } else if (node) {
  255. ret = omap_init_irq_of(node);
  256. } else {
  257. ret = omap_init_irq_legacy(base, NULL);
  258. }
  259. if (ret == 0)
  260. omap_irq_enable_protection();
  261. return ret;
  262. }
  263. static asmlinkage void __exception_irq_entry
  264. omap_intc_handle_irq(struct pt_regs *regs)
  265. {
  266. extern unsigned long irq_err_count;
  267. u32 irqnr;
  268. irqnr = intc_readl(INTC_SIR);
  269. /*
  270. * A spurious IRQ can result if interrupt that triggered the
  271. * sorting is no longer active during the sorting (10 INTC
  272. * functional clock cycles after interrupt assertion). Or a
  273. * change in interrupt mask affected the result during sorting
  274. * time. There is no special handling required except ignoring
  275. * the SIR register value just read and retrying.
  276. * See section 6.2.5 of AM335x TRM Literature Number: SPRUH73K
  277. *
  278. * Many a times, a spurious interrupt situation has been fixed
  279. * by adding a flush for the posted write acking the IRQ in
  280. * the device driver. Typically, this is going be the device
  281. * driver whose interrupt was handled just before the spurious
  282. * IRQ occurred. Pay attention to those device drivers if you
  283. * run into hitting the spurious IRQ condition below.
  284. */
  285. if (unlikely((irqnr & SPURIOUSIRQ_MASK) == SPURIOUSIRQ_MASK)) {
  286. pr_err_once("%s: spurious irq!\n", __func__);
  287. irq_err_count++;
  288. omap_ack_irq(NULL);
  289. return;
  290. }
  291. irqnr &= ACTIVEIRQ_MASK;
  292. handle_domain_irq(domain, irqnr, regs);
  293. }
  294. static int __init intc_of_init(struct device_node *node,
  295. struct device_node *parent)
  296. {
  297. int ret;
  298. omap_nr_pending = 3;
  299. omap_nr_irqs = 96;
  300. if (WARN_ON(!node))
  301. return -ENODEV;
  302. if (of_device_is_compatible(node, "ti,dm814-intc") ||
  303. of_device_is_compatible(node, "ti,dm816-intc") ||
  304. of_device_is_compatible(node, "ti,am33xx-intc")) {
  305. omap_nr_irqs = 128;
  306. omap_nr_pending = 4;
  307. }
  308. ret = omap_init_irq(-1, of_node_get(node));
  309. if (ret < 0)
  310. return ret;
  311. set_handle_irq(omap_intc_handle_irq);
  312. return 0;
  313. }
  314. IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
  315. IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
  316. IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
  317. IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
  318. IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);