irq-mvebu-gicp.c 6.4 KB

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  1. /*
  2. * Copyright (C) 2017 Marvell
  3. *
  4. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/io.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/msi.h>
  14. #include <linux/of.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #include <dt-bindings/interrupt-controller/arm-gic.h>
  19. #define GICP_SETSPI_NSR_OFFSET 0x0
  20. #define GICP_CLRSPI_NSR_OFFSET 0x8
  21. struct mvebu_gicp_spi_range {
  22. unsigned int start;
  23. unsigned int count;
  24. };
  25. struct mvebu_gicp {
  26. struct mvebu_gicp_spi_range *spi_ranges;
  27. unsigned int spi_ranges_cnt;
  28. unsigned int spi_cnt;
  29. unsigned long *spi_bitmap;
  30. spinlock_t spi_lock;
  31. struct resource *res;
  32. struct device *dev;
  33. };
  34. static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
  35. {
  36. int i;
  37. for (i = 0; i < gicp->spi_ranges_cnt; i++) {
  38. struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
  39. if (idx < r->count)
  40. return r->start + idx;
  41. idx -= r->count;
  42. }
  43. return -EINVAL;
  44. }
  45. static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  46. {
  47. struct mvebu_gicp *gicp = data->chip_data;
  48. phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
  49. phys_addr_t clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
  50. msg[0].data = data->hwirq;
  51. msg[0].address_lo = lower_32_bits(setspi);
  52. msg[0].address_hi = upper_32_bits(setspi);
  53. msg[1].data = data->hwirq;
  54. msg[1].address_lo = lower_32_bits(clrspi);
  55. msg[1].address_hi = upper_32_bits(clrspi);
  56. }
  57. static struct irq_chip gicp_irq_chip = {
  58. .name = "GICP",
  59. .irq_mask = irq_chip_mask_parent,
  60. .irq_unmask = irq_chip_unmask_parent,
  61. .irq_eoi = irq_chip_eoi_parent,
  62. .irq_set_affinity = irq_chip_set_affinity_parent,
  63. .irq_set_type = irq_chip_set_type_parent,
  64. .irq_compose_msi_msg = gicp_compose_msi_msg,
  65. };
  66. static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  67. unsigned int nr_irqs, void *args)
  68. {
  69. struct mvebu_gicp *gicp = domain->host_data;
  70. struct irq_fwspec fwspec;
  71. unsigned int hwirq;
  72. int ret;
  73. spin_lock(&gicp->spi_lock);
  74. hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
  75. if (hwirq == gicp->spi_cnt) {
  76. spin_unlock(&gicp->spi_lock);
  77. return -ENOSPC;
  78. }
  79. __set_bit(hwirq, gicp->spi_bitmap);
  80. spin_unlock(&gicp->spi_lock);
  81. fwspec.fwnode = domain->parent->fwnode;
  82. fwspec.param_count = 3;
  83. fwspec.param[0] = GIC_SPI;
  84. fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
  85. /*
  86. * Assume edge rising for now, it will be properly set when
  87. * ->set_type() is called
  88. */
  89. fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
  90. ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  91. if (ret) {
  92. dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
  93. goto free_hwirq;
  94. }
  95. ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
  96. &gicp_irq_chip, gicp);
  97. if (ret)
  98. goto free_irqs_parent;
  99. return 0;
  100. free_irqs_parent:
  101. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  102. free_hwirq:
  103. spin_lock(&gicp->spi_lock);
  104. __clear_bit(hwirq, gicp->spi_bitmap);
  105. spin_unlock(&gicp->spi_lock);
  106. return ret;
  107. }
  108. static void gicp_irq_domain_free(struct irq_domain *domain,
  109. unsigned int virq, unsigned int nr_irqs)
  110. {
  111. struct mvebu_gicp *gicp = domain->host_data;
  112. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  113. if (d->hwirq >= gicp->spi_cnt) {
  114. dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
  115. return;
  116. }
  117. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  118. spin_lock(&gicp->spi_lock);
  119. __clear_bit(d->hwirq, gicp->spi_bitmap);
  120. spin_unlock(&gicp->spi_lock);
  121. }
  122. static const struct irq_domain_ops gicp_domain_ops = {
  123. .alloc = gicp_irq_domain_alloc,
  124. .free = gicp_irq_domain_free,
  125. };
  126. static struct irq_chip gicp_msi_irq_chip = {
  127. .name = "GICP",
  128. .irq_set_type = irq_chip_set_type_parent,
  129. .flags = IRQCHIP_SUPPORTS_LEVEL_MSI,
  130. };
  131. static struct msi_domain_ops gicp_msi_ops = {
  132. };
  133. static struct msi_domain_info gicp_msi_domain_info = {
  134. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  135. MSI_FLAG_LEVEL_CAPABLE),
  136. .ops = &gicp_msi_ops,
  137. .chip = &gicp_msi_irq_chip,
  138. };
  139. static int mvebu_gicp_probe(struct platform_device *pdev)
  140. {
  141. struct mvebu_gicp *gicp;
  142. struct irq_domain *inner_domain, *plat_domain, *parent_domain;
  143. struct device_node *node = pdev->dev.of_node;
  144. struct device_node *irq_parent_dn;
  145. int ret, i;
  146. gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
  147. if (!gicp)
  148. return -ENOMEM;
  149. gicp->dev = &pdev->dev;
  150. spin_lock_init(&gicp->spi_lock);
  151. gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  152. if (!gicp->res)
  153. return -ENODEV;
  154. ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
  155. if (ret < 0)
  156. return ret;
  157. gicp->spi_ranges_cnt = ret / 2;
  158. gicp->spi_ranges =
  159. devm_kcalloc(&pdev->dev,
  160. gicp->spi_ranges_cnt,
  161. sizeof(struct mvebu_gicp_spi_range),
  162. GFP_KERNEL);
  163. if (!gicp->spi_ranges)
  164. return -ENOMEM;
  165. for (i = 0; i < gicp->spi_ranges_cnt; i++) {
  166. of_property_read_u32_index(node, "marvell,spi-ranges",
  167. i * 2,
  168. &gicp->spi_ranges[i].start);
  169. of_property_read_u32_index(node, "marvell,spi-ranges",
  170. i * 2 + 1,
  171. &gicp->spi_ranges[i].count);
  172. gicp->spi_cnt += gicp->spi_ranges[i].count;
  173. }
  174. gicp->spi_bitmap = devm_kcalloc(&pdev->dev,
  175. BITS_TO_LONGS(gicp->spi_cnt), sizeof(long),
  176. GFP_KERNEL);
  177. if (!gicp->spi_bitmap)
  178. return -ENOMEM;
  179. irq_parent_dn = of_irq_find_parent(node);
  180. if (!irq_parent_dn) {
  181. dev_err(&pdev->dev, "failed to find parent IRQ node\n");
  182. return -ENODEV;
  183. }
  184. parent_domain = irq_find_host(irq_parent_dn);
  185. if (!parent_domain) {
  186. dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
  187. return -ENODEV;
  188. }
  189. inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
  190. gicp->spi_cnt,
  191. of_node_to_fwnode(node),
  192. &gicp_domain_ops, gicp);
  193. if (!inner_domain)
  194. return -ENOMEM;
  195. plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
  196. &gicp_msi_domain_info,
  197. inner_domain);
  198. if (!plat_domain) {
  199. irq_domain_remove(inner_domain);
  200. return -ENOMEM;
  201. }
  202. platform_set_drvdata(pdev, gicp);
  203. return 0;
  204. }
  205. static const struct of_device_id mvebu_gicp_of_match[] = {
  206. { .compatible = "marvell,ap806-gicp", },
  207. {},
  208. };
  209. static struct platform_driver mvebu_gicp_driver = {
  210. .probe = mvebu_gicp_probe,
  211. .driver = {
  212. .name = "mvebu-gicp",
  213. .of_match_table = mvebu_gicp_of_match,
  214. },
  215. };
  216. builtin_platform_driver(mvebu_gicp_driver);