irq-mips-gic.c 20 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
  7. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  8. */
  9. #define pr_fmt(fmt) "irq-mips-gic: " fmt
  10. #include <linux/bitmap.h>
  11. #include <linux/clocksource.h>
  12. #include <linux/cpuhotplug.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqchip.h>
  17. #include <linux/of_address.h>
  18. #include <linux/percpu.h>
  19. #include <linux/sched.h>
  20. #include <linux/smp.h>
  21. #include <asm/mips-cps.h>
  22. #include <asm/setup.h>
  23. #include <asm/traps.h>
  24. #include <dt-bindings/interrupt-controller/mips-gic.h>
  25. #define GIC_MAX_INTRS 256
  26. #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
  27. /* Add 2 to convert GIC CPU pin to core interrupt */
  28. #define GIC_CPU_PIN_OFFSET 2
  29. /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
  30. #define GIC_PIN_TO_VEC_OFFSET 1
  31. /* Convert between local/shared IRQ number and GIC HW IRQ number. */
  32. #define GIC_LOCAL_HWIRQ_BASE 0
  33. #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
  34. #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
  35. #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
  36. #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
  37. #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
  38. void __iomem *mips_gic_base;
  39. static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
  40. static DEFINE_SPINLOCK(gic_lock);
  41. static struct irq_domain *gic_irq_domain;
  42. static struct irq_domain *gic_ipi_domain;
  43. static int gic_shared_intrs;
  44. static unsigned int gic_cpu_pin;
  45. static unsigned int timer_cpu_pin;
  46. static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  47. static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
  48. static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
  49. static struct gic_all_vpes_chip_data {
  50. u32 map;
  51. bool mask;
  52. } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
  53. static void gic_clear_pcpu_masks(unsigned int intr)
  54. {
  55. unsigned int i;
  56. /* Clear the interrupt's bit in all pcpu_masks */
  57. for_each_possible_cpu(i)
  58. clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
  59. }
  60. static bool gic_local_irq_is_routable(int intr)
  61. {
  62. u32 vpe_ctl;
  63. /* All local interrupts are routable in EIC mode. */
  64. if (cpu_has_veic)
  65. return true;
  66. vpe_ctl = read_gic_vl_ctl();
  67. switch (intr) {
  68. case GIC_LOCAL_INT_TIMER:
  69. return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
  70. case GIC_LOCAL_INT_PERFCTR:
  71. return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
  72. case GIC_LOCAL_INT_FDC:
  73. return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
  74. case GIC_LOCAL_INT_SWINT0:
  75. case GIC_LOCAL_INT_SWINT1:
  76. return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
  77. default:
  78. return true;
  79. }
  80. }
  81. static void gic_bind_eic_interrupt(int irq, int set)
  82. {
  83. /* Convert irq vector # to hw int # */
  84. irq -= GIC_PIN_TO_VEC_OFFSET;
  85. /* Set irq to use shadow set */
  86. write_gic_vl_eic_shadow_set(irq, set);
  87. }
  88. static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
  89. {
  90. irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
  91. write_gic_wedge(GIC_WEDGE_RW | hwirq);
  92. }
  93. int gic_get_c0_compare_int(void)
  94. {
  95. if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
  96. return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  97. return irq_create_mapping(gic_irq_domain,
  98. GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
  99. }
  100. int gic_get_c0_perfcount_int(void)
  101. {
  102. if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
  103. /* Is the performance counter shared with the timer? */
  104. if (cp0_perfcount_irq < 0)
  105. return -1;
  106. return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
  107. }
  108. return irq_create_mapping(gic_irq_domain,
  109. GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
  110. }
  111. int gic_get_c0_fdc_int(void)
  112. {
  113. if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
  114. /* Is the FDC IRQ even present? */
  115. if (cp0_fdc_irq < 0)
  116. return -1;
  117. return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
  118. }
  119. return irq_create_mapping(gic_irq_domain,
  120. GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
  121. }
  122. static void gic_handle_shared_int(bool chained)
  123. {
  124. unsigned int intr, virq;
  125. unsigned long *pcpu_mask;
  126. DECLARE_BITMAP(pending, GIC_MAX_INTRS);
  127. /* Get per-cpu bitmaps */
  128. pcpu_mask = this_cpu_ptr(pcpu_masks);
  129. if (mips_cm_is64)
  130. __ioread64_copy(pending, addr_gic_pend(),
  131. DIV_ROUND_UP(gic_shared_intrs, 64));
  132. else
  133. __ioread32_copy(pending, addr_gic_pend(),
  134. DIV_ROUND_UP(gic_shared_intrs, 32));
  135. bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
  136. for_each_set_bit(intr, pending, gic_shared_intrs) {
  137. virq = irq_linear_revmap(gic_irq_domain,
  138. GIC_SHARED_TO_HWIRQ(intr));
  139. if (chained)
  140. generic_handle_irq(virq);
  141. else
  142. do_IRQ(virq);
  143. }
  144. }
  145. static void gic_mask_irq(struct irq_data *d)
  146. {
  147. unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
  148. write_gic_rmask(intr);
  149. gic_clear_pcpu_masks(intr);
  150. }
  151. static void gic_unmask_irq(struct irq_data *d)
  152. {
  153. unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
  154. unsigned int cpu;
  155. write_gic_smask(intr);
  156. gic_clear_pcpu_masks(intr);
  157. cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
  158. set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
  159. }
  160. static void gic_ack_irq(struct irq_data *d)
  161. {
  162. unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
  163. write_gic_wedge(irq);
  164. }
  165. static int gic_set_type(struct irq_data *d, unsigned int type)
  166. {
  167. unsigned int irq, pol, trig, dual;
  168. unsigned long flags;
  169. irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
  170. spin_lock_irqsave(&gic_lock, flags);
  171. switch (type & IRQ_TYPE_SENSE_MASK) {
  172. case IRQ_TYPE_EDGE_FALLING:
  173. pol = GIC_POL_FALLING_EDGE;
  174. trig = GIC_TRIG_EDGE;
  175. dual = GIC_DUAL_SINGLE;
  176. break;
  177. case IRQ_TYPE_EDGE_RISING:
  178. pol = GIC_POL_RISING_EDGE;
  179. trig = GIC_TRIG_EDGE;
  180. dual = GIC_DUAL_SINGLE;
  181. break;
  182. case IRQ_TYPE_EDGE_BOTH:
  183. pol = 0; /* Doesn't matter */
  184. trig = GIC_TRIG_EDGE;
  185. dual = GIC_DUAL_DUAL;
  186. break;
  187. case IRQ_TYPE_LEVEL_LOW:
  188. pol = GIC_POL_ACTIVE_LOW;
  189. trig = GIC_TRIG_LEVEL;
  190. dual = GIC_DUAL_SINGLE;
  191. break;
  192. case IRQ_TYPE_LEVEL_HIGH:
  193. default:
  194. pol = GIC_POL_ACTIVE_HIGH;
  195. trig = GIC_TRIG_LEVEL;
  196. dual = GIC_DUAL_SINGLE;
  197. break;
  198. }
  199. change_gic_pol(irq, pol);
  200. change_gic_trig(irq, trig);
  201. change_gic_dual(irq, dual);
  202. if (trig == GIC_TRIG_EDGE)
  203. irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
  204. handle_edge_irq, NULL);
  205. else
  206. irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
  207. handle_level_irq, NULL);
  208. spin_unlock_irqrestore(&gic_lock, flags);
  209. return 0;
  210. }
  211. #ifdef CONFIG_SMP
  212. static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
  213. bool force)
  214. {
  215. unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
  216. unsigned long flags;
  217. unsigned int cpu;
  218. cpu = cpumask_first_and(cpumask, cpu_online_mask);
  219. if (cpu >= NR_CPUS)
  220. return -EINVAL;
  221. /* Assumption : cpumask refers to a single CPU */
  222. spin_lock_irqsave(&gic_lock, flags);
  223. /* Re-route this IRQ */
  224. write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
  225. /* Update the pcpu_masks */
  226. gic_clear_pcpu_masks(irq);
  227. if (read_gic_mask(irq))
  228. set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
  229. irq_data_update_effective_affinity(d, cpumask_of(cpu));
  230. spin_unlock_irqrestore(&gic_lock, flags);
  231. return IRQ_SET_MASK_OK;
  232. }
  233. #endif
  234. static struct irq_chip gic_level_irq_controller = {
  235. .name = "MIPS GIC",
  236. .irq_mask = gic_mask_irq,
  237. .irq_unmask = gic_unmask_irq,
  238. .irq_set_type = gic_set_type,
  239. #ifdef CONFIG_SMP
  240. .irq_set_affinity = gic_set_affinity,
  241. #endif
  242. };
  243. static struct irq_chip gic_edge_irq_controller = {
  244. .name = "MIPS GIC",
  245. .irq_ack = gic_ack_irq,
  246. .irq_mask = gic_mask_irq,
  247. .irq_unmask = gic_unmask_irq,
  248. .irq_set_type = gic_set_type,
  249. #ifdef CONFIG_SMP
  250. .irq_set_affinity = gic_set_affinity,
  251. #endif
  252. .ipi_send_single = gic_send_ipi,
  253. };
  254. static void gic_handle_local_int(bool chained)
  255. {
  256. unsigned long pending, masked;
  257. unsigned int intr, virq;
  258. pending = read_gic_vl_pend();
  259. masked = read_gic_vl_mask();
  260. bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
  261. for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
  262. virq = irq_linear_revmap(gic_irq_domain,
  263. GIC_LOCAL_TO_HWIRQ(intr));
  264. if (chained)
  265. generic_handle_irq(virq);
  266. else
  267. do_IRQ(virq);
  268. }
  269. }
  270. static void gic_mask_local_irq(struct irq_data *d)
  271. {
  272. int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
  273. write_gic_vl_rmask(BIT(intr));
  274. }
  275. static void gic_unmask_local_irq(struct irq_data *d)
  276. {
  277. int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
  278. write_gic_vl_smask(BIT(intr));
  279. }
  280. static struct irq_chip gic_local_irq_controller = {
  281. .name = "MIPS GIC Local",
  282. .irq_mask = gic_mask_local_irq,
  283. .irq_unmask = gic_unmask_local_irq,
  284. };
  285. static void gic_mask_local_irq_all_vpes(struct irq_data *d)
  286. {
  287. struct gic_all_vpes_chip_data *cd;
  288. unsigned long flags;
  289. int intr, cpu;
  290. intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
  291. cd = irq_data_get_irq_chip_data(d);
  292. cd->mask = false;
  293. spin_lock_irqsave(&gic_lock, flags);
  294. for_each_online_cpu(cpu) {
  295. write_gic_vl_other(mips_cm_vp_id(cpu));
  296. write_gic_vo_rmask(BIT(intr));
  297. }
  298. spin_unlock_irqrestore(&gic_lock, flags);
  299. }
  300. static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
  301. {
  302. struct gic_all_vpes_chip_data *cd;
  303. unsigned long flags;
  304. int intr, cpu;
  305. intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
  306. cd = irq_data_get_irq_chip_data(d);
  307. cd->mask = true;
  308. spin_lock_irqsave(&gic_lock, flags);
  309. for_each_online_cpu(cpu) {
  310. write_gic_vl_other(mips_cm_vp_id(cpu));
  311. write_gic_vo_smask(BIT(intr));
  312. }
  313. spin_unlock_irqrestore(&gic_lock, flags);
  314. }
  315. static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
  316. {
  317. struct gic_all_vpes_chip_data *cd;
  318. unsigned int intr;
  319. intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
  320. cd = irq_data_get_irq_chip_data(d);
  321. write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
  322. if (cd->mask)
  323. write_gic_vl_smask(BIT(intr));
  324. }
  325. static struct irq_chip gic_all_vpes_local_irq_controller = {
  326. .name = "MIPS GIC Local",
  327. .irq_mask = gic_mask_local_irq_all_vpes,
  328. .irq_unmask = gic_unmask_local_irq_all_vpes,
  329. .irq_cpu_online = gic_all_vpes_irq_cpu_online,
  330. };
  331. static void __gic_irq_dispatch(void)
  332. {
  333. gic_handle_local_int(false);
  334. gic_handle_shared_int(false);
  335. }
  336. static void gic_irq_dispatch(struct irq_desc *desc)
  337. {
  338. gic_handle_local_int(true);
  339. gic_handle_shared_int(true);
  340. }
  341. static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
  342. irq_hw_number_t hw, unsigned int cpu)
  343. {
  344. int intr = GIC_HWIRQ_TO_SHARED(hw);
  345. struct irq_data *data;
  346. unsigned long flags;
  347. data = irq_get_irq_data(virq);
  348. spin_lock_irqsave(&gic_lock, flags);
  349. write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
  350. write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
  351. irq_data_update_effective_affinity(data, cpumask_of(cpu));
  352. spin_unlock_irqrestore(&gic_lock, flags);
  353. return 0;
  354. }
  355. static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
  356. const u32 *intspec, unsigned int intsize,
  357. irq_hw_number_t *out_hwirq,
  358. unsigned int *out_type)
  359. {
  360. if (intsize != 3)
  361. return -EINVAL;
  362. if (intspec[0] == GIC_SHARED)
  363. *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
  364. else if (intspec[0] == GIC_LOCAL)
  365. *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
  366. else
  367. return -EINVAL;
  368. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  369. return 0;
  370. }
  371. static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
  372. irq_hw_number_t hwirq)
  373. {
  374. struct gic_all_vpes_chip_data *cd;
  375. unsigned long flags;
  376. unsigned int intr;
  377. int err, cpu;
  378. u32 map;
  379. if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
  380. /* verify that shared irqs don't conflict with an IPI irq */
  381. if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
  382. return -EBUSY;
  383. err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
  384. &gic_level_irq_controller,
  385. NULL);
  386. if (err)
  387. return err;
  388. irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
  389. return gic_shared_irq_domain_map(d, virq, hwirq, 0);
  390. }
  391. intr = GIC_HWIRQ_TO_LOCAL(hwirq);
  392. map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
  393. switch (intr) {
  394. case GIC_LOCAL_INT_TIMER:
  395. /* CONFIG_MIPS_CMP workaround (see __gic_init) */
  396. map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
  397. fallthrough;
  398. case GIC_LOCAL_INT_PERFCTR:
  399. case GIC_LOCAL_INT_FDC:
  400. /*
  401. * HACK: These are all really percpu interrupts, but
  402. * the rest of the MIPS kernel code does not use the
  403. * percpu IRQ API for them.
  404. */
  405. cd = &gic_all_vpes_chip_data[intr];
  406. cd->map = map;
  407. err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
  408. &gic_all_vpes_local_irq_controller,
  409. cd);
  410. if (err)
  411. return err;
  412. irq_set_handler(virq, handle_percpu_irq);
  413. break;
  414. default:
  415. err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
  416. &gic_local_irq_controller,
  417. NULL);
  418. if (err)
  419. return err;
  420. irq_set_handler(virq, handle_percpu_devid_irq);
  421. irq_set_percpu_devid(virq);
  422. break;
  423. }
  424. if (!gic_local_irq_is_routable(intr))
  425. return -EPERM;
  426. spin_lock_irqsave(&gic_lock, flags);
  427. for_each_online_cpu(cpu) {
  428. write_gic_vl_other(mips_cm_vp_id(cpu));
  429. write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
  430. }
  431. spin_unlock_irqrestore(&gic_lock, flags);
  432. return 0;
  433. }
  434. static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
  435. unsigned int nr_irqs, void *arg)
  436. {
  437. struct irq_fwspec *fwspec = arg;
  438. irq_hw_number_t hwirq;
  439. if (fwspec->param[0] == GIC_SHARED)
  440. hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
  441. else
  442. hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
  443. return gic_irq_domain_map(d, virq, hwirq);
  444. }
  445. void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
  446. unsigned int nr_irqs)
  447. {
  448. }
  449. static const struct irq_domain_ops gic_irq_domain_ops = {
  450. .xlate = gic_irq_domain_xlate,
  451. .alloc = gic_irq_domain_alloc,
  452. .free = gic_irq_domain_free,
  453. .map = gic_irq_domain_map,
  454. };
  455. static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
  456. const u32 *intspec, unsigned int intsize,
  457. irq_hw_number_t *out_hwirq,
  458. unsigned int *out_type)
  459. {
  460. /*
  461. * There's nothing to translate here. hwirq is dynamically allocated and
  462. * the irq type is always edge triggered.
  463. * */
  464. *out_hwirq = 0;
  465. *out_type = IRQ_TYPE_EDGE_RISING;
  466. return 0;
  467. }
  468. static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
  469. unsigned int nr_irqs, void *arg)
  470. {
  471. struct cpumask *ipimask = arg;
  472. irq_hw_number_t hwirq, base_hwirq;
  473. int cpu, ret, i;
  474. base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
  475. if (base_hwirq == gic_shared_intrs)
  476. return -ENOMEM;
  477. /* check that we have enough space */
  478. for (i = base_hwirq; i < nr_irqs; i++) {
  479. if (!test_bit(i, ipi_available))
  480. return -EBUSY;
  481. }
  482. bitmap_clear(ipi_available, base_hwirq, nr_irqs);
  483. /* map the hwirq for each cpu consecutively */
  484. i = 0;
  485. for_each_cpu(cpu, ipimask) {
  486. hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
  487. ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
  488. &gic_edge_irq_controller,
  489. NULL);
  490. if (ret)
  491. goto error;
  492. ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
  493. &gic_edge_irq_controller,
  494. NULL);
  495. if (ret)
  496. goto error;
  497. ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
  498. if (ret)
  499. goto error;
  500. ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
  501. if (ret)
  502. goto error;
  503. i++;
  504. }
  505. return 0;
  506. error:
  507. bitmap_set(ipi_available, base_hwirq, nr_irqs);
  508. return ret;
  509. }
  510. static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
  511. unsigned int nr_irqs)
  512. {
  513. irq_hw_number_t base_hwirq;
  514. struct irq_data *data;
  515. data = irq_get_irq_data(virq);
  516. if (!data)
  517. return;
  518. base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
  519. bitmap_set(ipi_available, base_hwirq, nr_irqs);
  520. }
  521. static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
  522. enum irq_domain_bus_token bus_token)
  523. {
  524. bool is_ipi;
  525. switch (bus_token) {
  526. case DOMAIN_BUS_IPI:
  527. is_ipi = d->bus_token == bus_token;
  528. return (!node || to_of_node(d->fwnode) == node) && is_ipi;
  529. break;
  530. default:
  531. return 0;
  532. }
  533. }
  534. static const struct irq_domain_ops gic_ipi_domain_ops = {
  535. .xlate = gic_ipi_domain_xlate,
  536. .alloc = gic_ipi_domain_alloc,
  537. .free = gic_ipi_domain_free,
  538. .match = gic_ipi_domain_match,
  539. };
  540. static int gic_cpu_startup(unsigned int cpu)
  541. {
  542. /* Enable or disable EIC */
  543. change_gic_vl_ctl(GIC_VX_CTL_EIC,
  544. cpu_has_veic ? GIC_VX_CTL_EIC : 0);
  545. /* Clear all local IRQ masks (ie. disable all local interrupts) */
  546. write_gic_vl_rmask(~0);
  547. /* Invoke irq_cpu_online callbacks to enable desired interrupts */
  548. irq_cpu_online();
  549. return 0;
  550. }
  551. static int __init gic_of_init(struct device_node *node,
  552. struct device_node *parent)
  553. {
  554. unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
  555. unsigned long reserved;
  556. phys_addr_t gic_base;
  557. struct resource res;
  558. size_t gic_len;
  559. /* Find the first available CPU vector. */
  560. i = 0;
  561. reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
  562. while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
  563. i++, &cpu_vec))
  564. reserved |= BIT(cpu_vec);
  565. cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
  566. if (cpu_vec == hweight_long(ST0_IM)) {
  567. pr_err("No CPU vectors available\n");
  568. return -ENODEV;
  569. }
  570. if (of_address_to_resource(node, 0, &res)) {
  571. /*
  572. * Probe the CM for the GIC base address if not specified
  573. * in the device-tree.
  574. */
  575. if (mips_cm_present()) {
  576. gic_base = read_gcr_gic_base() &
  577. ~CM_GCR_GIC_BASE_GICEN;
  578. gic_len = 0x20000;
  579. pr_warn("Using inherited base address %pa\n",
  580. &gic_base);
  581. } else {
  582. pr_err("Failed to get memory range\n");
  583. return -ENODEV;
  584. }
  585. } else {
  586. gic_base = res.start;
  587. gic_len = resource_size(&res);
  588. }
  589. if (mips_cm_present()) {
  590. write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
  591. /* Ensure GIC region is enabled before trying to access it */
  592. __sync();
  593. }
  594. mips_gic_base = ioremap(gic_base, gic_len);
  595. gicconfig = read_gic_config();
  596. gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
  597. gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
  598. gic_shared_intrs = (gic_shared_intrs + 1) * 8;
  599. if (cpu_has_veic) {
  600. /* Always use vector 1 in EIC mode */
  601. gic_cpu_pin = 0;
  602. timer_cpu_pin = gic_cpu_pin;
  603. set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
  604. __gic_irq_dispatch);
  605. } else {
  606. gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
  607. irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
  608. gic_irq_dispatch);
  609. /*
  610. * With the CMP implementation of SMP (deprecated), other CPUs
  611. * are started by the bootloader and put into a timer based
  612. * waiting poll loop. We must not re-route those CPU's local
  613. * timer interrupts as the wait instruction will never finish,
  614. * so just handle whatever CPU interrupt it is routed to by
  615. * default.
  616. *
  617. * This workaround should be removed when CMP support is
  618. * dropped.
  619. */
  620. if (IS_ENABLED(CONFIG_MIPS_CMP) &&
  621. gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
  622. timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
  623. irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
  624. GIC_CPU_PIN_OFFSET +
  625. timer_cpu_pin,
  626. gic_irq_dispatch);
  627. } else {
  628. timer_cpu_pin = gic_cpu_pin;
  629. }
  630. }
  631. gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
  632. gic_shared_intrs, 0,
  633. &gic_irq_domain_ops, NULL);
  634. if (!gic_irq_domain) {
  635. pr_err("Failed to add IRQ domain");
  636. return -ENXIO;
  637. }
  638. gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
  639. IRQ_DOMAIN_FLAG_IPI_PER_CPU,
  640. GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
  641. node, &gic_ipi_domain_ops, NULL);
  642. if (!gic_ipi_domain) {
  643. pr_err("Failed to add IPI domain");
  644. return -ENXIO;
  645. }
  646. irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
  647. if (node &&
  648. !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
  649. bitmap_set(ipi_resrv, v[0], v[1]);
  650. } else {
  651. /*
  652. * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
  653. * meeting the requirements of arch/mips SMP.
  654. */
  655. num_ipis = 2 * num_possible_cpus();
  656. bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
  657. }
  658. bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
  659. board_bind_eic_interrupt = &gic_bind_eic_interrupt;
  660. /* Setup defaults */
  661. for (i = 0; i < gic_shared_intrs; i++) {
  662. change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
  663. change_gic_trig(i, GIC_TRIG_LEVEL);
  664. write_gic_rmask(i);
  665. }
  666. return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
  667. "irqchip/mips/gic:starting",
  668. gic_cpu_startup, NULL);
  669. }
  670. IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);