irq-ls-scfg-msi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Freescale SCFG MSI(-X) support
  4. *
  5. * Copyright (C) 2016 Freescale Semiconductor.
  6. *
  7. * Author: Minghuan Lian <Minghuan.Lian@nxp.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/msi.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqchip/chained_irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_pci.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/dma-iommu.h>
  21. #define MSI_IRQS_PER_MSIR 32
  22. #define MSI_MSIR_OFFSET 4
  23. #define MSI_LS1043V1_1_IRQS_PER_MSIR 8
  24. #define MSI_LS1043V1_1_MSIR_OFFSET 0x10
  25. struct ls_scfg_msi_cfg {
  26. u32 ibs_shift; /* Shift of interrupt bit select */
  27. u32 msir_irqs; /* The irq number per MSIR */
  28. u32 msir_base; /* The base address of MSIR */
  29. };
  30. struct ls_scfg_msir {
  31. struct ls_scfg_msi *msi_data;
  32. unsigned int index;
  33. unsigned int gic_irq;
  34. unsigned int bit_start;
  35. unsigned int bit_end;
  36. unsigned int srs; /* Shared interrupt register select */
  37. void __iomem *reg;
  38. };
  39. struct ls_scfg_msi {
  40. spinlock_t lock;
  41. struct platform_device *pdev;
  42. struct irq_domain *parent;
  43. struct irq_domain *msi_domain;
  44. void __iomem *regs;
  45. phys_addr_t msiir_addr;
  46. struct ls_scfg_msi_cfg *cfg;
  47. u32 msir_num;
  48. struct ls_scfg_msir *msir;
  49. u32 irqs_num;
  50. unsigned long *used;
  51. };
  52. static struct irq_chip ls_scfg_msi_irq_chip = {
  53. .name = "MSI",
  54. .irq_mask = pci_msi_mask_irq,
  55. .irq_unmask = pci_msi_unmask_irq,
  56. };
  57. static struct msi_domain_info ls_scfg_msi_domain_info = {
  58. .flags = (MSI_FLAG_USE_DEF_DOM_OPS |
  59. MSI_FLAG_USE_DEF_CHIP_OPS |
  60. MSI_FLAG_PCI_MSIX),
  61. .chip = &ls_scfg_msi_irq_chip,
  62. };
  63. static int msi_affinity_flag = 1;
  64. static int __init early_parse_ls_scfg_msi(char *p)
  65. {
  66. if (p && strncmp(p, "no-affinity", 11) == 0)
  67. msi_affinity_flag = 0;
  68. else
  69. msi_affinity_flag = 1;
  70. return 0;
  71. }
  72. early_param("lsmsi", early_parse_ls_scfg_msi);
  73. static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
  74. {
  75. struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
  76. msg->address_hi = upper_32_bits(msi_data->msiir_addr);
  77. msg->address_lo = lower_32_bits(msi_data->msiir_addr);
  78. msg->data = data->hwirq;
  79. if (msi_affinity_flag) {
  80. const struct cpumask *mask;
  81. mask = irq_data_get_effective_affinity_mask(data);
  82. msg->data |= cpumask_first(mask);
  83. }
  84. iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
  85. }
  86. static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
  87. const struct cpumask *mask, bool force)
  88. {
  89. struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
  90. u32 cpu;
  91. if (!msi_affinity_flag)
  92. return -EINVAL;
  93. if (!force)
  94. cpu = cpumask_any_and(mask, cpu_online_mask);
  95. else
  96. cpu = cpumask_first(mask);
  97. if (cpu >= msi_data->msir_num)
  98. return -EINVAL;
  99. if (msi_data->msir[cpu].gic_irq <= 0) {
  100. pr_warn("cannot bind the irq to cpu%d\n", cpu);
  101. return -EINVAL;
  102. }
  103. irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));
  104. return IRQ_SET_MASK_OK;
  105. }
  106. static struct irq_chip ls_scfg_msi_parent_chip = {
  107. .name = "SCFG",
  108. .irq_compose_msi_msg = ls_scfg_msi_compose_msg,
  109. .irq_set_affinity = ls_scfg_msi_set_affinity,
  110. };
  111. static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
  112. unsigned int virq,
  113. unsigned int nr_irqs,
  114. void *args)
  115. {
  116. msi_alloc_info_t *info = args;
  117. struct ls_scfg_msi *msi_data = domain->host_data;
  118. int pos, err = 0;
  119. WARN_ON(nr_irqs != 1);
  120. spin_lock(&msi_data->lock);
  121. pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
  122. if (pos < msi_data->irqs_num)
  123. __set_bit(pos, msi_data->used);
  124. else
  125. err = -ENOSPC;
  126. spin_unlock(&msi_data->lock);
  127. if (err)
  128. return err;
  129. err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr);
  130. if (err)
  131. return err;
  132. irq_domain_set_info(domain, virq, pos,
  133. &ls_scfg_msi_parent_chip, msi_data,
  134. handle_simple_irq, NULL, NULL);
  135. return 0;
  136. }
  137. static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
  138. unsigned int virq, unsigned int nr_irqs)
  139. {
  140. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  141. struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
  142. int pos;
  143. pos = d->hwirq;
  144. if (pos < 0 || pos >= msi_data->irqs_num) {
  145. pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
  146. return;
  147. }
  148. spin_lock(&msi_data->lock);
  149. __clear_bit(pos, msi_data->used);
  150. spin_unlock(&msi_data->lock);
  151. }
  152. static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
  153. .alloc = ls_scfg_msi_domain_irq_alloc,
  154. .free = ls_scfg_msi_domain_irq_free,
  155. };
  156. static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
  157. {
  158. struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
  159. struct ls_scfg_msi *msi_data = msir->msi_data;
  160. unsigned long val;
  161. int pos, size, virq, hwirq;
  162. chained_irq_enter(irq_desc_get_chip(desc), desc);
  163. val = ioread32be(msir->reg);
  164. pos = msir->bit_start;
  165. size = msir->bit_end + 1;
  166. for_each_set_bit_from(pos, &val, size) {
  167. hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
  168. msir->srs;
  169. virq = irq_find_mapping(msi_data->parent, hwirq);
  170. if (virq)
  171. generic_handle_irq(virq);
  172. }
  173. chained_irq_exit(irq_desc_get_chip(desc), desc);
  174. }
  175. static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
  176. {
  177. /* Initialize MSI domain parent */
  178. msi_data->parent = irq_domain_add_linear(NULL,
  179. msi_data->irqs_num,
  180. &ls_scfg_msi_domain_ops,
  181. msi_data);
  182. if (!msi_data->parent) {
  183. dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
  184. return -ENOMEM;
  185. }
  186. msi_data->msi_domain = pci_msi_create_irq_domain(
  187. of_node_to_fwnode(msi_data->pdev->dev.of_node),
  188. &ls_scfg_msi_domain_info,
  189. msi_data->parent);
  190. if (!msi_data->msi_domain) {
  191. dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
  192. irq_domain_remove(msi_data->parent);
  193. return -ENOMEM;
  194. }
  195. return 0;
  196. }
  197. static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
  198. {
  199. struct ls_scfg_msir *msir;
  200. int virq, i, hwirq;
  201. virq = platform_get_irq(msi_data->pdev, index);
  202. if (virq <= 0)
  203. return -ENODEV;
  204. msir = &msi_data->msir[index];
  205. msir->index = index;
  206. msir->msi_data = msi_data;
  207. msir->gic_irq = virq;
  208. msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
  209. if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
  210. msir->bit_start = 32 - ((msir->index + 1) *
  211. MSI_LS1043V1_1_IRQS_PER_MSIR);
  212. msir->bit_end = msir->bit_start +
  213. MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
  214. } else {
  215. msir->bit_start = 0;
  216. msir->bit_end = msi_data->cfg->msir_irqs - 1;
  217. }
  218. irq_set_chained_handler_and_data(msir->gic_irq,
  219. ls_scfg_msi_irq_handler,
  220. msir);
  221. if (msi_affinity_flag) {
  222. /* Associate MSIR interrupt to the cpu */
  223. irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
  224. msir->srs = 0; /* This value is determined by the CPU */
  225. } else
  226. msir->srs = index;
  227. /* Release the hwirqs corresponding to this MSIR */
  228. if (!msi_affinity_flag || msir->index == 0) {
  229. for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
  230. hwirq = i << msi_data->cfg->ibs_shift | msir->index;
  231. bitmap_clear(msi_data->used, hwirq, 1);
  232. }
  233. }
  234. return 0;
  235. }
  236. static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
  237. {
  238. struct ls_scfg_msi *msi_data = msir->msi_data;
  239. int i, hwirq;
  240. if (msir->gic_irq > 0)
  241. irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
  242. for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
  243. hwirq = i << msi_data->cfg->ibs_shift | msir->index;
  244. bitmap_set(msi_data->used, hwirq, 1);
  245. }
  246. return 0;
  247. }
  248. static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
  249. .ibs_shift = 3,
  250. .msir_irqs = MSI_IRQS_PER_MSIR,
  251. .msir_base = MSI_MSIR_OFFSET,
  252. };
  253. static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
  254. .ibs_shift = 2,
  255. .msir_irqs = MSI_IRQS_PER_MSIR,
  256. .msir_base = MSI_MSIR_OFFSET,
  257. };
  258. static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
  259. .ibs_shift = 2,
  260. .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
  261. .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
  262. };
  263. static const struct of_device_id ls_scfg_msi_id[] = {
  264. /* The following two misspelled compatibles are obsolete */
  265. { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
  266. { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
  267. { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
  268. { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
  269. { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
  270. { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
  271. { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
  272. {},
  273. };
  274. MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
  275. static int ls_scfg_msi_probe(struct platform_device *pdev)
  276. {
  277. const struct of_device_id *match;
  278. struct ls_scfg_msi *msi_data;
  279. struct resource *res;
  280. int i, ret;
  281. match = of_match_device(ls_scfg_msi_id, &pdev->dev);
  282. if (!match)
  283. return -ENODEV;
  284. msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
  285. if (!msi_data)
  286. return -ENOMEM;
  287. msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
  288. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  289. msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
  290. if (IS_ERR(msi_data->regs)) {
  291. dev_err(&pdev->dev, "failed to initialize 'regs'\n");
  292. return PTR_ERR(msi_data->regs);
  293. }
  294. msi_data->msiir_addr = res->start;
  295. msi_data->pdev = pdev;
  296. spin_lock_init(&msi_data->lock);
  297. msi_data->irqs_num = MSI_IRQS_PER_MSIR *
  298. (1 << msi_data->cfg->ibs_shift);
  299. msi_data->used = devm_kcalloc(&pdev->dev,
  300. BITS_TO_LONGS(msi_data->irqs_num),
  301. sizeof(*msi_data->used),
  302. GFP_KERNEL);
  303. if (!msi_data->used)
  304. return -ENOMEM;
  305. /*
  306. * Reserve all the hwirqs
  307. * The available hwirqs will be released in ls1_msi_setup_hwirq()
  308. */
  309. bitmap_set(msi_data->used, 0, msi_data->irqs_num);
  310. msi_data->msir_num = of_irq_count(pdev->dev.of_node);
  311. if (msi_affinity_flag) {
  312. u32 cpu_num;
  313. cpu_num = num_possible_cpus();
  314. if (msi_data->msir_num >= cpu_num)
  315. msi_data->msir_num = cpu_num;
  316. else
  317. msi_affinity_flag = 0;
  318. }
  319. msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
  320. sizeof(*msi_data->msir),
  321. GFP_KERNEL);
  322. if (!msi_data->msir)
  323. return -ENOMEM;
  324. for (i = 0; i < msi_data->msir_num; i++)
  325. ls_scfg_msi_setup_hwirq(msi_data, i);
  326. ret = ls_scfg_msi_domains_init(msi_data);
  327. if (ret)
  328. return ret;
  329. platform_set_drvdata(pdev, msi_data);
  330. return 0;
  331. }
  332. static int ls_scfg_msi_remove(struct platform_device *pdev)
  333. {
  334. struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
  335. int i;
  336. for (i = 0; i < msi_data->msir_num; i++)
  337. ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
  338. irq_domain_remove(msi_data->msi_domain);
  339. irq_domain_remove(msi_data->parent);
  340. platform_set_drvdata(pdev, NULL);
  341. return 0;
  342. }
  343. static struct platform_driver ls_scfg_msi_driver = {
  344. .driver = {
  345. .name = "ls-scfg-msi",
  346. .of_match_table = ls_scfg_msi_id,
  347. },
  348. .probe = ls_scfg_msi_probe,
  349. .remove = ls_scfg_msi_remove,
  350. };
  351. module_platform_driver(ls_scfg_msi_driver);
  352. MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>");
  353. MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver");
  354. MODULE_LICENSE("GPL v2");