irq-loongson-pch-msi.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
  4. * Loongson PCH MSI support
  5. */
  6. #define pr_fmt(fmt) "pch-msi: " fmt
  7. #include <linux/irqchip.h>
  8. #include <linux/msi.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_pci.h>
  13. #include <linux/pci.h>
  14. #include <linux/slab.h>
  15. struct pch_msi_data {
  16. struct mutex msi_map_lock;
  17. phys_addr_t doorbell;
  18. u32 irq_first; /* The vector number that MSIs starts */
  19. u32 num_irqs; /* The number of vectors for MSIs */
  20. unsigned long *msi_map;
  21. };
  22. static void pch_msi_mask_msi_irq(struct irq_data *d)
  23. {
  24. pci_msi_mask_irq(d);
  25. irq_chip_mask_parent(d);
  26. }
  27. static void pch_msi_unmask_msi_irq(struct irq_data *d)
  28. {
  29. irq_chip_unmask_parent(d);
  30. pci_msi_unmask_irq(d);
  31. }
  32. static struct irq_chip pch_msi_irq_chip = {
  33. .name = "PCH PCI MSI",
  34. .irq_mask = pch_msi_mask_msi_irq,
  35. .irq_unmask = pch_msi_unmask_msi_irq,
  36. .irq_ack = irq_chip_ack_parent,
  37. .irq_set_affinity = irq_chip_set_affinity_parent,
  38. };
  39. static int pch_msi_allocate_hwirq(struct pch_msi_data *priv, int num_req)
  40. {
  41. int first;
  42. mutex_lock(&priv->msi_map_lock);
  43. first = bitmap_find_free_region(priv->msi_map, priv->num_irqs,
  44. get_count_order(num_req));
  45. if (first < 0) {
  46. mutex_unlock(&priv->msi_map_lock);
  47. return -ENOSPC;
  48. }
  49. mutex_unlock(&priv->msi_map_lock);
  50. return priv->irq_first + first;
  51. }
  52. static void pch_msi_free_hwirq(struct pch_msi_data *priv,
  53. int hwirq, int num_req)
  54. {
  55. int first = hwirq - priv->irq_first;
  56. mutex_lock(&priv->msi_map_lock);
  57. bitmap_release_region(priv->msi_map, first, get_count_order(num_req));
  58. mutex_unlock(&priv->msi_map_lock);
  59. }
  60. static void pch_msi_compose_msi_msg(struct irq_data *data,
  61. struct msi_msg *msg)
  62. {
  63. struct pch_msi_data *priv = irq_data_get_irq_chip_data(data);
  64. msg->address_hi = upper_32_bits(priv->doorbell);
  65. msg->address_lo = lower_32_bits(priv->doorbell);
  66. msg->data = data->hwirq;
  67. }
  68. static struct msi_domain_info pch_msi_domain_info = {
  69. .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  70. MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
  71. .chip = &pch_msi_irq_chip,
  72. };
  73. static struct irq_chip middle_irq_chip = {
  74. .name = "PCH MSI",
  75. .irq_mask = irq_chip_mask_parent,
  76. .irq_unmask = irq_chip_unmask_parent,
  77. .irq_ack = irq_chip_ack_parent,
  78. .irq_set_affinity = irq_chip_set_affinity_parent,
  79. .irq_compose_msi_msg = pch_msi_compose_msi_msg,
  80. };
  81. static int pch_msi_parent_domain_alloc(struct irq_domain *domain,
  82. unsigned int virq, int hwirq)
  83. {
  84. struct irq_fwspec fwspec;
  85. fwspec.fwnode = domain->parent->fwnode;
  86. fwspec.param_count = 1;
  87. fwspec.param[0] = hwirq;
  88. return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  89. }
  90. static int pch_msi_middle_domain_alloc(struct irq_domain *domain,
  91. unsigned int virq,
  92. unsigned int nr_irqs, void *args)
  93. {
  94. struct pch_msi_data *priv = domain->host_data;
  95. int hwirq, err, i;
  96. hwirq = pch_msi_allocate_hwirq(priv, nr_irqs);
  97. if (hwirq < 0)
  98. return hwirq;
  99. for (i = 0; i < nr_irqs; i++) {
  100. err = pch_msi_parent_domain_alloc(domain, virq + i, hwirq + i);
  101. if (err)
  102. goto err_hwirq;
  103. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  104. &middle_irq_chip, priv);
  105. }
  106. return 0;
  107. err_hwirq:
  108. pch_msi_free_hwirq(priv, hwirq, nr_irqs);
  109. irq_domain_free_irqs_parent(domain, virq, i - 1);
  110. return err;
  111. }
  112. static void pch_msi_middle_domain_free(struct irq_domain *domain,
  113. unsigned int virq,
  114. unsigned int nr_irqs)
  115. {
  116. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  117. struct pch_msi_data *priv = irq_data_get_irq_chip_data(d);
  118. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  119. pch_msi_free_hwirq(priv, d->hwirq, nr_irqs);
  120. }
  121. static const struct irq_domain_ops pch_msi_middle_domain_ops = {
  122. .alloc = pch_msi_middle_domain_alloc,
  123. .free = pch_msi_middle_domain_free,
  124. };
  125. static int pch_msi_init_domains(struct pch_msi_data *priv,
  126. struct device_node *node,
  127. struct irq_domain *parent)
  128. {
  129. struct irq_domain *middle_domain, *msi_domain;
  130. middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
  131. priv->num_irqs,
  132. &pch_msi_middle_domain_ops,
  133. priv);
  134. if (!middle_domain) {
  135. pr_err("Failed to create the MSI middle domain\n");
  136. return -ENOMEM;
  137. }
  138. middle_domain->parent = parent;
  139. irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
  140. msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
  141. &pch_msi_domain_info,
  142. middle_domain);
  143. if (!msi_domain) {
  144. pr_err("Failed to create PCI MSI domain\n");
  145. irq_domain_remove(middle_domain);
  146. return -ENOMEM;
  147. }
  148. return 0;
  149. }
  150. static int pch_msi_init(struct device_node *node,
  151. struct device_node *parent)
  152. {
  153. struct pch_msi_data *priv;
  154. struct irq_domain *parent_domain;
  155. struct resource res;
  156. int ret;
  157. parent_domain = irq_find_host(parent);
  158. if (!parent_domain) {
  159. pr_err("Failed to find the parent domain\n");
  160. return -ENXIO;
  161. }
  162. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  163. if (!priv)
  164. return -ENOMEM;
  165. mutex_init(&priv->msi_map_lock);
  166. ret = of_address_to_resource(node, 0, &res);
  167. if (ret) {
  168. pr_err("Failed to allocate resource\n");
  169. goto err_priv;
  170. }
  171. priv->doorbell = res.start;
  172. if (of_property_read_u32(node, "loongson,msi-base-vec",
  173. &priv->irq_first)) {
  174. pr_err("Unable to parse MSI vec base\n");
  175. ret = -EINVAL;
  176. goto err_priv;
  177. }
  178. if (of_property_read_u32(node, "loongson,msi-num-vecs",
  179. &priv->num_irqs)) {
  180. pr_err("Unable to parse MSI vec number\n");
  181. ret = -EINVAL;
  182. goto err_priv;
  183. }
  184. priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
  185. if (!priv->msi_map) {
  186. ret = -ENOMEM;
  187. goto err_priv;
  188. }
  189. pr_debug("Registering %d MSIs, starting at %d\n",
  190. priv->num_irqs, priv->irq_first);
  191. ret = pch_msi_init_domains(priv, node, parent_domain);
  192. if (ret)
  193. goto err_map;
  194. return 0;
  195. err_map:
  196. kfree(priv->msi_map);
  197. err_priv:
  198. kfree(priv);
  199. return ret;
  200. }
  201. IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);