irq-jcore-aic.c 3.1 KB

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  1. /*
  2. * J-Core SoC AIC driver
  3. *
  4. * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/irq.h>
  11. #include <linux/io.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/cpu.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #define JCORE_AIC_MAX_HWIRQ 127
  19. #define JCORE_AIC1_MIN_HWIRQ 16
  20. #define JCORE_AIC2_MIN_HWIRQ 64
  21. #define JCORE_AIC1_INTPRI_REG 8
  22. static struct irq_chip jcore_aic;
  23. /*
  24. * The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do
  25. * not distinguish or use distinct irq number ranges for per-cpu event
  26. * interrupts (timer, IPI). Since information to determine whether a
  27. * particular irq number should be treated as per-cpu is not available
  28. * at mapping time, we use a wrapper handler function which chooses
  29. * the right handler at runtime based on whether IRQF_PERCPU was used
  30. * when requesting the irq.
  31. */
  32. static void handle_jcore_irq(struct irq_desc *desc)
  33. {
  34. if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
  35. handle_percpu_irq(desc);
  36. else
  37. handle_simple_irq(desc);
  38. }
  39. static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
  40. irq_hw_number_t hwirq)
  41. {
  42. struct irq_chip *aic = d->host_data;
  43. irq_set_chip_and_handler(irq, aic, handle_jcore_irq);
  44. return 0;
  45. }
  46. static const struct irq_domain_ops jcore_aic_irqdomain_ops = {
  47. .map = jcore_aic_irqdomain_map,
  48. .xlate = irq_domain_xlate_onecell,
  49. };
  50. static void noop(struct irq_data *data)
  51. {
  52. }
  53. static int __init aic_irq_of_init(struct device_node *node,
  54. struct device_node *parent)
  55. {
  56. unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
  57. unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;
  58. struct irq_domain *domain;
  59. pr_info("Initializing J-Core AIC\n");
  60. /* AIC1 needs priority initialization to receive interrupts. */
  61. if (of_device_is_compatible(node, "jcore,aic1")) {
  62. unsigned cpu;
  63. for_each_present_cpu(cpu) {
  64. void __iomem *base = of_iomap(node, cpu);
  65. if (!base) {
  66. pr_err("Unable to map AIC for cpu %u\n", cpu);
  67. return -ENOMEM;
  68. }
  69. __raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
  70. iounmap(base);
  71. }
  72. min_irq = JCORE_AIC1_MIN_HWIRQ;
  73. }
  74. /*
  75. * The irq chip framework requires either mask/unmask or enable/disable
  76. * function pointers to be provided, but the hardware does not have any
  77. * such mechanism; the only interrupt masking is at the cpu level and
  78. * it affects all interrupts. We provide dummy mask/unmask. The hardware
  79. * handles all interrupt control and clears pending status when the cpu
  80. * accepts the interrupt.
  81. */
  82. jcore_aic.irq_mask = noop;
  83. jcore_aic.irq_unmask = noop;
  84. jcore_aic.name = "AIC";
  85. domain = irq_domain_add_linear(node, dom_sz, &jcore_aic_irqdomain_ops,
  86. &jcore_aic);
  87. if (!domain)
  88. return -ENOMEM;
  89. irq_create_strict_mappings(domain, min_irq, min_irq, dom_sz - min_irq);
  90. return 0;
  91. }
  92. IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
  93. IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);