irq-ixp4xx.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * irqchip for the IXP4xx interrupt controller
  4. * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
  5. *
  6. * Based on arch/arm/mach-ixp4xx/common.c
  7. * Copyright 2002 (C) Intel Corporation
  8. * Copyright 2003-2004 (C) MontaVista, Software, Inc.
  9. * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/irq.h>
  14. #include <linux/io.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqchip/irq-ixp4xx.h>
  17. #include <linux/irqdomain.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/cpu.h>
  23. #include <asm/exception.h>
  24. #include <asm/mach/irq.h>
  25. #define IXP4XX_ICPR 0x00 /* Interrupt Status */
  26. #define IXP4XX_ICMR 0x04 /* Interrupt Enable */
  27. #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
  28. #define IXP4XX_ICIP 0x0C /* IRQ Status */
  29. #define IXP4XX_ICFP 0x10 /* FIQ Status */
  30. #define IXP4XX_ICHR 0x14 /* Interrupt Priority */
  31. #define IXP4XX_ICIH 0x18 /* IRQ Highest Pri Int */
  32. #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
  33. /* IXP43x and IXP46x-only */
  34. #define IXP4XX_ICPR2 0x20 /* Interrupt Status 2 */
  35. #define IXP4XX_ICMR2 0x24 /* Interrupt Enable 2 */
  36. #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
  37. #define IXP4XX_ICIP2 0x2C /* IRQ Status */
  38. #define IXP4XX_ICFP2 0x30 /* FIQ Status */
  39. #define IXP4XX_ICEEN 0x34 /* Error High Pri Enable */
  40. /**
  41. * struct ixp4xx_irq - state container for the Faraday IRQ controller
  42. * @irqbase: IRQ controller memory base in virtual memory
  43. * @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
  44. * @irqchip: irqchip for this instance
  45. * @domain: IRQ domain for this instance
  46. */
  47. struct ixp4xx_irq {
  48. void __iomem *irqbase;
  49. bool is_356;
  50. struct irq_chip irqchip;
  51. struct irq_domain *domain;
  52. };
  53. /* Local static state container */
  54. static struct ixp4xx_irq ixirq;
  55. /* GPIO Clocks */
  56. #define IXP4XX_GPIO_CLK_0 14
  57. #define IXP4XX_GPIO_CLK_1 15
  58. static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
  59. {
  60. /* All are level active high (asserted) here */
  61. if (type != IRQ_TYPE_LEVEL_HIGH)
  62. return -EINVAL;
  63. return 0;
  64. }
  65. static void ixp4xx_irq_mask(struct irq_data *d)
  66. {
  67. struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
  68. u32 val;
  69. if (ixi->is_356 && d->hwirq >= 32) {
  70. val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
  71. val &= ~BIT(d->hwirq - 32);
  72. __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
  73. } else {
  74. val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
  75. val &= ~BIT(d->hwirq);
  76. __raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
  77. }
  78. }
  79. /*
  80. * Level triggered interrupts on GPIO lines can only be cleared when the
  81. * interrupt condition disappears.
  82. */
  83. static void ixp4xx_irq_unmask(struct irq_data *d)
  84. {
  85. struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
  86. u32 val;
  87. if (ixi->is_356 && d->hwirq >= 32) {
  88. val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
  89. val |= BIT(d->hwirq - 32);
  90. __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
  91. } else {
  92. val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
  93. val |= BIT(d->hwirq);
  94. __raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
  95. }
  96. }
  97. asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
  98. {
  99. struct ixp4xx_irq *ixi = &ixirq;
  100. unsigned long status;
  101. int i;
  102. status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
  103. for_each_set_bit(i, &status, 32)
  104. handle_domain_irq(ixi->domain, i, regs);
  105. /*
  106. * IXP465/IXP435 has an upper IRQ status register
  107. */
  108. if (ixi->is_356) {
  109. status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
  110. for_each_set_bit(i, &status, 32)
  111. handle_domain_irq(ixi->domain, i + 32, regs);
  112. }
  113. }
  114. static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
  115. struct irq_fwspec *fwspec,
  116. unsigned long *hwirq,
  117. unsigned int *type)
  118. {
  119. /* We support standard DT translation */
  120. if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
  121. *hwirq = fwspec->param[0];
  122. *type = fwspec->param[1];
  123. return 0;
  124. }
  125. if (is_fwnode_irqchip(fwspec->fwnode)) {
  126. if (fwspec->param_count != 2)
  127. return -EINVAL;
  128. *hwirq = fwspec->param[0];
  129. *type = fwspec->param[1];
  130. WARN_ON(*type == IRQ_TYPE_NONE);
  131. return 0;
  132. }
  133. return -EINVAL;
  134. }
  135. static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
  136. unsigned int irq, unsigned int nr_irqs,
  137. void *data)
  138. {
  139. struct ixp4xx_irq *ixi = d->host_data;
  140. irq_hw_number_t hwirq;
  141. unsigned int type = IRQ_TYPE_NONE;
  142. struct irq_fwspec *fwspec = data;
  143. int ret;
  144. int i;
  145. ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
  146. if (ret)
  147. return ret;
  148. for (i = 0; i < nr_irqs; i++) {
  149. /*
  150. * TODO: after converting IXP4xx to only device tree, set
  151. * handle_bad_irq as default handler and assume all consumers
  152. * call .set_type() as this is provided in the second cell in
  153. * the device tree phandle.
  154. */
  155. irq_domain_set_info(d,
  156. irq + i,
  157. hwirq + i,
  158. &ixi->irqchip,
  159. ixi,
  160. handle_level_irq,
  161. NULL, NULL);
  162. irq_set_probe(irq + i);
  163. }
  164. return 0;
  165. }
  166. /*
  167. * This needs to be a hierarchical irqdomain to work well with the
  168. * GPIO irqchip (which is lower in the hierarchy)
  169. */
  170. static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
  171. .translate = ixp4xx_irq_domain_translate,
  172. .alloc = ixp4xx_irq_domain_alloc,
  173. .free = irq_domain_free_irqs_common,
  174. };
  175. /**
  176. * ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
  177. *
  178. * This function will go away when we transition to DT probing.
  179. */
  180. struct irq_domain *ixp4xx_get_irq_domain(void)
  181. {
  182. struct ixp4xx_irq *ixi = &ixirq;
  183. return ixi->domain;
  184. }
  185. EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);
  186. /*
  187. * This is the Linux IRQ to hwirq mapping table. This goes away when
  188. * we have DT support as all IRQ resources are defined in the device
  189. * tree. It will register all the IRQs that are not used by the hierarchical
  190. * GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
  191. * the GPIO driver using . This is a step-gap solution.
  192. */
  193. struct ixp4xx_irq_chunk {
  194. int irq;
  195. int hwirq;
  196. int nr_irqs;
  197. };
  198. static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
  199. {
  200. .irq = 16,
  201. .hwirq = 0,
  202. .nr_irqs = 6,
  203. },
  204. {
  205. .irq = 24,
  206. .hwirq = 8,
  207. .nr_irqs = 11,
  208. },
  209. {
  210. .irq = 46,
  211. .hwirq = 30,
  212. .nr_irqs = 2,
  213. },
  214. /* Only on the 436 variants */
  215. {
  216. .irq = 48,
  217. .hwirq = 32,
  218. .nr_irqs = 10,
  219. },
  220. };
  221. /**
  222. * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
  223. * @ixi: State container
  224. * @irqbase: Virtual memory base for the interrupt controller
  225. * @fwnode: Corresponding fwnode abstraction for this controller
  226. * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
  227. */
  228. static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
  229. void __iomem *irqbase,
  230. struct fwnode_handle *fwnode,
  231. bool is_356)
  232. {
  233. int nr_irqs;
  234. ixi->irqbase = irqbase;
  235. ixi->is_356 = is_356;
  236. /* Route all sources to IRQ instead of FIQ */
  237. __raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
  238. /* Disable all interrupts */
  239. __raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
  240. if (is_356) {
  241. /* Route upper 32 sources to IRQ instead of FIQ */
  242. __raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
  243. /* Disable upper 32 interrupts */
  244. __raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
  245. nr_irqs = 64;
  246. } else {
  247. nr_irqs = 32;
  248. }
  249. ixi->irqchip.name = "IXP4xx";
  250. ixi->irqchip.irq_mask = ixp4xx_irq_mask;
  251. ixi->irqchip.irq_unmask = ixp4xx_irq_unmask;
  252. ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
  253. ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
  254. &ixp4xx_irqdomain_ops,
  255. ixi);
  256. if (!ixi->domain) {
  257. pr_crit("IXP4XX: can not add primary irqdomain\n");
  258. return -ENODEV;
  259. }
  260. set_handle_irq(ixp4xx_handle_irq);
  261. return 0;
  262. }
  263. /**
  264. * ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
  265. * @irqbase: physical base for the irq controller
  266. * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
  267. */
  268. void __init ixp4xx_irq_init(resource_size_t irqbase,
  269. bool is_356)
  270. {
  271. struct ixp4xx_irq *ixi = &ixirq;
  272. void __iomem *base;
  273. struct fwnode_handle *fwnode;
  274. struct irq_fwspec fwspec;
  275. int nr_chunks;
  276. int ret;
  277. int i;
  278. base = ioremap(irqbase, 0x100);
  279. if (!base) {
  280. pr_crit("IXP4XX: could not ioremap interrupt controller\n");
  281. return;
  282. }
  283. fwnode = irq_domain_alloc_fwnode(&irqbase);
  284. if (!fwnode) {
  285. pr_crit("IXP4XX: no domain handle\n");
  286. return;
  287. }
  288. ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
  289. if (ret) {
  290. pr_crit("IXP4XX: failed to set up irqchip\n");
  291. irq_domain_free_fwnode(fwnode);
  292. }
  293. nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
  294. if (!is_356)
  295. nr_chunks--;
  296. /*
  297. * After adding OF support, this is no longer needed: irqs
  298. * will be allocated for the respective fwnodes.
  299. */
  300. for (i = 0; i < nr_chunks; i++) {
  301. const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];
  302. pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
  303. chunk->irq, chunk->irq + chunk->nr_irqs - 1,
  304. chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
  305. fwspec.fwnode = fwnode;
  306. fwspec.param[0] = chunk->hwirq;
  307. fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
  308. fwspec.param_count = 2;
  309. ret = __irq_domain_alloc_irqs(ixi->domain,
  310. chunk->irq,
  311. chunk->nr_irqs,
  312. NUMA_NO_NODE,
  313. &fwspec,
  314. false,
  315. NULL);
  316. if (ret < 0) {
  317. pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
  318. ret);
  319. return;
  320. }
  321. }
  322. }
  323. EXPORT_SYMBOL_GPL(ixp4xx_irq_init);
  324. #ifdef CONFIG_OF
  325. int __init ixp4xx_of_init_irq(struct device_node *np,
  326. struct device_node *parent)
  327. {
  328. struct ixp4xx_irq *ixi = &ixirq;
  329. void __iomem *base;
  330. struct fwnode_handle *fwnode;
  331. bool is_356;
  332. int ret;
  333. base = of_iomap(np, 0);
  334. if (!base) {
  335. pr_crit("IXP4XX: could not ioremap interrupt controller\n");
  336. return -ENODEV;
  337. }
  338. fwnode = of_node_to_fwnode(np);
  339. /* These chip variants have 64 interrupts */
  340. is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
  341. of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
  342. of_device_is_compatible(np, "intel,ixp46x-interrupt");
  343. ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
  344. if (ret)
  345. pr_crit("IXP4XX: failed to set up irqchip\n");
  346. return ret;
  347. }
  348. IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
  349. ixp4xx_of_init_irq);
  350. IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
  351. ixp4xx_of_init_irq);
  352. IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
  353. ixp4xx_of_init_irq);
  354. IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
  355. ixp4xx_of_init_irq);
  356. #endif