irq-ingenic.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  4. * Ingenic XBurst platform IRQ support
  5. */
  6. #include <linux/errno.h>
  7. #include <linux/init.h>
  8. #include <linux/types.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/ioport.h>
  11. #include <linux/irqchip.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/timex.h>
  15. #include <linux/slab.h>
  16. #include <linux/delay.h>
  17. #include <asm/io.h>
  18. struct ingenic_intc_data {
  19. void __iomem *base;
  20. struct irq_domain *domain;
  21. unsigned num_chips;
  22. };
  23. #define JZ_REG_INTC_STATUS 0x00
  24. #define JZ_REG_INTC_MASK 0x04
  25. #define JZ_REG_INTC_SET_MASK 0x08
  26. #define JZ_REG_INTC_CLEAR_MASK 0x0c
  27. #define JZ_REG_INTC_PENDING 0x10
  28. #define CHIP_SIZE 0x20
  29. static irqreturn_t intc_cascade(int irq, void *data)
  30. {
  31. struct ingenic_intc_data *intc = irq_get_handler_data(irq);
  32. struct irq_domain *domain = intc->domain;
  33. struct irq_chip_generic *gc;
  34. uint32_t pending;
  35. unsigned i;
  36. for (i = 0; i < intc->num_chips; i++) {
  37. gc = irq_get_domain_generic_chip(domain, i * 32);
  38. pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
  39. if (!pending)
  40. continue;
  41. while (pending) {
  42. int bit = __fls(pending);
  43. irq = irq_linear_revmap(domain, bit + (i * 32));
  44. generic_handle_irq(irq);
  45. pending &= ~BIT(bit);
  46. }
  47. }
  48. return IRQ_HANDLED;
  49. }
  50. static int __init ingenic_intc_of_init(struct device_node *node,
  51. unsigned num_chips)
  52. {
  53. struct ingenic_intc_data *intc;
  54. struct irq_chip_generic *gc;
  55. struct irq_chip_type *ct;
  56. struct irq_domain *domain;
  57. int parent_irq, err = 0;
  58. unsigned i;
  59. intc = kzalloc(sizeof(*intc), GFP_KERNEL);
  60. if (!intc) {
  61. err = -ENOMEM;
  62. goto out_err;
  63. }
  64. parent_irq = irq_of_parse_and_map(node, 0);
  65. if (!parent_irq) {
  66. err = -EINVAL;
  67. goto out_free;
  68. }
  69. err = irq_set_handler_data(parent_irq, intc);
  70. if (err)
  71. goto out_unmap_irq;
  72. intc->num_chips = num_chips;
  73. intc->base = of_iomap(node, 0);
  74. if (!intc->base) {
  75. err = -ENODEV;
  76. goto out_unmap_irq;
  77. }
  78. domain = irq_domain_add_linear(node, num_chips * 32,
  79. &irq_generic_chip_ops, NULL);
  80. if (!domain) {
  81. err = -ENOMEM;
  82. goto out_unmap_base;
  83. }
  84. intc->domain = domain;
  85. err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
  86. handle_level_irq, 0,
  87. IRQ_NOPROBE | IRQ_LEVEL, 0);
  88. if (err)
  89. goto out_domain_remove;
  90. for (i = 0; i < num_chips; i++) {
  91. gc = irq_get_domain_generic_chip(domain, i * 32);
  92. gc->wake_enabled = IRQ_MSK(32);
  93. gc->reg_base = intc->base + (i * CHIP_SIZE);
  94. ct = gc->chip_types;
  95. ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
  96. ct->regs.disable = JZ_REG_INTC_SET_MASK;
  97. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  98. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  99. ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
  100. ct->chip.irq_set_wake = irq_gc_set_wake;
  101. ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
  102. /* Mask all irqs */
  103. irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
  104. }
  105. if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
  106. "SoC intc cascade interrupt", NULL))
  107. pr_err("Failed to register SoC intc cascade interrupt\n");
  108. return 0;
  109. out_domain_remove:
  110. irq_domain_remove(domain);
  111. out_unmap_base:
  112. iounmap(intc->base);
  113. out_unmap_irq:
  114. irq_dispose_mapping(parent_irq);
  115. out_free:
  116. kfree(intc);
  117. out_err:
  118. return err;
  119. }
  120. static int __init intc_1chip_of_init(struct device_node *node,
  121. struct device_node *parent)
  122. {
  123. return ingenic_intc_of_init(node, 1);
  124. }
  125. IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
  126. IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
  127. static int __init intc_2chip_of_init(struct device_node *node,
  128. struct device_node *parent)
  129. {
  130. return ingenic_intc_of_init(node, 2);
  131. }
  132. IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
  133. IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
  134. IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
  135. IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);