irq-imgpdc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * IMG PowerDown Controller (PDC)
  4. *
  5. * Copyright 2010-2013 Imagination Technologies Ltd.
  6. *
  7. * Exposes the syswake and PDC peripheral wake interrupts to the system.
  8. *
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irqdomain.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/spinlock.h>
  18. /* PDC interrupt register numbers */
  19. #define PDC_IRQ_STATUS 0x310
  20. #define PDC_IRQ_ENABLE 0x314
  21. #define PDC_IRQ_CLEAR 0x318
  22. #define PDC_IRQ_ROUTE 0x31c
  23. #define PDC_SYS_WAKE_BASE 0x330
  24. #define PDC_SYS_WAKE_STRIDE 0x8
  25. #define PDC_SYS_WAKE_CONFIG_BASE 0x334
  26. #define PDC_SYS_WAKE_CONFIG_STRIDE 0x8
  27. /* PDC interrupt register field masks */
  28. #define PDC_IRQ_SYS3 0x08
  29. #define PDC_IRQ_SYS2 0x04
  30. #define PDC_IRQ_SYS1 0x02
  31. #define PDC_IRQ_SYS0 0x01
  32. #define PDC_IRQ_ROUTE_WU_EN_SYS3 0x08000000
  33. #define PDC_IRQ_ROUTE_WU_EN_SYS2 0x04000000
  34. #define PDC_IRQ_ROUTE_WU_EN_SYS1 0x02000000
  35. #define PDC_IRQ_ROUTE_WU_EN_SYS0 0x01000000
  36. #define PDC_IRQ_ROUTE_WU_EN_WD 0x00040000
  37. #define PDC_IRQ_ROUTE_WU_EN_IR 0x00020000
  38. #define PDC_IRQ_ROUTE_WU_EN_RTC 0x00010000
  39. #define PDC_IRQ_ROUTE_EXT_EN_SYS3 0x00000800
  40. #define PDC_IRQ_ROUTE_EXT_EN_SYS2 0x00000400
  41. #define PDC_IRQ_ROUTE_EXT_EN_SYS1 0x00000200
  42. #define PDC_IRQ_ROUTE_EXT_EN_SYS0 0x00000100
  43. #define PDC_IRQ_ROUTE_EXT_EN_WD 0x00000004
  44. #define PDC_IRQ_ROUTE_EXT_EN_IR 0x00000002
  45. #define PDC_IRQ_ROUTE_EXT_EN_RTC 0x00000001
  46. #define PDC_SYS_WAKE_RESET 0x00000010
  47. #define PDC_SYS_WAKE_INT_MODE 0x0000000e
  48. #define PDC_SYS_WAKE_INT_MODE_SHIFT 1
  49. #define PDC_SYS_WAKE_PIN_VAL 0x00000001
  50. /* PDC interrupt constants */
  51. #define PDC_SYS_WAKE_INT_LOW 0x0
  52. #define PDC_SYS_WAKE_INT_HIGH 0x1
  53. #define PDC_SYS_WAKE_INT_DOWN 0x2
  54. #define PDC_SYS_WAKE_INT_UP 0x3
  55. #define PDC_SYS_WAKE_INT_CHANGE 0x6
  56. #define PDC_SYS_WAKE_INT_NONE 0x4
  57. /**
  58. * struct pdc_intc_priv - private pdc interrupt data.
  59. * @nr_perips: Number of peripheral interrupt signals.
  60. * @nr_syswakes: Number of syswake signals.
  61. * @perip_irqs: List of peripheral IRQ numbers handled.
  62. * @syswake_irq: Shared PDC syswake IRQ number.
  63. * @domain: IRQ domain for PDC peripheral and syswake IRQs.
  64. * @pdc_base: Base of PDC registers.
  65. * @irq_route: Cached version of PDC_IRQ_ROUTE register.
  66. * @lock: Lock to protect the PDC syswake registers and the cached
  67. * values of those registers in this struct.
  68. */
  69. struct pdc_intc_priv {
  70. unsigned int nr_perips;
  71. unsigned int nr_syswakes;
  72. unsigned int *perip_irqs;
  73. unsigned int syswake_irq;
  74. struct irq_domain *domain;
  75. void __iomem *pdc_base;
  76. u32 irq_route;
  77. raw_spinlock_t lock;
  78. };
  79. static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs,
  80. unsigned int data)
  81. {
  82. iowrite32(data, priv->pdc_base + reg_offs);
  83. }
  84. static unsigned int pdc_read(struct pdc_intc_priv *priv,
  85. unsigned int reg_offs)
  86. {
  87. return ioread32(priv->pdc_base + reg_offs);
  88. }
  89. /* Generic IRQ callbacks */
  90. #define SYS0_HWIRQ 8
  91. static unsigned int hwirq_is_syswake(irq_hw_number_t hw)
  92. {
  93. return hw >= SYS0_HWIRQ;
  94. }
  95. static unsigned int hwirq_to_syswake(irq_hw_number_t hw)
  96. {
  97. return hw - SYS0_HWIRQ;
  98. }
  99. static irq_hw_number_t syswake_to_hwirq(unsigned int syswake)
  100. {
  101. return SYS0_HWIRQ + syswake;
  102. }
  103. static struct pdc_intc_priv *irqd_to_priv(struct irq_data *data)
  104. {
  105. return (struct pdc_intc_priv *)data->domain->host_data;
  106. }
  107. /*
  108. * perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains
  109. * wake bits, therefore we cannot use the generic irqchip mask callbacks as they
  110. * cache the mask.
  111. */
  112. static void perip_irq_mask(struct irq_data *data)
  113. {
  114. struct pdc_intc_priv *priv = irqd_to_priv(data);
  115. raw_spin_lock(&priv->lock);
  116. priv->irq_route &= ~data->mask;
  117. pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
  118. raw_spin_unlock(&priv->lock);
  119. }
  120. static void perip_irq_unmask(struct irq_data *data)
  121. {
  122. struct pdc_intc_priv *priv = irqd_to_priv(data);
  123. raw_spin_lock(&priv->lock);
  124. priv->irq_route |= data->mask;
  125. pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
  126. raw_spin_unlock(&priv->lock);
  127. }
  128. static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type)
  129. {
  130. struct pdc_intc_priv *priv = irqd_to_priv(data);
  131. unsigned int syswake = hwirq_to_syswake(data->hwirq);
  132. unsigned int irq_mode;
  133. unsigned int soc_sys_wake_regoff, soc_sys_wake;
  134. /* translate to syswake IRQ mode */
  135. switch (flow_type) {
  136. case IRQ_TYPE_EDGE_BOTH:
  137. irq_mode = PDC_SYS_WAKE_INT_CHANGE;
  138. break;
  139. case IRQ_TYPE_EDGE_RISING:
  140. irq_mode = PDC_SYS_WAKE_INT_UP;
  141. break;
  142. case IRQ_TYPE_EDGE_FALLING:
  143. irq_mode = PDC_SYS_WAKE_INT_DOWN;
  144. break;
  145. case IRQ_TYPE_LEVEL_HIGH:
  146. irq_mode = PDC_SYS_WAKE_INT_HIGH;
  147. break;
  148. case IRQ_TYPE_LEVEL_LOW:
  149. irq_mode = PDC_SYS_WAKE_INT_LOW;
  150. break;
  151. default:
  152. return -EINVAL;
  153. }
  154. raw_spin_lock(&priv->lock);
  155. /* set the IRQ mode */
  156. soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE;
  157. soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff);
  158. soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE;
  159. soc_sys_wake |= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT;
  160. pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
  161. /* and update the handler */
  162. irq_setup_alt_chip(data, flow_type);
  163. raw_spin_unlock(&priv->lock);
  164. return 0;
  165. }
  166. /* applies to both peripheral and syswake interrupts */
  167. static int pdc_irq_set_wake(struct irq_data *data, unsigned int on)
  168. {
  169. struct pdc_intc_priv *priv = irqd_to_priv(data);
  170. irq_hw_number_t hw = data->hwirq;
  171. unsigned int mask = (1 << 16) << hw;
  172. unsigned int dst_irq;
  173. raw_spin_lock(&priv->lock);
  174. if (on)
  175. priv->irq_route |= mask;
  176. else
  177. priv->irq_route &= ~mask;
  178. pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
  179. raw_spin_unlock(&priv->lock);
  180. /* control the destination IRQ wakeup too for standby mode */
  181. if (hwirq_is_syswake(hw))
  182. dst_irq = priv->syswake_irq;
  183. else
  184. dst_irq = priv->perip_irqs[hw];
  185. irq_set_irq_wake(dst_irq, on);
  186. return 0;
  187. }
  188. static void pdc_intc_perip_isr(struct irq_desc *desc)
  189. {
  190. unsigned int irq = irq_desc_get_irq(desc);
  191. struct pdc_intc_priv *priv;
  192. unsigned int i, irq_no;
  193. priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
  194. /* find the peripheral number */
  195. for (i = 0; i < priv->nr_perips; ++i)
  196. if (irq == priv->perip_irqs[i])
  197. goto found;
  198. /* should never get here */
  199. return;
  200. found:
  201. /* pass on the interrupt */
  202. irq_no = irq_linear_revmap(priv->domain, i);
  203. generic_handle_irq(irq_no);
  204. }
  205. static void pdc_intc_syswake_isr(struct irq_desc *desc)
  206. {
  207. struct pdc_intc_priv *priv;
  208. unsigned int syswake, irq_no;
  209. unsigned int status;
  210. priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
  211. status = pdc_read(priv, PDC_IRQ_STATUS) &
  212. pdc_read(priv, PDC_IRQ_ENABLE);
  213. status &= (1 << priv->nr_syswakes) - 1;
  214. for (syswake = 0; status; status >>= 1, ++syswake) {
  215. /* Has this sys_wake triggered? */
  216. if (!(status & 1))
  217. continue;
  218. irq_no = irq_linear_revmap(priv->domain,
  219. syswake_to_hwirq(syswake));
  220. generic_handle_irq(irq_no);
  221. }
  222. }
  223. static void pdc_intc_setup(struct pdc_intc_priv *priv)
  224. {
  225. int i;
  226. unsigned int soc_sys_wake_regoff;
  227. unsigned int soc_sys_wake;
  228. /*
  229. * Mask all syswake interrupts before routing, or we could receive an
  230. * interrupt before we're ready to handle it.
  231. */
  232. pdc_write(priv, PDC_IRQ_ENABLE, 0);
  233. /*
  234. * Enable routing of all syswakes
  235. * Disable all wake sources
  236. */
  237. priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) -
  238. PDC_IRQ_ROUTE_EXT_EN_SYS0);
  239. pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
  240. /* Initialise syswake IRQ */
  241. for (i = 0; i < priv->nr_syswakes; ++i) {
  242. /* set the IRQ mode to none */
  243. soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE;
  244. soc_sys_wake = PDC_SYS_WAKE_INT_NONE
  245. << PDC_SYS_WAKE_INT_MODE_SHIFT;
  246. pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
  247. }
  248. }
  249. static int pdc_intc_probe(struct platform_device *pdev)
  250. {
  251. struct pdc_intc_priv *priv;
  252. struct device_node *node = pdev->dev.of_node;
  253. struct resource *res_regs;
  254. struct irq_chip_generic *gc;
  255. unsigned int i;
  256. int irq, ret;
  257. u32 val;
  258. if (!node)
  259. return -ENOENT;
  260. /* Get registers */
  261. res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  262. if (res_regs == NULL) {
  263. dev_err(&pdev->dev, "cannot find registers resource\n");
  264. return -ENOENT;
  265. }
  266. /* Allocate driver data */
  267. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  268. if (!priv) {
  269. dev_err(&pdev->dev, "cannot allocate device data\n");
  270. return -ENOMEM;
  271. }
  272. raw_spin_lock_init(&priv->lock);
  273. platform_set_drvdata(pdev, priv);
  274. /* Ioremap the registers */
  275. priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
  276. resource_size(res_regs));
  277. if (!priv->pdc_base)
  278. return -EIO;
  279. /* Get number of peripherals */
  280. ret = of_property_read_u32(node, "num-perips", &val);
  281. if (ret) {
  282. dev_err(&pdev->dev, "No num-perips node property found\n");
  283. return -EINVAL;
  284. }
  285. if (val > SYS0_HWIRQ) {
  286. dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
  287. return -EINVAL;
  288. }
  289. priv->nr_perips = val;
  290. /* Get number of syswakes */
  291. ret = of_property_read_u32(node, "num-syswakes", &val);
  292. if (ret) {
  293. dev_err(&pdev->dev, "No num-syswakes node property found\n");
  294. return -EINVAL;
  295. }
  296. if (val > SYS0_HWIRQ) {
  297. dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
  298. return -EINVAL;
  299. }
  300. priv->nr_syswakes = val;
  301. /* Get peripheral IRQ numbers */
  302. priv->perip_irqs = devm_kcalloc(&pdev->dev, 4, priv->nr_perips,
  303. GFP_KERNEL);
  304. if (!priv->perip_irqs) {
  305. dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
  306. return -ENOMEM;
  307. }
  308. for (i = 0; i < priv->nr_perips; ++i) {
  309. irq = platform_get_irq(pdev, 1 + i);
  310. if (irq < 0)
  311. return irq;
  312. priv->perip_irqs[i] = irq;
  313. }
  314. /* check if too many were provided */
  315. if (platform_get_irq(pdev, 1 + i) >= 0) {
  316. dev_err(&pdev->dev, "surplus perip IRQs detected\n");
  317. return -EINVAL;
  318. }
  319. /* Get syswake IRQ number */
  320. irq = platform_get_irq(pdev, 0);
  321. if (irq < 0)
  322. return irq;
  323. priv->syswake_irq = irq;
  324. /* Set up an IRQ domain */
  325. priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
  326. priv);
  327. if (unlikely(!priv->domain)) {
  328. dev_err(&pdev->dev, "cannot add IRQ domain\n");
  329. return -ENOMEM;
  330. }
  331. /*
  332. * Set up 2 generic irq chips with 2 chip types.
  333. * The first one for peripheral irqs (only 1 chip type used)
  334. * The second one for syswake irqs (edge and level chip types)
  335. */
  336. ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
  337. handle_level_irq, 0, 0,
  338. IRQ_GC_INIT_NESTED_LOCK);
  339. if (ret)
  340. goto err_generic;
  341. /* peripheral interrupt chip */
  342. gc = irq_get_domain_generic_chip(priv->domain, 0);
  343. gc->unused = ~(BIT(priv->nr_perips) - 1);
  344. gc->reg_base = priv->pdc_base;
  345. /*
  346. * IRQ_ROUTE contains wake bits, so we can't use the generic versions as
  347. * they cache the mask
  348. */
  349. gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE;
  350. gc->chip_types[0].chip.irq_mask = perip_irq_mask;
  351. gc->chip_types[0].chip.irq_unmask = perip_irq_unmask;
  352. gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
  353. /* syswake interrupt chip */
  354. gc = irq_get_domain_generic_chip(priv->domain, 8);
  355. gc->unused = ~(BIT(priv->nr_syswakes) - 1);
  356. gc->reg_base = priv->pdc_base;
  357. /* edge interrupts */
  358. gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
  359. gc->chip_types[0].handler = handle_edge_irq;
  360. gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR;
  361. gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE;
  362. gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
  363. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  364. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  365. gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type;
  366. gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
  367. /* for standby we pass on to the shared syswake IRQ */
  368. gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
  369. /* level interrupts */
  370. gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK;
  371. gc->chip_types[1].handler = handle_level_irq;
  372. gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR;
  373. gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE;
  374. gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
  375. gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
  376. gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
  377. gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type;
  378. gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake;
  379. /* for standby we pass on to the shared syswake IRQ */
  380. gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
  381. /* Set up the hardware to enable interrupt routing */
  382. pdc_intc_setup(priv);
  383. /* Setup chained handlers for the peripheral IRQs */
  384. for (i = 0; i < priv->nr_perips; ++i) {
  385. irq = priv->perip_irqs[i];
  386. irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr,
  387. priv);
  388. }
  389. /* Setup chained handler for the syswake IRQ */
  390. irq_set_chained_handler_and_data(priv->syswake_irq,
  391. pdc_intc_syswake_isr, priv);
  392. dev_info(&pdev->dev,
  393. "PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
  394. priv->nr_perips,
  395. priv->nr_syswakes);
  396. return 0;
  397. err_generic:
  398. irq_domain_remove(priv->domain);
  399. return ret;
  400. }
  401. static int pdc_intc_remove(struct platform_device *pdev)
  402. {
  403. struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
  404. irq_domain_remove(priv->domain);
  405. return 0;
  406. }
  407. static const struct of_device_id pdc_intc_match[] = {
  408. { .compatible = "img,pdc-intc" },
  409. {}
  410. };
  411. static struct platform_driver pdc_intc_driver = {
  412. .driver = {
  413. .name = "pdc-intc",
  414. .of_match_table = pdc_intc_match,
  415. },
  416. .probe = pdc_intc_probe,
  417. .remove = pdc_intc_remove,
  418. };
  419. static int __init pdc_intc_init(void)
  420. {
  421. return platform_driver_register(&pdc_intc_driver);
  422. }
  423. core_initcall(pdc_intc_init);