irq-gic.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2002 ARM Limited, All Rights Reserved.
  4. *
  5. * Interrupt architecture for the GIC:
  6. *
  7. * o There is one Interrupt Distributor, which receives interrupts
  8. * from system devices and sends them to the Interrupt Controllers.
  9. *
  10. * o There is one CPU Interface per CPU, which sends interrupts sent
  11. * by the Distributor, and interrupts generated locally, to the
  12. * associated CPU. The base address of the CPU interface is usually
  13. * aliased so that the same address points to different chips depending
  14. * on the CPU it is accessed from.
  15. *
  16. * Note that IRQs 0-31 are special - they are local to each CPU.
  17. * As such, the enable set/clear, pending set/clear and active bit
  18. * registers are banked per-cpu for these sources.
  19. */
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/err.h>
  23. #include <linux/module.h>
  24. #include <linux/list.h>
  25. #include <linux/smp.h>
  26. #include <linux/cpu.h>
  27. #include <linux/cpu_pm.h>
  28. #include <linux/cpumask.h>
  29. #include <linux/io.h>
  30. #include <linux/of.h>
  31. #include <linux/of_address.h>
  32. #include <linux/of_irq.h>
  33. #include <linux/acpi.h>
  34. #include <linux/irqdomain.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/percpu.h>
  37. #include <linux/slab.h>
  38. #include <linux/irqchip.h>
  39. #include <linux/irqchip/chained_irq.h>
  40. #include <linux/irqchip/arm-gic.h>
  41. #include <asm/cputype.h>
  42. #include <asm/irq.h>
  43. #include <asm/exception.h>
  44. #include <asm/smp_plat.h>
  45. #include <asm/virt.h>
  46. #include "irq-gic-common.h"
  47. #ifdef CONFIG_ARM64
  48. #include <asm/cpufeature.h>
  49. static void gic_check_cpu_features(void)
  50. {
  51. WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  52. TAINT_CPU_OUT_OF_SPEC,
  53. "GICv3 system registers enabled, broken firmware!\n");
  54. }
  55. #else
  56. #define gic_check_cpu_features() do { } while(0)
  57. #endif
  58. union gic_base {
  59. void __iomem *common_base;
  60. void __percpu * __iomem *percpu_base;
  61. };
  62. struct gic_chip_data {
  63. struct irq_chip chip;
  64. union gic_base dist_base;
  65. union gic_base cpu_base;
  66. void __iomem *raw_dist_base;
  67. void __iomem *raw_cpu_base;
  68. u32 percpu_offset;
  69. #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  70. u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  71. u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  72. u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  73. u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  74. u32 __percpu *saved_ppi_enable;
  75. u32 __percpu *saved_ppi_active;
  76. u32 __percpu *saved_ppi_conf;
  77. #endif
  78. struct irq_domain *domain;
  79. unsigned int gic_irqs;
  80. };
  81. #ifdef CONFIG_BL_SWITCHER
  82. static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  83. #define gic_lock_irqsave(f) \
  84. raw_spin_lock_irqsave(&cpu_map_lock, (f))
  85. #define gic_unlock_irqrestore(f) \
  86. raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
  87. #define gic_lock() raw_spin_lock(&cpu_map_lock)
  88. #define gic_unlock() raw_spin_unlock(&cpu_map_lock)
  89. #else
  90. #define gic_lock_irqsave(f) do { (void)(f); } while(0)
  91. #define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
  92. #define gic_lock() do { } while(0)
  93. #define gic_unlock() do { } while(0)
  94. #endif
  95. static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
  96. /*
  97. * The GIC mapping of CPU interfaces does not necessarily match
  98. * the logical CPU numbering. Let's use a mapping as returned
  99. * by the GIC itself.
  100. */
  101. #define NR_GIC_CPU_IF 8
  102. static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
  103. static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
  104. static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
  105. static struct gic_kvm_info gic_v2_kvm_info;
  106. static DEFINE_PER_CPU(u32, sgi_intid);
  107. #ifdef CONFIG_GIC_NON_BANKED
  108. static DEFINE_STATIC_KEY_FALSE(frankengic_key);
  109. static void enable_frankengic(void)
  110. {
  111. static_branch_enable(&frankengic_key);
  112. }
  113. static inline void __iomem *__get_base(union gic_base *base)
  114. {
  115. if (static_branch_unlikely(&frankengic_key))
  116. return raw_cpu_read(*base->percpu_base);
  117. return base->common_base;
  118. }
  119. #define gic_data_dist_base(d) __get_base(&(d)->dist_base)
  120. #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
  121. #else
  122. #define gic_data_dist_base(d) ((d)->dist_base.common_base)
  123. #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
  124. #define enable_frankengic() do { } while(0)
  125. #endif
  126. static inline void __iomem *gic_dist_base(struct irq_data *d)
  127. {
  128. struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
  129. return gic_data_dist_base(gic_data);
  130. }
  131. static inline void __iomem *gic_cpu_base(struct irq_data *d)
  132. {
  133. struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
  134. return gic_data_cpu_base(gic_data);
  135. }
  136. static inline unsigned int gic_irq(struct irq_data *d)
  137. {
  138. return d->hwirq;
  139. }
  140. static inline bool cascading_gic_irq(struct irq_data *d)
  141. {
  142. void *data = irq_data_get_irq_handler_data(d);
  143. /*
  144. * If handler_data is set, this is a cascading interrupt, and
  145. * it cannot possibly be forwarded.
  146. */
  147. return data != NULL;
  148. }
  149. /*
  150. * Routines to acknowledge, disable and enable interrupts
  151. */
  152. static void gic_poke_irq(struct irq_data *d, u32 offset)
  153. {
  154. u32 mask = 1 << (gic_irq(d) % 32);
  155. writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
  156. }
  157. static int gic_peek_irq(struct irq_data *d, u32 offset)
  158. {
  159. u32 mask = 1 << (gic_irq(d) % 32);
  160. return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
  161. }
  162. static void gic_mask_irq(struct irq_data *d)
  163. {
  164. gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
  165. }
  166. static void gic_eoimode1_mask_irq(struct irq_data *d)
  167. {
  168. gic_mask_irq(d);
  169. /*
  170. * When masking a forwarded interrupt, make sure it is
  171. * deactivated as well.
  172. *
  173. * This ensures that an interrupt that is getting
  174. * disabled/masked will not get "stuck", because there is
  175. * noone to deactivate it (guest is being terminated).
  176. */
  177. if (irqd_is_forwarded_to_vcpu(d))
  178. gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
  179. }
  180. static void gic_unmask_irq(struct irq_data *d)
  181. {
  182. gic_poke_irq(d, GIC_DIST_ENABLE_SET);
  183. }
  184. static void gic_eoi_irq(struct irq_data *d)
  185. {
  186. u32 hwirq = gic_irq(d);
  187. if (hwirq < 16)
  188. hwirq = this_cpu_read(sgi_intid);
  189. writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
  190. }
  191. static void gic_eoimode1_eoi_irq(struct irq_data *d)
  192. {
  193. u32 hwirq = gic_irq(d);
  194. /* Do not deactivate an IRQ forwarded to a vcpu. */
  195. if (irqd_is_forwarded_to_vcpu(d))
  196. return;
  197. if (hwirq < 16)
  198. hwirq = this_cpu_read(sgi_intid);
  199. writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
  200. }
  201. static int gic_irq_set_irqchip_state(struct irq_data *d,
  202. enum irqchip_irq_state which, bool val)
  203. {
  204. u32 reg;
  205. switch (which) {
  206. case IRQCHIP_STATE_PENDING:
  207. reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
  208. break;
  209. case IRQCHIP_STATE_ACTIVE:
  210. reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
  211. break;
  212. case IRQCHIP_STATE_MASKED:
  213. reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
  214. break;
  215. default:
  216. return -EINVAL;
  217. }
  218. gic_poke_irq(d, reg);
  219. return 0;
  220. }
  221. static int gic_irq_get_irqchip_state(struct irq_data *d,
  222. enum irqchip_irq_state which, bool *val)
  223. {
  224. switch (which) {
  225. case IRQCHIP_STATE_PENDING:
  226. *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
  227. break;
  228. case IRQCHIP_STATE_ACTIVE:
  229. *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
  230. break;
  231. case IRQCHIP_STATE_MASKED:
  232. *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
  233. break;
  234. default:
  235. return -EINVAL;
  236. }
  237. return 0;
  238. }
  239. static int gic_set_type(struct irq_data *d, unsigned int type)
  240. {
  241. void __iomem *base = gic_dist_base(d);
  242. unsigned int gicirq = gic_irq(d);
  243. int ret;
  244. /* Interrupt configuration for SGIs can't be changed */
  245. if (gicirq < 16)
  246. return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
  247. /* SPIs have restrictions on the supported types */
  248. if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
  249. type != IRQ_TYPE_EDGE_RISING)
  250. return -EINVAL;
  251. ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
  252. if (ret && gicirq < 32) {
  253. /* Misconfigured PPIs are usually not fatal */
  254. pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
  255. ret = 0;
  256. }
  257. return ret;
  258. }
  259. static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
  260. {
  261. /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
  262. if (cascading_gic_irq(d) || gic_irq(d) < 16)
  263. return -EINVAL;
  264. if (vcpu)
  265. irqd_set_forwarded_to_vcpu(d);
  266. else
  267. irqd_clr_forwarded_to_vcpu(d);
  268. return 0;
  269. }
  270. static int gic_retrigger(struct irq_data *data)
  271. {
  272. return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
  273. }
  274. static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
  275. {
  276. u32 irqstat, irqnr;
  277. struct gic_chip_data *gic = &gic_data[0];
  278. void __iomem *cpu_base = gic_data_cpu_base(gic);
  279. do {
  280. irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
  281. irqnr = irqstat & GICC_IAR_INT_ID_MASK;
  282. if (unlikely(irqnr >= 1020))
  283. break;
  284. if (static_branch_likely(&supports_deactivate_key))
  285. writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
  286. isb();
  287. /*
  288. * Ensure any shared data written by the CPU sending the IPI
  289. * is read after we've read the ACK register on the GIC.
  290. *
  291. * Pairs with the write barrier in gic_ipi_send_mask
  292. */
  293. if (irqnr <= 15) {
  294. smp_rmb();
  295. /*
  296. * The GIC encodes the source CPU in GICC_IAR,
  297. * leading to the deactivation to fail if not
  298. * written back as is to GICC_EOI. Stash the INTID
  299. * away for gic_eoi_irq() to write back. This only
  300. * works because we don't nest SGIs...
  301. */
  302. this_cpu_write(sgi_intid, irqstat);
  303. }
  304. handle_domain_irq(gic->domain, irqnr, regs);
  305. } while (1);
  306. }
  307. static void gic_handle_cascade_irq(struct irq_desc *desc)
  308. {
  309. struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
  310. struct irq_chip *chip = irq_desc_get_chip(desc);
  311. unsigned int cascade_irq, gic_irq;
  312. unsigned long status;
  313. chained_irq_enter(chip, desc);
  314. status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
  315. gic_irq = (status & GICC_IAR_INT_ID_MASK);
  316. if (gic_irq == GICC_INT_SPURIOUS)
  317. goto out;
  318. cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
  319. if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
  320. handle_bad_irq(desc);
  321. } else {
  322. isb();
  323. generic_handle_irq(cascade_irq);
  324. }
  325. out:
  326. chained_irq_exit(chip, desc);
  327. }
  328. static const struct irq_chip gic_chip = {
  329. .irq_mask = gic_mask_irq,
  330. .irq_unmask = gic_unmask_irq,
  331. .irq_eoi = gic_eoi_irq,
  332. .irq_set_type = gic_set_type,
  333. .irq_retrigger = gic_retrigger,
  334. .irq_get_irqchip_state = gic_irq_get_irqchip_state,
  335. .irq_set_irqchip_state = gic_irq_set_irqchip_state,
  336. .flags = IRQCHIP_SET_TYPE_MASKED |
  337. IRQCHIP_SKIP_SET_WAKE |
  338. IRQCHIP_MASK_ON_SUSPEND,
  339. };
  340. void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
  341. {
  342. BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
  343. irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
  344. &gic_data[gic_nr]);
  345. }
  346. static u8 gic_get_cpumask(struct gic_chip_data *gic)
  347. {
  348. void __iomem *base = gic_data_dist_base(gic);
  349. u32 mask, i;
  350. for (i = mask = 0; i < 32; i += 4) {
  351. mask = readl_relaxed(base + GIC_DIST_TARGET + i);
  352. mask |= mask >> 16;
  353. mask |= mask >> 8;
  354. if (mask)
  355. break;
  356. }
  357. if (!mask && num_possible_cpus() > 1)
  358. pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
  359. return mask;
  360. }
  361. static bool gic_check_gicv2(void __iomem *base)
  362. {
  363. u32 val = readl_relaxed(base + GIC_CPU_IDENT);
  364. return (val & 0xff0fff) == 0x02043B;
  365. }
  366. static void gic_cpu_if_up(struct gic_chip_data *gic)
  367. {
  368. void __iomem *cpu_base = gic_data_cpu_base(gic);
  369. u32 bypass = 0;
  370. u32 mode = 0;
  371. int i;
  372. if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
  373. mode = GIC_CPU_CTRL_EOImodeNS;
  374. if (gic_check_gicv2(cpu_base))
  375. for (i = 0; i < 4; i++)
  376. writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
  377. /*
  378. * Preserve bypass disable bits to be written back later
  379. */
  380. bypass = readl(cpu_base + GIC_CPU_CTRL);
  381. bypass &= GICC_DIS_BYPASS_MASK;
  382. writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
  383. }
  384. static void gic_dist_init(struct gic_chip_data *gic)
  385. {
  386. unsigned int i;
  387. u32 cpumask;
  388. unsigned int gic_irqs = gic->gic_irqs;
  389. void __iomem *base = gic_data_dist_base(gic);
  390. writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
  391. /*
  392. * Set all global interrupts to this CPU only.
  393. */
  394. cpumask = gic_get_cpumask(gic);
  395. cpumask |= cpumask << 8;
  396. cpumask |= cpumask << 16;
  397. for (i = 32; i < gic_irqs; i += 4)
  398. writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
  399. gic_dist_config(base, gic_irqs, NULL);
  400. writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
  401. }
  402. static int gic_cpu_init(struct gic_chip_data *gic)
  403. {
  404. void __iomem *dist_base = gic_data_dist_base(gic);
  405. void __iomem *base = gic_data_cpu_base(gic);
  406. unsigned int cpu_mask, cpu = smp_processor_id();
  407. int i;
  408. /*
  409. * Setting up the CPU map is only relevant for the primary GIC
  410. * because any nested/secondary GICs do not directly interface
  411. * with the CPU(s).
  412. */
  413. if (gic == &gic_data[0]) {
  414. /*
  415. * Get what the GIC says our CPU mask is.
  416. */
  417. if (WARN_ON(cpu >= NR_GIC_CPU_IF))
  418. return -EINVAL;
  419. gic_check_cpu_features();
  420. cpu_mask = gic_get_cpumask(gic);
  421. gic_cpu_map[cpu] = cpu_mask;
  422. /*
  423. * Clear our mask from the other map entries in case they're
  424. * still undefined.
  425. */
  426. for (i = 0; i < NR_GIC_CPU_IF; i++)
  427. if (i != cpu)
  428. gic_cpu_map[i] &= ~cpu_mask;
  429. }
  430. gic_cpu_config(dist_base, 32, NULL);
  431. writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
  432. gic_cpu_if_up(gic);
  433. return 0;
  434. }
  435. int gic_cpu_if_down(unsigned int gic_nr)
  436. {
  437. void __iomem *cpu_base;
  438. u32 val = 0;
  439. if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
  440. return -EINVAL;
  441. cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
  442. val = readl(cpu_base + GIC_CPU_CTRL);
  443. val &= ~GICC_ENABLE;
  444. writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
  445. return 0;
  446. }
  447. #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  448. /*
  449. * Saves the GIC distributor registers during suspend or idle. Must be called
  450. * with interrupts disabled but before powering down the GIC. After calling
  451. * this function, no interrupts will be delivered by the GIC, and another
  452. * platform-specific wakeup source must be enabled.
  453. */
  454. void gic_dist_save(struct gic_chip_data *gic)
  455. {
  456. unsigned int gic_irqs;
  457. void __iomem *dist_base;
  458. int i;
  459. if (WARN_ON(!gic))
  460. return;
  461. gic_irqs = gic->gic_irqs;
  462. dist_base = gic_data_dist_base(gic);
  463. if (!dist_base)
  464. return;
  465. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
  466. gic->saved_spi_conf[i] =
  467. readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
  468. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
  469. gic->saved_spi_target[i] =
  470. readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
  471. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
  472. gic->saved_spi_enable[i] =
  473. readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
  474. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
  475. gic->saved_spi_active[i] =
  476. readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
  477. }
  478. /*
  479. * Restores the GIC distributor registers during resume or when coming out of
  480. * idle. Must be called before enabling interrupts. If a level interrupt
  481. * that occurred while the GIC was suspended is still present, it will be
  482. * handled normally, but any edge interrupts that occurred will not be seen by
  483. * the GIC and need to be handled by the platform-specific wakeup source.
  484. */
  485. void gic_dist_restore(struct gic_chip_data *gic)
  486. {
  487. unsigned int gic_irqs;
  488. unsigned int i;
  489. void __iomem *dist_base;
  490. if (WARN_ON(!gic))
  491. return;
  492. gic_irqs = gic->gic_irqs;
  493. dist_base = gic_data_dist_base(gic);
  494. if (!dist_base)
  495. return;
  496. writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
  497. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
  498. writel_relaxed(gic->saved_spi_conf[i],
  499. dist_base + GIC_DIST_CONFIG + i * 4);
  500. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
  501. writel_relaxed(GICD_INT_DEF_PRI_X4,
  502. dist_base + GIC_DIST_PRI + i * 4);
  503. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
  504. writel_relaxed(gic->saved_spi_target[i],
  505. dist_base + GIC_DIST_TARGET + i * 4);
  506. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
  507. writel_relaxed(GICD_INT_EN_CLR_X32,
  508. dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
  509. writel_relaxed(gic->saved_spi_enable[i],
  510. dist_base + GIC_DIST_ENABLE_SET + i * 4);
  511. }
  512. for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
  513. writel_relaxed(GICD_INT_EN_CLR_X32,
  514. dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
  515. writel_relaxed(gic->saved_spi_active[i],
  516. dist_base + GIC_DIST_ACTIVE_SET + i * 4);
  517. }
  518. writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
  519. }
  520. void gic_cpu_save(struct gic_chip_data *gic)
  521. {
  522. int i;
  523. u32 *ptr;
  524. void __iomem *dist_base;
  525. void __iomem *cpu_base;
  526. if (WARN_ON(!gic))
  527. return;
  528. dist_base = gic_data_dist_base(gic);
  529. cpu_base = gic_data_cpu_base(gic);
  530. if (!dist_base || !cpu_base)
  531. return;
  532. ptr = raw_cpu_ptr(gic->saved_ppi_enable);
  533. for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
  534. ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
  535. ptr = raw_cpu_ptr(gic->saved_ppi_active);
  536. for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
  537. ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
  538. ptr = raw_cpu_ptr(gic->saved_ppi_conf);
  539. for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
  540. ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
  541. }
  542. void gic_cpu_restore(struct gic_chip_data *gic)
  543. {
  544. int i;
  545. u32 *ptr;
  546. void __iomem *dist_base;
  547. void __iomem *cpu_base;
  548. if (WARN_ON(!gic))
  549. return;
  550. dist_base = gic_data_dist_base(gic);
  551. cpu_base = gic_data_cpu_base(gic);
  552. if (!dist_base || !cpu_base)
  553. return;
  554. ptr = raw_cpu_ptr(gic->saved_ppi_enable);
  555. for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
  556. writel_relaxed(GICD_INT_EN_CLR_X32,
  557. dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
  558. writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
  559. }
  560. ptr = raw_cpu_ptr(gic->saved_ppi_active);
  561. for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
  562. writel_relaxed(GICD_INT_EN_CLR_X32,
  563. dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
  564. writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
  565. }
  566. ptr = raw_cpu_ptr(gic->saved_ppi_conf);
  567. for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
  568. writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
  569. for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
  570. writel_relaxed(GICD_INT_DEF_PRI_X4,
  571. dist_base + GIC_DIST_PRI + i * 4);
  572. writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
  573. gic_cpu_if_up(gic);
  574. }
  575. static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
  576. {
  577. int i;
  578. for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
  579. switch (cmd) {
  580. case CPU_PM_ENTER:
  581. gic_cpu_save(&gic_data[i]);
  582. break;
  583. case CPU_PM_ENTER_FAILED:
  584. case CPU_PM_EXIT:
  585. gic_cpu_restore(&gic_data[i]);
  586. break;
  587. case CPU_CLUSTER_PM_ENTER:
  588. gic_dist_save(&gic_data[i]);
  589. break;
  590. case CPU_CLUSTER_PM_ENTER_FAILED:
  591. case CPU_CLUSTER_PM_EXIT:
  592. gic_dist_restore(&gic_data[i]);
  593. break;
  594. }
  595. }
  596. return NOTIFY_OK;
  597. }
  598. static struct notifier_block gic_notifier_block = {
  599. .notifier_call = gic_notifier,
  600. };
  601. static int gic_pm_init(struct gic_chip_data *gic)
  602. {
  603. gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
  604. sizeof(u32));
  605. if (WARN_ON(!gic->saved_ppi_enable))
  606. return -ENOMEM;
  607. gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
  608. sizeof(u32));
  609. if (WARN_ON(!gic->saved_ppi_active))
  610. goto free_ppi_enable;
  611. gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
  612. sizeof(u32));
  613. if (WARN_ON(!gic->saved_ppi_conf))
  614. goto free_ppi_active;
  615. if (gic == &gic_data[0])
  616. cpu_pm_register_notifier(&gic_notifier_block);
  617. return 0;
  618. free_ppi_active:
  619. free_percpu(gic->saved_ppi_active);
  620. free_ppi_enable:
  621. free_percpu(gic->saved_ppi_enable);
  622. return -ENOMEM;
  623. }
  624. #else
  625. static int gic_pm_init(struct gic_chip_data *gic)
  626. {
  627. return 0;
  628. }
  629. #endif
  630. #ifdef CONFIG_SMP
  631. static void rmw_writeb(u8 bval, void __iomem *addr)
  632. {
  633. static DEFINE_RAW_SPINLOCK(rmw_lock);
  634. unsigned long offset = (unsigned long)addr & 3UL;
  635. unsigned long shift = offset * 8;
  636. unsigned long flags;
  637. u32 val;
  638. raw_spin_lock_irqsave(&rmw_lock, flags);
  639. addr -= offset;
  640. val = readl_relaxed(addr);
  641. val &= ~GENMASK(shift + 7, shift);
  642. val |= bval << shift;
  643. writel_relaxed(val, addr);
  644. raw_spin_unlock_irqrestore(&rmw_lock, flags);
  645. }
  646. static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
  647. bool force)
  648. {
  649. void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
  650. unsigned int cpu;
  651. if (!force)
  652. cpu = cpumask_any_and(mask_val, cpu_online_mask);
  653. else
  654. cpu = cpumask_first(mask_val);
  655. if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
  656. return -EINVAL;
  657. if (static_branch_unlikely(&needs_rmw_access))
  658. rmw_writeb(gic_cpu_map[cpu], reg);
  659. else
  660. writeb_relaxed(gic_cpu_map[cpu], reg);
  661. irq_data_update_effective_affinity(d, cpumask_of(cpu));
  662. return IRQ_SET_MASK_OK_DONE;
  663. }
  664. static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
  665. {
  666. int cpu;
  667. unsigned long flags, map = 0;
  668. if (unlikely(nr_cpu_ids == 1)) {
  669. /* Only one CPU? let's do a self-IPI... */
  670. writel_relaxed(2 << 24 | d->hwirq,
  671. gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
  672. return;
  673. }
  674. gic_lock_irqsave(flags);
  675. /* Convert our logical CPU mask into a physical one. */
  676. for_each_cpu(cpu, mask)
  677. map |= gic_cpu_map[cpu];
  678. /*
  679. * Ensure that stores to Normal memory are visible to the
  680. * other CPUs before they observe us issuing the IPI.
  681. */
  682. dmb(ishst);
  683. /* this always happens on GIC0 */
  684. writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
  685. gic_unlock_irqrestore(flags);
  686. }
  687. static int gic_starting_cpu(unsigned int cpu)
  688. {
  689. gic_cpu_init(&gic_data[0]);
  690. return 0;
  691. }
  692. static __init void gic_smp_init(void)
  693. {
  694. struct irq_fwspec sgi_fwspec = {
  695. .fwnode = gic_data[0].domain->fwnode,
  696. .param_count = 1,
  697. };
  698. int base_sgi;
  699. cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
  700. "irqchip/arm/gic:starting",
  701. gic_starting_cpu, NULL);
  702. base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
  703. NUMA_NO_NODE, &sgi_fwspec,
  704. false, NULL);
  705. if (WARN_ON(base_sgi <= 0))
  706. return;
  707. set_smp_ipi_range(base_sgi, 8);
  708. }
  709. #else
  710. #define gic_smp_init() do { } while(0)
  711. #define gic_set_affinity NULL
  712. #define gic_ipi_send_mask NULL
  713. #endif
  714. #ifdef CONFIG_BL_SWITCHER
  715. /*
  716. * gic_send_sgi - send a SGI directly to given CPU interface number
  717. *
  718. * cpu_id: the ID for the destination CPU interface
  719. * irq: the IPI number to send a SGI for
  720. */
  721. void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
  722. {
  723. BUG_ON(cpu_id >= NR_GIC_CPU_IF);
  724. cpu_id = 1 << cpu_id;
  725. /* this always happens on GIC0 */
  726. writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
  727. }
  728. /*
  729. * gic_get_cpu_id - get the CPU interface ID for the specified CPU
  730. *
  731. * @cpu: the logical CPU number to get the GIC ID for.
  732. *
  733. * Return the CPU interface ID for the given logical CPU number,
  734. * or -1 if the CPU number is too large or the interface ID is
  735. * unknown (more than one bit set).
  736. */
  737. int gic_get_cpu_id(unsigned int cpu)
  738. {
  739. unsigned int cpu_bit;
  740. if (cpu >= NR_GIC_CPU_IF)
  741. return -1;
  742. cpu_bit = gic_cpu_map[cpu];
  743. if (cpu_bit & (cpu_bit - 1))
  744. return -1;
  745. return __ffs(cpu_bit);
  746. }
  747. /*
  748. * gic_migrate_target - migrate IRQs to another CPU interface
  749. *
  750. * @new_cpu_id: the CPU target ID to migrate IRQs to
  751. *
  752. * Migrate all peripheral interrupts with a target matching the current CPU
  753. * to the interface corresponding to @new_cpu_id. The CPU interface mapping
  754. * is also updated. Targets to other CPU interfaces are unchanged.
  755. * This must be called with IRQs locally disabled.
  756. */
  757. void gic_migrate_target(unsigned int new_cpu_id)
  758. {
  759. unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
  760. void __iomem *dist_base;
  761. int i, ror_val, cpu = smp_processor_id();
  762. u32 val, cur_target_mask, active_mask;
  763. BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
  764. dist_base = gic_data_dist_base(&gic_data[gic_nr]);
  765. if (!dist_base)
  766. return;
  767. gic_irqs = gic_data[gic_nr].gic_irqs;
  768. cur_cpu_id = __ffs(gic_cpu_map[cpu]);
  769. cur_target_mask = 0x01010101 << cur_cpu_id;
  770. ror_val = (cur_cpu_id - new_cpu_id) & 31;
  771. gic_lock();
  772. /* Update the target interface for this logical CPU */
  773. gic_cpu_map[cpu] = 1 << new_cpu_id;
  774. /*
  775. * Find all the peripheral interrupts targeting the current
  776. * CPU interface and migrate them to the new CPU interface.
  777. * We skip DIST_TARGET 0 to 7 as they are read-only.
  778. */
  779. for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
  780. val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
  781. active_mask = val & cur_target_mask;
  782. if (active_mask) {
  783. val &= ~active_mask;
  784. val |= ror32(active_mask, ror_val);
  785. writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
  786. }
  787. }
  788. gic_unlock();
  789. /*
  790. * Now let's migrate and clear any potential SGIs that might be
  791. * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
  792. * is a banked register, we can only forward the SGI using
  793. * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
  794. * doesn't use that information anyway.
  795. *
  796. * For the same reason we do not adjust SGI source information
  797. * for previously sent SGIs by us to other CPUs either.
  798. */
  799. for (i = 0; i < 16; i += 4) {
  800. int j;
  801. val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
  802. if (!val)
  803. continue;
  804. writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
  805. for (j = i; j < i + 4; j++) {
  806. if (val & 0xff)
  807. writel_relaxed((1 << (new_cpu_id + 16)) | j,
  808. dist_base + GIC_DIST_SOFTINT);
  809. val >>= 8;
  810. }
  811. }
  812. }
  813. /*
  814. * gic_get_sgir_physaddr - get the physical address for the SGI register
  815. *
  816. * REturn the physical address of the SGI register to be used
  817. * by some early assembly code when the kernel is not yet available.
  818. */
  819. static unsigned long gic_dist_physaddr;
  820. unsigned long gic_get_sgir_physaddr(void)
  821. {
  822. if (!gic_dist_physaddr)
  823. return 0;
  824. return gic_dist_physaddr + GIC_DIST_SOFTINT;
  825. }
  826. static void __init gic_init_physaddr(struct device_node *node)
  827. {
  828. struct resource res;
  829. if (of_address_to_resource(node, 0, &res) == 0) {
  830. gic_dist_physaddr = res.start;
  831. pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
  832. }
  833. }
  834. #else
  835. #define gic_init_physaddr(node) do { } while (0)
  836. #endif
  837. static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
  838. irq_hw_number_t hw)
  839. {
  840. struct gic_chip_data *gic = d->host_data;
  841. struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
  842. switch (hw) {
  843. case 0 ... 15:
  844. irq_set_percpu_devid(irq);
  845. irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
  846. handle_percpu_devid_fasteoi_ipi,
  847. NULL, NULL);
  848. break;
  849. case 16 ... 31:
  850. irq_set_percpu_devid(irq);
  851. irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
  852. handle_percpu_devid_irq, NULL, NULL);
  853. break;
  854. default:
  855. irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
  856. handle_fasteoi_irq, NULL, NULL);
  857. irq_set_probe(irq);
  858. irqd_set_single_target(irqd);
  859. break;
  860. }
  861. /* Prevents SW retriggers which mess up the ACK/EOI ordering */
  862. irqd_set_handle_enforce_irqctx(irqd);
  863. return 0;
  864. }
  865. static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
  866. {
  867. }
  868. static int gic_irq_domain_translate(struct irq_domain *d,
  869. struct irq_fwspec *fwspec,
  870. unsigned long *hwirq,
  871. unsigned int *type)
  872. {
  873. if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
  874. *hwirq = fwspec->param[0];
  875. *type = IRQ_TYPE_EDGE_RISING;
  876. return 0;
  877. }
  878. if (is_of_node(fwspec->fwnode)) {
  879. if (fwspec->param_count < 3)
  880. return -EINVAL;
  881. switch (fwspec->param[0]) {
  882. case 0: /* SPI */
  883. *hwirq = fwspec->param[1] + 32;
  884. break;
  885. case 1: /* PPI */
  886. *hwirq = fwspec->param[1] + 16;
  887. break;
  888. default:
  889. return -EINVAL;
  890. }
  891. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  892. /* Make it clear that broken DTs are... broken */
  893. WARN_ON(*type == IRQ_TYPE_NONE);
  894. return 0;
  895. }
  896. if (is_fwnode_irqchip(fwspec->fwnode)) {
  897. if(fwspec->param_count != 2)
  898. return -EINVAL;
  899. if (fwspec->param[0] < 16) {
  900. pr_err(FW_BUG "Illegal GSI%d translation request\n",
  901. fwspec->param[0]);
  902. return -EINVAL;
  903. }
  904. *hwirq = fwspec->param[0];
  905. *type = fwspec->param[1];
  906. WARN_ON(*type == IRQ_TYPE_NONE);
  907. return 0;
  908. }
  909. return -EINVAL;
  910. }
  911. static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  912. unsigned int nr_irqs, void *arg)
  913. {
  914. int i, ret;
  915. irq_hw_number_t hwirq;
  916. unsigned int type = IRQ_TYPE_NONE;
  917. struct irq_fwspec *fwspec = arg;
  918. ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
  919. if (ret)
  920. return ret;
  921. for (i = 0; i < nr_irqs; i++) {
  922. ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
  923. if (ret)
  924. return ret;
  925. }
  926. return 0;
  927. }
  928. static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
  929. .translate = gic_irq_domain_translate,
  930. .alloc = gic_irq_domain_alloc,
  931. .free = irq_domain_free_irqs_top,
  932. };
  933. static const struct irq_domain_ops gic_irq_domain_ops = {
  934. .map = gic_irq_domain_map,
  935. .unmap = gic_irq_domain_unmap,
  936. };
  937. static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
  938. const char *name, bool use_eoimode1)
  939. {
  940. /* Initialize irq_chip */
  941. gic->chip = gic_chip;
  942. gic->chip.name = name;
  943. gic->chip.parent_device = dev;
  944. if (use_eoimode1) {
  945. gic->chip.irq_mask = gic_eoimode1_mask_irq;
  946. gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
  947. gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
  948. }
  949. if (gic == &gic_data[0]) {
  950. gic->chip.irq_set_affinity = gic_set_affinity;
  951. gic->chip.ipi_send_mask = gic_ipi_send_mask;
  952. }
  953. }
  954. static int gic_init_bases(struct gic_chip_data *gic,
  955. struct fwnode_handle *handle)
  956. {
  957. int gic_irqs, ret;
  958. if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
  959. /* Frankein-GIC without banked registers... */
  960. unsigned int cpu;
  961. gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
  962. gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
  963. if (WARN_ON(!gic->dist_base.percpu_base ||
  964. !gic->cpu_base.percpu_base)) {
  965. ret = -ENOMEM;
  966. goto error;
  967. }
  968. for_each_possible_cpu(cpu) {
  969. u32 mpidr = cpu_logical_map(cpu);
  970. u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  971. unsigned long offset = gic->percpu_offset * core_id;
  972. *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
  973. gic->raw_dist_base + offset;
  974. *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
  975. gic->raw_cpu_base + offset;
  976. }
  977. enable_frankengic();
  978. } else {
  979. /* Normal, sane GIC... */
  980. WARN(gic->percpu_offset,
  981. "GIC_NON_BANKED not enabled, ignoring %08x offset!",
  982. gic->percpu_offset);
  983. gic->dist_base.common_base = gic->raw_dist_base;
  984. gic->cpu_base.common_base = gic->raw_cpu_base;
  985. }
  986. /*
  987. * Find out how many interrupts are supported.
  988. * The GIC only supports up to 1020 interrupt sources.
  989. */
  990. gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
  991. gic_irqs = (gic_irqs + 1) * 32;
  992. if (gic_irqs > 1020)
  993. gic_irqs = 1020;
  994. gic->gic_irqs = gic_irqs;
  995. if (handle) { /* DT/ACPI */
  996. gic->domain = irq_domain_create_linear(handle, gic_irqs,
  997. &gic_irq_domain_hierarchy_ops,
  998. gic);
  999. } else { /* Legacy support */
  1000. /*
  1001. * For primary GICs, skip over SGIs.
  1002. * No secondary GIC support whatsoever.
  1003. */
  1004. int irq_base;
  1005. gic_irqs -= 16; /* calculate # of irqs to allocate */
  1006. irq_base = irq_alloc_descs(16, 16, gic_irqs,
  1007. numa_node_id());
  1008. if (irq_base < 0) {
  1009. WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
  1010. irq_base = 16;
  1011. }
  1012. gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
  1013. 16, &gic_irq_domain_ops, gic);
  1014. }
  1015. if (WARN_ON(!gic->domain)) {
  1016. ret = -ENODEV;
  1017. goto error;
  1018. }
  1019. gic_dist_init(gic);
  1020. ret = gic_cpu_init(gic);
  1021. if (ret)
  1022. goto error;
  1023. ret = gic_pm_init(gic);
  1024. if (ret)
  1025. goto error;
  1026. return 0;
  1027. error:
  1028. if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
  1029. free_percpu(gic->dist_base.percpu_base);
  1030. free_percpu(gic->cpu_base.percpu_base);
  1031. }
  1032. return ret;
  1033. }
  1034. static int __init __gic_init_bases(struct gic_chip_data *gic,
  1035. struct fwnode_handle *handle)
  1036. {
  1037. char *name;
  1038. int i, ret;
  1039. if (WARN_ON(!gic || gic->domain))
  1040. return -EINVAL;
  1041. if (gic == &gic_data[0]) {
  1042. /*
  1043. * Initialize the CPU interface map to all CPUs.
  1044. * It will be refined as each CPU probes its ID.
  1045. * This is only necessary for the primary GIC.
  1046. */
  1047. for (i = 0; i < NR_GIC_CPU_IF; i++)
  1048. gic_cpu_map[i] = 0xff;
  1049. set_handle_irq(gic_handle_irq);
  1050. if (static_branch_likely(&supports_deactivate_key))
  1051. pr_info("GIC: Using split EOI/Deactivate mode\n");
  1052. }
  1053. if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
  1054. name = kasprintf(GFP_KERNEL, "GICv2");
  1055. gic_init_chip(gic, NULL, name, true);
  1056. } else {
  1057. name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
  1058. gic_init_chip(gic, NULL, name, false);
  1059. }
  1060. ret = gic_init_bases(gic, handle);
  1061. if (ret)
  1062. kfree(name);
  1063. else if (gic == &gic_data[0])
  1064. gic_smp_init();
  1065. return ret;
  1066. }
  1067. void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
  1068. {
  1069. struct gic_chip_data *gic;
  1070. /*
  1071. * Non-DT/ACPI systems won't run a hypervisor, so let's not
  1072. * bother with these...
  1073. */
  1074. static_branch_disable(&supports_deactivate_key);
  1075. gic = &gic_data[0];
  1076. gic->raw_dist_base = dist_base;
  1077. gic->raw_cpu_base = cpu_base;
  1078. __gic_init_bases(gic, NULL);
  1079. }
  1080. static void gic_teardown(struct gic_chip_data *gic)
  1081. {
  1082. if (WARN_ON(!gic))
  1083. return;
  1084. if (gic->raw_dist_base)
  1085. iounmap(gic->raw_dist_base);
  1086. if (gic->raw_cpu_base)
  1087. iounmap(gic->raw_cpu_base);
  1088. }
  1089. #ifdef CONFIG_OF
  1090. static int gic_cnt __initdata;
  1091. static bool gicv2_force_probe;
  1092. static int __init gicv2_force_probe_cfg(char *buf)
  1093. {
  1094. return strtobool(buf, &gicv2_force_probe);
  1095. }
  1096. early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
  1097. static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
  1098. {
  1099. struct resource cpuif_res;
  1100. of_address_to_resource(node, 1, &cpuif_res);
  1101. if (!is_hyp_mode_available())
  1102. return false;
  1103. if (resource_size(&cpuif_res) < SZ_8K) {
  1104. void __iomem *alt;
  1105. /*
  1106. * Check for a stupid firmware that only exposes the
  1107. * first page of a GICv2.
  1108. */
  1109. if (!gic_check_gicv2(*base))
  1110. return false;
  1111. if (!gicv2_force_probe) {
  1112. pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
  1113. return false;
  1114. }
  1115. alt = ioremap(cpuif_res.start, SZ_8K);
  1116. if (!alt)
  1117. return false;
  1118. if (!gic_check_gicv2(alt + SZ_4K)) {
  1119. /*
  1120. * The first page was that of a GICv2, and
  1121. * the second was *something*. Let's trust it
  1122. * to be a GICv2, and update the mapping.
  1123. */
  1124. pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
  1125. &cpuif_res.start);
  1126. iounmap(*base);
  1127. *base = alt;
  1128. return true;
  1129. }
  1130. /*
  1131. * We detected *two* initial GICv2 pages in a
  1132. * row. Could be a GICv2 aliased over two 64kB
  1133. * pages. Update the resource, map the iospace, and
  1134. * pray.
  1135. */
  1136. iounmap(alt);
  1137. alt = ioremap(cpuif_res.start, SZ_128K);
  1138. if (!alt)
  1139. return false;
  1140. pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
  1141. &cpuif_res.start);
  1142. cpuif_res.end = cpuif_res.start + SZ_128K -1;
  1143. iounmap(*base);
  1144. *base = alt;
  1145. }
  1146. if (resource_size(&cpuif_res) == SZ_128K) {
  1147. /*
  1148. * Verify that we have the first 4kB of a GICv2
  1149. * aliased over the first 64kB by checking the
  1150. * GICC_IIDR register on both ends.
  1151. */
  1152. if (!gic_check_gicv2(*base) ||
  1153. !gic_check_gicv2(*base + 0xf000))
  1154. return false;
  1155. /*
  1156. * Move the base up by 60kB, so that we have a 8kB
  1157. * contiguous region, which allows us to use GICC_DIR
  1158. * at its normal offset. Please pass me that bucket.
  1159. */
  1160. *base += 0xf000;
  1161. cpuif_res.start += 0xf000;
  1162. pr_warn("GIC: Adjusting CPU interface base to %pa\n",
  1163. &cpuif_res.start);
  1164. }
  1165. return true;
  1166. }
  1167. static bool gic_enable_rmw_access(void *data)
  1168. {
  1169. /*
  1170. * The EMEV2 class of machines has a broken interconnect, and
  1171. * locks up on accesses that are less than 32bit. So far, only
  1172. * the affinity setting requires it.
  1173. */
  1174. if (of_machine_is_compatible("renesas,emev2")) {
  1175. static_branch_enable(&needs_rmw_access);
  1176. return true;
  1177. }
  1178. return false;
  1179. }
  1180. static const struct gic_quirk gic_quirks[] = {
  1181. {
  1182. .desc = "broken byte access",
  1183. .compatible = "arm,pl390",
  1184. .init = gic_enable_rmw_access,
  1185. },
  1186. { },
  1187. };
  1188. static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
  1189. {
  1190. if (!gic || !node)
  1191. return -EINVAL;
  1192. gic->raw_dist_base = of_iomap(node, 0);
  1193. if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
  1194. goto error;
  1195. gic->raw_cpu_base = of_iomap(node, 1);
  1196. if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
  1197. goto error;
  1198. if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
  1199. gic->percpu_offset = 0;
  1200. gic_enable_of_quirks(node, gic_quirks, gic);
  1201. return 0;
  1202. error:
  1203. gic_teardown(gic);
  1204. return -ENOMEM;
  1205. }
  1206. int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
  1207. {
  1208. int ret;
  1209. if (!dev || !dev->of_node || !gic || !irq)
  1210. return -EINVAL;
  1211. *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
  1212. if (!*gic)
  1213. return -ENOMEM;
  1214. gic_init_chip(*gic, dev, dev->of_node->name, false);
  1215. ret = gic_of_setup(*gic, dev->of_node);
  1216. if (ret)
  1217. return ret;
  1218. ret = gic_init_bases(*gic, &dev->of_node->fwnode);
  1219. if (ret) {
  1220. gic_teardown(*gic);
  1221. return ret;
  1222. }
  1223. irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
  1224. return 0;
  1225. }
  1226. static void __init gic_of_setup_kvm_info(struct device_node *node)
  1227. {
  1228. int ret;
  1229. struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
  1230. struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
  1231. gic_v2_kvm_info.type = GIC_V2;
  1232. gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
  1233. if (!gic_v2_kvm_info.maint_irq)
  1234. return;
  1235. ret = of_address_to_resource(node, 2, vctrl_res);
  1236. if (ret)
  1237. return;
  1238. ret = of_address_to_resource(node, 3, vcpu_res);
  1239. if (ret)
  1240. return;
  1241. if (static_branch_likely(&supports_deactivate_key))
  1242. gic_set_kvm_info(&gic_v2_kvm_info);
  1243. }
  1244. int __init
  1245. gic_of_init(struct device_node *node, struct device_node *parent)
  1246. {
  1247. struct gic_chip_data *gic;
  1248. int irq, ret;
  1249. if (WARN_ON(!node))
  1250. return -ENODEV;
  1251. if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
  1252. return -EINVAL;
  1253. gic = &gic_data[gic_cnt];
  1254. ret = gic_of_setup(gic, node);
  1255. if (ret)
  1256. return ret;
  1257. /*
  1258. * Disable split EOI/Deactivate if either HYP is not available
  1259. * or the CPU interface is too small.
  1260. */
  1261. if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
  1262. static_branch_disable(&supports_deactivate_key);
  1263. ret = __gic_init_bases(gic, &node->fwnode);
  1264. if (ret) {
  1265. gic_teardown(gic);
  1266. return ret;
  1267. }
  1268. if (!gic_cnt) {
  1269. gic_init_physaddr(node);
  1270. gic_of_setup_kvm_info(node);
  1271. }
  1272. if (parent) {
  1273. irq = irq_of_parse_and_map(node, 0);
  1274. gic_cascade_irq(gic_cnt, irq);
  1275. }
  1276. if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
  1277. gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
  1278. gic_cnt++;
  1279. return 0;
  1280. }
  1281. IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
  1282. IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
  1283. IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
  1284. IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
  1285. IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
  1286. IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
  1287. IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
  1288. IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
  1289. IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
  1290. #else
  1291. int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
  1292. {
  1293. return -ENOTSUPP;
  1294. }
  1295. #endif
  1296. #ifdef CONFIG_ACPI
  1297. static struct
  1298. {
  1299. phys_addr_t cpu_phys_base;
  1300. u32 maint_irq;
  1301. int maint_irq_mode;
  1302. phys_addr_t vctrl_base;
  1303. phys_addr_t vcpu_base;
  1304. } acpi_data __initdata;
  1305. static int __init
  1306. gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
  1307. const unsigned long end)
  1308. {
  1309. struct acpi_madt_generic_interrupt *processor;
  1310. phys_addr_t gic_cpu_base;
  1311. static int cpu_base_assigned;
  1312. processor = (struct acpi_madt_generic_interrupt *)header;
  1313. if (BAD_MADT_GICC_ENTRY(processor, end))
  1314. return -EINVAL;
  1315. /*
  1316. * There is no support for non-banked GICv1/2 register in ACPI spec.
  1317. * All CPU interface addresses have to be the same.
  1318. */
  1319. gic_cpu_base = processor->base_address;
  1320. if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
  1321. return -EINVAL;
  1322. acpi_data.cpu_phys_base = gic_cpu_base;
  1323. acpi_data.maint_irq = processor->vgic_interrupt;
  1324. acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
  1325. ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
  1326. acpi_data.vctrl_base = processor->gich_base_address;
  1327. acpi_data.vcpu_base = processor->gicv_base_address;
  1328. cpu_base_assigned = 1;
  1329. return 0;
  1330. }
  1331. /* The things you have to do to just *count* something... */
  1332. static int __init acpi_dummy_func(union acpi_subtable_headers *header,
  1333. const unsigned long end)
  1334. {
  1335. return 0;
  1336. }
  1337. static bool __init acpi_gic_redist_is_present(void)
  1338. {
  1339. return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
  1340. acpi_dummy_func, 0) > 0;
  1341. }
  1342. static bool __init gic_validate_dist(struct acpi_subtable_header *header,
  1343. struct acpi_probe_entry *ape)
  1344. {
  1345. struct acpi_madt_generic_distributor *dist;
  1346. dist = (struct acpi_madt_generic_distributor *)header;
  1347. return (dist->version == ape->driver_data &&
  1348. (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
  1349. !acpi_gic_redist_is_present()));
  1350. }
  1351. #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
  1352. #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
  1353. #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
  1354. #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
  1355. static void __init gic_acpi_setup_kvm_info(void)
  1356. {
  1357. int irq;
  1358. struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
  1359. struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
  1360. gic_v2_kvm_info.type = GIC_V2;
  1361. if (!acpi_data.vctrl_base)
  1362. return;
  1363. vctrl_res->flags = IORESOURCE_MEM;
  1364. vctrl_res->start = acpi_data.vctrl_base;
  1365. vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
  1366. if (!acpi_data.vcpu_base)
  1367. return;
  1368. vcpu_res->flags = IORESOURCE_MEM;
  1369. vcpu_res->start = acpi_data.vcpu_base;
  1370. vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
  1371. irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
  1372. acpi_data.maint_irq_mode,
  1373. ACPI_ACTIVE_HIGH);
  1374. if (irq <= 0)
  1375. return;
  1376. gic_v2_kvm_info.maint_irq = irq;
  1377. gic_set_kvm_info(&gic_v2_kvm_info);
  1378. }
  1379. static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
  1380. const unsigned long end)
  1381. {
  1382. struct acpi_madt_generic_distributor *dist;
  1383. struct fwnode_handle *domain_handle;
  1384. struct gic_chip_data *gic = &gic_data[0];
  1385. int count, ret;
  1386. /* Collect CPU base addresses */
  1387. count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
  1388. gic_acpi_parse_madt_cpu, 0);
  1389. if (count <= 0) {
  1390. pr_err("No valid GICC entries exist\n");
  1391. return -EINVAL;
  1392. }
  1393. gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
  1394. if (!gic->raw_cpu_base) {
  1395. pr_err("Unable to map GICC registers\n");
  1396. return -ENOMEM;
  1397. }
  1398. dist = (struct acpi_madt_generic_distributor *)header;
  1399. gic->raw_dist_base = ioremap(dist->base_address,
  1400. ACPI_GICV2_DIST_MEM_SIZE);
  1401. if (!gic->raw_dist_base) {
  1402. pr_err("Unable to map GICD registers\n");
  1403. gic_teardown(gic);
  1404. return -ENOMEM;
  1405. }
  1406. /*
  1407. * Disable split EOI/Deactivate if HYP is not available. ACPI
  1408. * guarantees that we'll always have a GICv2, so the CPU
  1409. * interface will always be the right size.
  1410. */
  1411. if (!is_hyp_mode_available())
  1412. static_branch_disable(&supports_deactivate_key);
  1413. /*
  1414. * Initialize GIC instance zero (no multi-GIC support).
  1415. */
  1416. domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
  1417. if (!domain_handle) {
  1418. pr_err("Unable to allocate domain handle\n");
  1419. gic_teardown(gic);
  1420. return -ENOMEM;
  1421. }
  1422. ret = __gic_init_bases(gic, domain_handle);
  1423. if (ret) {
  1424. pr_err("Failed to initialise GIC\n");
  1425. irq_domain_free_fwnode(domain_handle);
  1426. gic_teardown(gic);
  1427. return ret;
  1428. }
  1429. acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
  1430. if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
  1431. gicv2m_init(NULL, gic_data[0].domain);
  1432. if (static_branch_likely(&supports_deactivate_key))
  1433. gic_acpi_setup_kvm_info();
  1434. return 0;
  1435. }
  1436. IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
  1437. gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
  1438. gic_v2_acpi_init);
  1439. IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
  1440. gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
  1441. gic_v2_acpi_init);
  1442. #endif