irq-gic-common.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2002 ARM Limited, All Rights Reserved.
  4. */
  5. #include <linux/interrupt.h>
  6. #include <linux/io.h>
  7. #include <linux/irq.h>
  8. #include <linux/irqchip/arm-gic.h>
  9. #include "irq-gic-common.h"
  10. static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  11. static const struct gic_kvm_info *gic_kvm_info;
  12. const struct gic_kvm_info *gic_get_kvm_info(void)
  13. {
  14. return gic_kvm_info;
  15. }
  16. void gic_set_kvm_info(const struct gic_kvm_info *info)
  17. {
  18. BUG_ON(gic_kvm_info != NULL);
  19. gic_kvm_info = info;
  20. }
  21. void gic_enable_of_quirks(const struct device_node *np,
  22. const struct gic_quirk *quirks, void *data)
  23. {
  24. for (; quirks->desc; quirks++) {
  25. if (!of_device_is_compatible(np, quirks->compatible))
  26. continue;
  27. if (quirks->init(data))
  28. pr_info("GIC: enabling workaround for %s\n",
  29. quirks->desc);
  30. }
  31. }
  32. void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
  33. void *data)
  34. {
  35. for (; quirks->desc; quirks++) {
  36. if (quirks->compatible)
  37. continue;
  38. if (quirks->iidr != (quirks->mask & iidr))
  39. continue;
  40. if (quirks->init(data))
  41. pr_info("GIC: enabling workaround for %s\n",
  42. quirks->desc);
  43. }
  44. }
  45. int gic_configure_irq(unsigned int irq, unsigned int type,
  46. void __iomem *base, void (*sync_access)(void))
  47. {
  48. u32 confmask = 0x2 << ((irq % 16) * 2);
  49. u32 confoff = (irq / 16) * 4;
  50. u32 val, oldval;
  51. int ret = 0;
  52. unsigned long flags;
  53. /*
  54. * Read current configuration register, and insert the config
  55. * for "irq", depending on "type".
  56. */
  57. raw_spin_lock_irqsave(&irq_controller_lock, flags);
  58. val = oldval = readl_relaxed(base + confoff);
  59. if (type & IRQ_TYPE_LEVEL_MASK)
  60. val &= ~confmask;
  61. else if (type & IRQ_TYPE_EDGE_BOTH)
  62. val |= confmask;
  63. /* If the current configuration is the same, then we are done */
  64. if (val == oldval) {
  65. raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
  66. return 0;
  67. }
  68. /*
  69. * Write back the new configuration, and possibly re-enable
  70. * the interrupt. If we fail to write a new configuration for
  71. * an SPI then WARN and return an error. If we fail to write the
  72. * configuration for a PPI this is most likely because the GIC
  73. * does not allow us to set the configuration or we are in a
  74. * non-secure mode, and hence it may not be catastrophic.
  75. */
  76. writel_relaxed(val, base + confoff);
  77. if (readl_relaxed(base + confoff) != val)
  78. ret = -EINVAL;
  79. raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
  80. if (sync_access)
  81. sync_access();
  82. return ret;
  83. }
  84. void gic_dist_config(void __iomem *base, int gic_irqs,
  85. void (*sync_access)(void))
  86. {
  87. unsigned int i;
  88. /*
  89. * Set all global interrupts to be level triggered, active low.
  90. */
  91. for (i = 32; i < gic_irqs; i += 16)
  92. writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
  93. base + GIC_DIST_CONFIG + i / 4);
  94. /*
  95. * Set priority on all global interrupts.
  96. */
  97. for (i = 32; i < gic_irqs; i += 4)
  98. writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
  99. /*
  100. * Deactivate and disable all SPIs. Leave the PPI and SGIs
  101. * alone as they are in the redistributor registers on GICv3.
  102. */
  103. for (i = 32; i < gic_irqs; i += 32) {
  104. writel_relaxed(GICD_INT_EN_CLR_X32,
  105. base + GIC_DIST_ACTIVE_CLEAR + i / 8);
  106. writel_relaxed(GICD_INT_EN_CLR_X32,
  107. base + GIC_DIST_ENABLE_CLEAR + i / 8);
  108. }
  109. if (sync_access)
  110. sync_access();
  111. }
  112. void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
  113. {
  114. int i;
  115. /*
  116. * Deal with the banked PPI and SGI interrupts - disable all
  117. * private interrupts. Make sure everything is deactivated.
  118. */
  119. for (i = 0; i < nr; i += 32) {
  120. writel_relaxed(GICD_INT_EN_CLR_X32,
  121. base + GIC_DIST_ACTIVE_CLEAR + i / 8);
  122. writel_relaxed(GICD_INT_EN_CLR_X32,
  123. base + GIC_DIST_ENABLE_CLEAR + i / 8);
  124. }
  125. /*
  126. * Set priority on PPI and SGI interrupts
  127. */
  128. for (i = 0; i < nr; i += 4)
  129. writel_relaxed(GICD_INT_DEF_PRI_X4,
  130. base + GIC_DIST_PRI + i * 4 / 4);
  131. if (sync_access)
  132. sync_access();
  133. }