irq-ftintc010.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * irqchip for the Faraday Technology FTINTC010 Copyright (C) 2017 Linus
  4. * Walleij <linus.walleij@linaro.org>
  5. *
  6. * Based on arch/arm/mach-gemini/irq.c
  7. * Copyright (C) 2001-2006 Storlink, Corp.
  8. * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/irq.h>
  12. #include <linux/io.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/irqchip/versatile-fpga.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/cpu.h>
  21. #include <asm/exception.h>
  22. #include <asm/mach/irq.h>
  23. #define FT010_NUM_IRQS 32
  24. #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00)
  25. #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04)
  26. #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08)
  27. /* Selects level- or edge-triggered */
  28. #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C)
  29. /* Selects active low/high or falling/rising edge */
  30. #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10)
  31. #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14)
  32. #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20)
  33. #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24)
  34. #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28)
  35. #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C)
  36. #define FT010_FIQ_POLARITY(base_addr) (base_addr + 0x30)
  37. #define FT010_FIQ_STATUS(base_addr) (base_addr + 0x34)
  38. /**
  39. * struct ft010_irq_data - irq data container for the Faraday IRQ controller
  40. * @base: memory offset in virtual memory
  41. * @chip: chip container for this instance
  42. * @domain: IRQ domain for this instance
  43. */
  44. struct ft010_irq_data {
  45. void __iomem *base;
  46. struct irq_chip chip;
  47. struct irq_domain *domain;
  48. };
  49. static void ft010_irq_mask(struct irq_data *d)
  50. {
  51. struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
  52. unsigned int mask;
  53. mask = readl(FT010_IRQ_MASK(f->base));
  54. mask &= ~BIT(irqd_to_hwirq(d));
  55. writel(mask, FT010_IRQ_MASK(f->base));
  56. }
  57. static void ft010_irq_unmask(struct irq_data *d)
  58. {
  59. struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
  60. unsigned int mask;
  61. mask = readl(FT010_IRQ_MASK(f->base));
  62. mask |= BIT(irqd_to_hwirq(d));
  63. writel(mask, FT010_IRQ_MASK(f->base));
  64. }
  65. static void ft010_irq_ack(struct irq_data *d)
  66. {
  67. struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
  68. writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
  69. }
  70. static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger)
  71. {
  72. struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
  73. int offset = irqd_to_hwirq(d);
  74. u32 mode, polarity;
  75. mode = readl(FT010_IRQ_MODE(f->base));
  76. polarity = readl(FT010_IRQ_POLARITY(f->base));
  77. if (trigger & (IRQ_TYPE_LEVEL_LOW)) {
  78. irq_set_handler_locked(d, handle_level_irq);
  79. mode &= ~BIT(offset);
  80. polarity |= BIT(offset);
  81. } else if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
  82. irq_set_handler_locked(d, handle_level_irq);
  83. mode &= ~BIT(offset);
  84. polarity &= ~BIT(offset);
  85. } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
  86. irq_set_handler_locked(d, handle_edge_irq);
  87. mode |= BIT(offset);
  88. polarity |= BIT(offset);
  89. } else if (trigger & IRQ_TYPE_EDGE_RISING) {
  90. irq_set_handler_locked(d, handle_edge_irq);
  91. mode |= BIT(offset);
  92. polarity &= ~BIT(offset);
  93. } else {
  94. irq_set_handler_locked(d, handle_bad_irq);
  95. pr_warn("Faraday IRQ: no supported trigger selected for line %d\n",
  96. offset);
  97. }
  98. writel(mode, FT010_IRQ_MODE(f->base));
  99. writel(polarity, FT010_IRQ_POLARITY(f->base));
  100. return 0;
  101. }
  102. static struct irq_chip ft010_irq_chip = {
  103. .name = "FTINTC010",
  104. .irq_ack = ft010_irq_ack,
  105. .irq_mask = ft010_irq_mask,
  106. .irq_unmask = ft010_irq_unmask,
  107. .irq_set_type = ft010_irq_set_type,
  108. };
  109. /* Local static for the IRQ entry call */
  110. static struct ft010_irq_data firq;
  111. asmlinkage void __exception_irq_entry ft010_irqchip_handle_irq(struct pt_regs *regs)
  112. {
  113. struct ft010_irq_data *f = &firq;
  114. int irq;
  115. u32 status;
  116. while ((status = readl(FT010_IRQ_STATUS(f->base)))) {
  117. irq = ffs(status) - 1;
  118. handle_domain_irq(f->domain, irq, regs);
  119. }
  120. }
  121. static int ft010_irqdomain_map(struct irq_domain *d, unsigned int irq,
  122. irq_hw_number_t hwirq)
  123. {
  124. struct ft010_irq_data *f = d->host_data;
  125. irq_set_chip_data(irq, f);
  126. /* All IRQs should set up their type, flags as bad by default */
  127. irq_set_chip_and_handler(irq, &ft010_irq_chip, handle_bad_irq);
  128. irq_set_probe(irq);
  129. return 0;
  130. }
  131. static void ft010_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
  132. {
  133. irq_set_chip_and_handler(irq, NULL, NULL);
  134. irq_set_chip_data(irq, NULL);
  135. }
  136. static const struct irq_domain_ops ft010_irqdomain_ops = {
  137. .map = ft010_irqdomain_map,
  138. .unmap = ft010_irqdomain_unmap,
  139. .xlate = irq_domain_xlate_onetwocell,
  140. };
  141. int __init ft010_of_init_irq(struct device_node *node,
  142. struct device_node *parent)
  143. {
  144. struct ft010_irq_data *f = &firq;
  145. /*
  146. * Disable the idle handler by default since it is buggy
  147. * For more info see arch/arm/mach-gemini/idle.c
  148. */
  149. cpu_idle_poll_ctrl(true);
  150. f->base = of_iomap(node, 0);
  151. WARN(!f->base, "unable to map gemini irq registers\n");
  152. /* Disable all interrupts */
  153. writel(0, FT010_IRQ_MASK(f->base));
  154. writel(0, FT010_FIQ_MASK(f->base));
  155. f->domain = irq_domain_add_simple(node, FT010_NUM_IRQS, 0,
  156. &ft010_irqdomain_ops, f);
  157. set_handle_irq(ft010_irqchip_handle_irq);
  158. return 0;
  159. }
  160. IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
  161. ft010_of_init_irq);
  162. IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
  163. ft010_of_init_irq);
  164. IRQCHIP_DECLARE(moxa, "moxa,moxart-ic",
  165. ft010_of_init_irq);