irq-eznps.c 4.5 KB

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  1. /*
  2. * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/interrupt.h>
  33. #include <linux/module.h>
  34. #include <linux/of.h>
  35. #include <linux/irq.h>
  36. #include <linux/irqdomain.h>
  37. #include <linux/irqchip.h>
  38. #include <soc/nps/common.h>
  39. #define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
  40. #define NPS_TIMER0_IRQ 3
  41. /*
  42. * NPS400 core includes an Interrupt Controller (IC) support.
  43. * All cores can deactivate level irqs at first level control
  44. * at cores mesh layer called MTM.
  45. * For devices out side chip e.g. uart, network there is another
  46. * level called Global Interrupt Manager (GIM).
  47. * This second level can control level and edge interrupt.
  48. *
  49. * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
  50. * with private HW copy per CPU.
  51. */
  52. static void nps400_irq_mask(struct irq_data *irqd)
  53. {
  54. unsigned int ienb;
  55. unsigned int irq = irqd_to_hwirq(irqd);
  56. ienb = read_aux_reg(AUX_IENABLE);
  57. ienb &= ~(1 << irq);
  58. write_aux_reg(AUX_IENABLE, ienb);
  59. }
  60. static void nps400_irq_unmask(struct irq_data *irqd)
  61. {
  62. unsigned int ienb;
  63. unsigned int irq = irqd_to_hwirq(irqd);
  64. ienb = read_aux_reg(AUX_IENABLE);
  65. ienb |= (1 << irq);
  66. write_aux_reg(AUX_IENABLE, ienb);
  67. }
  68. static void nps400_irq_eoi_global(struct irq_data *irqd)
  69. {
  70. unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
  71. write_aux_reg(CTOP_AUX_IACK, 1 << irq);
  72. /* Don't ack GIC before all device access attempts are done */
  73. mb();
  74. nps_ack_gic();
  75. }
  76. static void nps400_irq_ack(struct irq_data *irqd)
  77. {
  78. unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
  79. write_aux_reg(CTOP_AUX_IACK, 1 << irq);
  80. }
  81. static struct irq_chip nps400_irq_chip_fasteoi = {
  82. .name = "NPS400 IC Global",
  83. .irq_mask = nps400_irq_mask,
  84. .irq_unmask = nps400_irq_unmask,
  85. .irq_eoi = nps400_irq_eoi_global,
  86. };
  87. static struct irq_chip nps400_irq_chip_percpu = {
  88. .name = "NPS400 IC",
  89. .irq_mask = nps400_irq_mask,
  90. .irq_unmask = nps400_irq_unmask,
  91. .irq_ack = nps400_irq_ack,
  92. };
  93. static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
  94. irq_hw_number_t hw)
  95. {
  96. switch (hw) {
  97. case NPS_TIMER0_IRQ:
  98. #ifdef CONFIG_SMP
  99. case NPS_IPI_IRQ:
  100. #endif
  101. irq_set_percpu_devid(virq);
  102. irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
  103. handle_percpu_devid_irq);
  104. break;
  105. default:
  106. irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
  107. handle_fasteoi_irq);
  108. break;
  109. }
  110. return 0;
  111. }
  112. static const struct irq_domain_ops nps400_irq_ops = {
  113. .xlate = irq_domain_xlate_onecell,
  114. .map = nps400_irq_map,
  115. };
  116. static int __init nps400_of_init(struct device_node *node,
  117. struct device_node *parent)
  118. {
  119. struct irq_domain *nps400_root_domain;
  120. if (parent) {
  121. pr_err("DeviceTree incore ic not a root irq controller\n");
  122. return -EINVAL;
  123. }
  124. nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
  125. &nps400_irq_ops, NULL);
  126. if (!nps400_root_domain) {
  127. pr_err("nps400 root irq domain not avail\n");
  128. return -ENOMEM;
  129. }
  130. /*
  131. * Needed for primary domain lookup to succeed
  132. * This is a primary irqchip, and can never have a parent
  133. */
  134. irq_set_default_host(nps400_root_domain);
  135. #ifdef CONFIG_SMP
  136. irq_create_mapping(nps400_root_domain, NPS_IPI_IRQ);
  137. #endif
  138. return 0;
  139. }
  140. IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);