irq-dw-apb-ictl.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. /*
  2. * Synopsys DW APB ICTL irqchip driver.
  3. *
  4. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  5. *
  6. * based on GPL'ed 2.6 kernel sources
  7. * (c) Marvell International Ltd.
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/interrupt.h>
  20. #define APB_INT_ENABLE_L 0x00
  21. #define APB_INT_ENABLE_H 0x04
  22. #define APB_INT_MASK_L 0x08
  23. #define APB_INT_MASK_H 0x0c
  24. #define APB_INT_FINALSTATUS_L 0x30
  25. #define APB_INT_FINALSTATUS_H 0x34
  26. #define APB_INT_BASE_OFFSET 0x04
  27. /* irq domain of the primary interrupt controller. */
  28. static struct irq_domain *dw_apb_ictl_irq_domain;
  29. static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs)
  30. {
  31. struct irq_domain *d = dw_apb_ictl_irq_domain;
  32. int n;
  33. for (n = 0; n < d->revmap_size; n += 32) {
  34. struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
  35. u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
  36. while (stat) {
  37. u32 hwirq = ffs(stat) - 1;
  38. handle_domain_irq(d, hwirq, regs);
  39. stat &= ~BIT(hwirq);
  40. }
  41. }
  42. }
  43. static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)
  44. {
  45. struct irq_domain *d = irq_desc_get_handler_data(desc);
  46. struct irq_chip *chip = irq_desc_get_chip(desc);
  47. int n;
  48. chained_irq_enter(chip, desc);
  49. for (n = 0; n < d->revmap_size; n += 32) {
  50. struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
  51. u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
  52. while (stat) {
  53. u32 hwirq = ffs(stat) - 1;
  54. u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
  55. generic_handle_irq(virq);
  56. stat &= ~BIT(hwirq);
  57. }
  58. }
  59. chained_irq_exit(chip, desc);
  60. }
  61. static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  62. unsigned int nr_irqs, void *arg)
  63. {
  64. int i, ret;
  65. irq_hw_number_t hwirq;
  66. unsigned int type = IRQ_TYPE_NONE;
  67. struct irq_fwspec *fwspec = arg;
  68. ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
  69. if (ret)
  70. return ret;
  71. for (i = 0; i < nr_irqs; i++)
  72. irq_map_generic_chip(domain, virq + i, hwirq + i);
  73. return 0;
  74. }
  75. static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = {
  76. .translate = irq_domain_translate_onecell,
  77. .alloc = dw_apb_ictl_irq_domain_alloc,
  78. .free = irq_domain_free_irqs_top,
  79. };
  80. #ifdef CONFIG_PM
  81. static void dw_apb_ictl_resume(struct irq_data *d)
  82. {
  83. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  84. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  85. irq_gc_lock(gc);
  86. writel_relaxed(~0, gc->reg_base + ct->regs.enable);
  87. writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
  88. irq_gc_unlock(gc);
  89. }
  90. #else
  91. #define dw_apb_ictl_resume NULL
  92. #endif /* CONFIG_PM */
  93. static int __init dw_apb_ictl_init(struct device_node *np,
  94. struct device_node *parent)
  95. {
  96. const struct irq_domain_ops *domain_ops;
  97. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  98. struct resource r;
  99. struct irq_domain *domain;
  100. struct irq_chip_generic *gc;
  101. void __iomem *iobase;
  102. int ret, nrirqs, parent_irq, i;
  103. u32 reg;
  104. if (!parent) {
  105. /* Used as the primary interrupt controller */
  106. parent_irq = 0;
  107. domain_ops = &dw_apb_ictl_irq_domain_ops;
  108. } else {
  109. /* Map the parent interrupt for the chained handler */
  110. parent_irq = irq_of_parse_and_map(np, 0);
  111. if (parent_irq <= 0) {
  112. pr_err("%pOF: unable to parse irq\n", np);
  113. return -EINVAL;
  114. }
  115. domain_ops = &irq_generic_chip_ops;
  116. }
  117. ret = of_address_to_resource(np, 0, &r);
  118. if (ret) {
  119. pr_err("%pOF: unable to get resource\n", np);
  120. return ret;
  121. }
  122. if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
  123. pr_err("%pOF: unable to request mem region\n", np);
  124. return -ENOMEM;
  125. }
  126. iobase = ioremap(r.start, resource_size(&r));
  127. if (!iobase) {
  128. pr_err("%pOF: unable to map resource\n", np);
  129. ret = -ENOMEM;
  130. goto err_release;
  131. }
  132. /*
  133. * DW IP can be configured to allow 2-64 irqs. We can determine
  134. * the number of irqs supported by writing into enable register
  135. * and look for bits not set, as corresponding flip-flops will
  136. * have been removed by synthesis tool.
  137. */
  138. /* mask and enable all interrupts */
  139. writel_relaxed(~0, iobase + APB_INT_MASK_L);
  140. writel_relaxed(~0, iobase + APB_INT_MASK_H);
  141. writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
  142. writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
  143. reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
  144. if (reg)
  145. nrirqs = 32 + fls(reg);
  146. else
  147. nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
  148. domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL);
  149. if (!domain) {
  150. pr_err("%pOF: unable to add irq domain\n", np);
  151. ret = -ENOMEM;
  152. goto err_unmap;
  153. }
  154. ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name,
  155. handle_level_irq, clr, 0,
  156. IRQ_GC_INIT_MASK_CACHE);
  157. if (ret) {
  158. pr_err("%pOF: unable to alloc irq domain gc\n", np);
  159. goto err_unmap;
  160. }
  161. for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) {
  162. gc = irq_get_domain_generic_chip(domain, i * 32);
  163. gc->reg_base = iobase + i * APB_INT_BASE_OFFSET;
  164. gc->chip_types[0].regs.mask = APB_INT_MASK_L;
  165. gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;
  166. gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
  167. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
  168. gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
  169. }
  170. if (parent_irq) {
  171. irq_set_chained_handler_and_data(parent_irq,
  172. dw_apb_ictl_handle_irq_cascaded, domain);
  173. } else {
  174. dw_apb_ictl_irq_domain = domain;
  175. set_handle_irq(dw_apb_ictl_handle_irq);
  176. }
  177. return 0;
  178. err_unmap:
  179. iounmap(iobase);
  180. err_release:
  181. release_mem_region(r.start, resource_size(&r));
  182. return ret;
  183. }
  184. IRQCHIP_DECLARE(dw_apb_ictl,
  185. "snps,dw-apb-ictl", dw_apb_ictl_init);