irq-digicolor.c 3.2 KB

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  1. /*
  2. * Conexant Digicolor SoCs IRQ chip driver
  3. *
  4. * Author: Baruch Siach <baruch@tkos.co.il>
  5. *
  6. * Copyright (C) 2014 Paradox Innovation Ltd.
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqchip.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/regmap.h>
  20. #include <asm/exception.h>
  21. #define UC_IRQ_CONTROL 0x04
  22. #define IC_FLAG_CLEAR_LO 0x00
  23. #define IC_FLAG_CLEAR_XLO 0x04
  24. #define IC_INT0ENABLE_LO 0x10
  25. #define IC_INT0ENABLE_XLO 0x14
  26. #define IC_INT0STATUS_LO 0x18
  27. #define IC_INT0STATUS_XLO 0x1c
  28. static struct irq_domain *digicolor_irq_domain;
  29. static void __exception_irq_entry digicolor_handle_irq(struct pt_regs *regs)
  30. {
  31. struct irq_domain_chip_generic *dgc = digicolor_irq_domain->gc;
  32. struct irq_chip_generic *gc = dgc->gc[0];
  33. u32 status, hwirq;
  34. do {
  35. status = irq_reg_readl(gc, IC_INT0STATUS_LO);
  36. if (status) {
  37. hwirq = ffs(status) - 1;
  38. } else {
  39. status = irq_reg_readl(gc, IC_INT0STATUS_XLO);
  40. if (status)
  41. hwirq = ffs(status) - 1 + 32;
  42. else
  43. return;
  44. }
  45. handle_domain_irq(digicolor_irq_domain, hwirq, regs);
  46. } while (1);
  47. }
  48. static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base,
  49. unsigned en_reg, unsigned ack_reg)
  50. {
  51. struct irq_chip_generic *gc;
  52. gc = irq_get_domain_generic_chip(digicolor_irq_domain, irq_base);
  53. gc->reg_base = reg_base;
  54. gc->chip_types[0].regs.ack = ack_reg;
  55. gc->chip_types[0].regs.mask = en_reg;
  56. gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
  57. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  58. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  59. }
  60. static int __init digicolor_of_init(struct device_node *node,
  61. struct device_node *parent)
  62. {
  63. void __iomem *reg_base;
  64. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  65. struct regmap *ucregs;
  66. int ret;
  67. reg_base = of_iomap(node, 0);
  68. if (!reg_base) {
  69. pr_err("%pOF: unable to map IC registers\n", node);
  70. return -ENXIO;
  71. }
  72. /* disable all interrupts */
  73. writel(0, reg_base + IC_INT0ENABLE_LO);
  74. writel(0, reg_base + IC_INT0ENABLE_XLO);
  75. ucregs = syscon_regmap_lookup_by_phandle(node, "syscon");
  76. if (IS_ERR(ucregs)) {
  77. pr_err("%pOF: unable to map UC registers\n", node);
  78. return PTR_ERR(ucregs);
  79. }
  80. /* channel 1, regular IRQs */
  81. regmap_write(ucregs, UC_IRQ_CONTROL, 1);
  82. digicolor_irq_domain =
  83. irq_domain_add_linear(node, 64, &irq_generic_chip_ops, NULL);
  84. if (!digicolor_irq_domain) {
  85. pr_err("%pOF: unable to create IRQ domain\n", node);
  86. return -ENOMEM;
  87. }
  88. ret = irq_alloc_domain_generic_chips(digicolor_irq_domain, 32, 1,
  89. "digicolor_irq", handle_level_irq,
  90. clr, 0, 0);
  91. if (ret) {
  92. pr_err("%pOF: unable to allocate IRQ gc\n", node);
  93. return ret;
  94. }
  95. digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO);
  96. digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO);
  97. set_handle_irq(digicolor_handle_irq);
  98. return 0;
  99. }
  100. IRQCHIP_DECLARE(conexant_digicolor_ic, "cnxt,cx92755-ic", digicolor_of_init);