irq-davinci-aintc.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. //
  3. // Copyright (C) 2006, 2019 Texas Instruments.
  4. //
  5. // Interrupt handler for DaVinci boards.
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqchip/irq-davinci-aintc.h>
  11. #include <linux/io.h>
  12. #include <linux/irqdomain.h>
  13. #include <asm/exception.h>
  14. #define DAVINCI_AINTC_FIQ_REG0 0x00
  15. #define DAVINCI_AINTC_FIQ_REG1 0x04
  16. #define DAVINCI_AINTC_IRQ_REG0 0x08
  17. #define DAVINCI_AINTC_IRQ_REG1 0x0c
  18. #define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
  19. #define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
  20. #define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
  21. #define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
  22. #define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
  23. #define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
  24. #define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
  25. static void __iomem *davinci_aintc_base;
  26. static struct irq_domain *davinci_aintc_irq_domain;
  27. static inline void davinci_aintc_writel(unsigned long value, int offset)
  28. {
  29. writel_relaxed(value, davinci_aintc_base + offset);
  30. }
  31. static inline unsigned long davinci_aintc_readl(int offset)
  32. {
  33. return readl_relaxed(davinci_aintc_base + offset);
  34. }
  35. static __init void
  36. davinci_aintc_setup_gc(void __iomem *base,
  37. unsigned int irq_start, unsigned int num)
  38. {
  39. struct irq_chip_generic *gc;
  40. struct irq_chip_type *ct;
  41. gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
  42. gc->reg_base = base;
  43. gc->irq_base = irq_start;
  44. ct = gc->chip_types;
  45. ct->chip.irq_ack = irq_gc_ack_set_bit;
  46. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  47. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  48. ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
  49. ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
  50. irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  51. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  52. }
  53. static asmlinkage void __exception_irq_entry
  54. davinci_aintc_handle_irq(struct pt_regs *regs)
  55. {
  56. int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
  57. /*
  58. * Use the formula for entry vector index generation from section
  59. * 8.3.3 of the manual.
  60. */
  61. irqnr >>= 2;
  62. irqnr -= 1;
  63. handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs);
  64. }
  65. /* ARM Interrupt Controller Initialization */
  66. void __init davinci_aintc_init(const struct davinci_aintc_config *config)
  67. {
  68. unsigned int irq_off, reg_off, prio, shift;
  69. void __iomem *req;
  70. int ret, irq_base;
  71. const u8 *prios;
  72. req = request_mem_region(config->reg.start,
  73. resource_size(&config->reg),
  74. "davinci-cp-intc");
  75. if (!req) {
  76. pr_err("%s: register range busy\n", __func__);
  77. return;
  78. }
  79. davinci_aintc_base = ioremap(config->reg.start,
  80. resource_size(&config->reg));
  81. if (!davinci_aintc_base) {
  82. pr_err("%s: unable to ioremap register range\n", __func__);
  83. return;
  84. }
  85. /* Clear all interrupt requests */
  86. davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
  87. davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
  88. davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
  89. davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
  90. /* Disable all interrupts */
  91. davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
  92. davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
  93. /* Interrupts disabled immediately, IRQ entry reflects all */
  94. davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
  95. /* we don't use the hardware vector table, just its entry addresses */
  96. davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
  97. /* Clear all interrupt requests */
  98. davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
  99. davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
  100. davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
  101. davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
  102. prios = config->prios;
  103. for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
  104. reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
  105. for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
  106. prio |= (*prios & 0x07) << shift;
  107. davinci_aintc_writel(prio, reg_off);
  108. }
  109. irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
  110. if (irq_base < 0) {
  111. pr_err("%s: unable to allocate interrupt descriptors: %d\n",
  112. __func__, irq_base);
  113. return;
  114. }
  115. davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
  116. config->num_irqs, irq_base, 0,
  117. &irq_domain_simple_ops, NULL);
  118. if (!davinci_aintc_irq_domain) {
  119. pr_err("%s: unable to create interrupt domain\n", __func__);
  120. return;
  121. }
  122. ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
  123. "AINTC", handle_edge_irq,
  124. IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
  125. if (ret) {
  126. pr_err("%s: unable to allocate generic irq chips for domain\n",
  127. __func__);
  128. return;
  129. }
  130. for (irq_off = 0, reg_off = 0;
  131. irq_off < config->num_irqs;
  132. irq_off += 32, reg_off += 0x04)
  133. davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
  134. irq_base + irq_off, 32);
  135. set_handle_irq(davinci_aintc_handle_irq);
  136. }