irq-csky-apb-intc.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
  3. #include <linux/kernel.h>
  4. #include <linux/init.h>
  5. #include <linux/of.h>
  6. #include <linux/of_address.h>
  7. #include <linux/module.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/irq.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <asm/irq.h>
  14. #define INTC_IRQS 64
  15. #define CK_INTC_ICR 0x00
  16. #define CK_INTC_PEN31_00 0x14
  17. #define CK_INTC_PEN63_32 0x2c
  18. #define CK_INTC_NEN31_00 0x10
  19. #define CK_INTC_NEN63_32 0x28
  20. #define CK_INTC_SOURCE 0x40
  21. #define CK_INTC_DUAL_BASE 0x100
  22. #define GX_INTC_PEN31_00 0x00
  23. #define GX_INTC_PEN63_32 0x04
  24. #define GX_INTC_NEN31_00 0x40
  25. #define GX_INTC_NEN63_32 0x44
  26. #define GX_INTC_NMASK31_00 0x50
  27. #define GX_INTC_NMASK63_32 0x54
  28. #define GX_INTC_SOURCE 0x60
  29. static void __iomem *reg_base;
  30. static struct irq_domain *root_domain;
  31. static int nr_irq = INTC_IRQS;
  32. /*
  33. * When controller support pulse signal, the PEN_reg will hold on signal
  34. * without software trigger.
  35. *
  36. * So, to support pulse signal we need to clear IFR_reg and the address of
  37. * IFR_offset is NEN_offset - 8.
  38. */
  39. static void irq_ck_mask_set_bit(struct irq_data *d)
  40. {
  41. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  42. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  43. unsigned long ifr = ct->regs.mask - 8;
  44. u32 mask = d->mask;
  45. irq_gc_lock(gc);
  46. *ct->mask_cache |= mask;
  47. irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
  48. irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
  49. irq_gc_unlock(gc);
  50. }
  51. static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base,
  52. u32 mask_reg, u32 irq_base)
  53. {
  54. struct irq_chip_generic *gc;
  55. gc = irq_get_domain_generic_chip(root_domain, irq_base);
  56. gc->reg_base = reg_base;
  57. gc->chip_types[0].regs.mask = mask_reg;
  58. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  59. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  60. if (of_find_property(node, "csky,support-pulse-signal", NULL))
  61. gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit;
  62. }
  63. static inline u32 build_channel_val(u32 idx, u32 magic)
  64. {
  65. u32 res;
  66. /*
  67. * Set the same index for each channel
  68. */
  69. res = idx | (idx << 8) | (idx << 16) | (idx << 24);
  70. /*
  71. * Set the channel magic number in descending order.
  72. * The magic is 0x00010203 for ck-intc
  73. * The magic is 0x03020100 for gx6605s-intc
  74. */
  75. return res | magic;
  76. }
  77. static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr)
  78. {
  79. u32 i;
  80. /* Setup 64 channel slots */
  81. for (i = 0; i < INTC_IRQS; i += 4)
  82. writel(build_channel_val(i, magic), reg_addr + i);
  83. }
  84. static int __init
  85. ck_intc_init_comm(struct device_node *node, struct device_node *parent)
  86. {
  87. int ret;
  88. if (parent) {
  89. pr_err("C-SKY Intc not a root irq controller\n");
  90. return -EINVAL;
  91. }
  92. reg_base = of_iomap(node, 0);
  93. if (!reg_base) {
  94. pr_err("C-SKY Intc unable to map: %p.\n", node);
  95. return -EINVAL;
  96. }
  97. root_domain = irq_domain_add_linear(node, nr_irq,
  98. &irq_generic_chip_ops, NULL);
  99. if (!root_domain) {
  100. pr_err("C-SKY Intc irq_domain_add failed.\n");
  101. return -ENOMEM;
  102. }
  103. ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
  104. "csky_intc", handle_level_irq,
  105. IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0, 0);
  106. if (ret) {
  107. pr_err("C-SKY Intc irq_alloc_gc failed.\n");
  108. return -ENOMEM;
  109. }
  110. return 0;
  111. }
  112. static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq,
  113. u32 irq_base)
  114. {
  115. if (hwirq == 0)
  116. return 0;
  117. handle_domain_irq(root_domain, irq_base + __fls(hwirq), regs);
  118. return 1;
  119. }
  120. /* gx6605s 64 irqs interrupt controller */
  121. static void gx_irq_handler(struct pt_regs *regs)
  122. {
  123. bool ret;
  124. retry:
  125. ret = handle_irq_perbit(regs,
  126. readl(reg_base + GX_INTC_PEN63_32), 32);
  127. if (ret)
  128. goto retry;
  129. ret = handle_irq_perbit(regs,
  130. readl(reg_base + GX_INTC_PEN31_00), 0);
  131. if (ret)
  132. goto retry;
  133. }
  134. static int __init
  135. gx_intc_init(struct device_node *node, struct device_node *parent)
  136. {
  137. int ret;
  138. ret = ck_intc_init_comm(node, parent);
  139. if (ret)
  140. return ret;
  141. /*
  142. * Initial enable reg to disable all interrupts
  143. */
  144. writel(0x0, reg_base + GX_INTC_NEN31_00);
  145. writel(0x0, reg_base + GX_INTC_NEN63_32);
  146. /*
  147. * Initial mask reg with all unmasked, because we only use enalbe reg
  148. */
  149. writel(0x0, reg_base + GX_INTC_NMASK31_00);
  150. writel(0x0, reg_base + GX_INTC_NMASK63_32);
  151. setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE);
  152. ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0);
  153. ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32);
  154. set_handle_irq(gx_irq_handler);
  155. return 0;
  156. }
  157. IRQCHIP_DECLARE(csky_gx6605s_intc, "csky,gx6605s-intc", gx_intc_init);
  158. /*
  159. * C-SKY simple 64 irqs interrupt controller, dual-together could support 128
  160. * irqs.
  161. */
  162. static void ck_irq_handler(struct pt_regs *regs)
  163. {
  164. bool ret;
  165. void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00;
  166. void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32;
  167. retry:
  168. /* handle 0 - 63 irqs */
  169. ret = handle_irq_perbit(regs, readl(reg_pen_hi), 32);
  170. if (ret)
  171. goto retry;
  172. ret = handle_irq_perbit(regs, readl(reg_pen_lo), 0);
  173. if (ret)
  174. goto retry;
  175. if (nr_irq == INTC_IRQS)
  176. return;
  177. /* handle 64 - 127 irqs */
  178. ret = handle_irq_perbit(regs,
  179. readl(reg_pen_hi + CK_INTC_DUAL_BASE), 96);
  180. if (ret)
  181. goto retry;
  182. ret = handle_irq_perbit(regs,
  183. readl(reg_pen_lo + CK_INTC_DUAL_BASE), 64);
  184. if (ret)
  185. goto retry;
  186. }
  187. static int __init
  188. ck_intc_init(struct device_node *node, struct device_node *parent)
  189. {
  190. int ret;
  191. ret = ck_intc_init_comm(node, parent);
  192. if (ret)
  193. return ret;
  194. /* Initial enable reg to disable all interrupts */
  195. writel(0, reg_base + CK_INTC_NEN31_00);
  196. writel(0, reg_base + CK_INTC_NEN63_32);
  197. /* Enable irq intc */
  198. writel(BIT(31), reg_base + CK_INTC_ICR);
  199. ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0);
  200. ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32);
  201. setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE);
  202. set_handle_irq(ck_irq_handler);
  203. return 0;
  204. }
  205. IRQCHIP_DECLARE(ck_intc, "csky,apb-intc", ck_intc_init);
  206. static int __init
  207. ck_dual_intc_init(struct device_node *node, struct device_node *parent)
  208. {
  209. int ret;
  210. /* dual-apb-intc up to 128 irq sources*/
  211. nr_irq = INTC_IRQS * 2;
  212. ret = ck_intc_init(node, parent);
  213. if (ret)
  214. return ret;
  215. /* Initial enable reg to disable all interrupts */
  216. writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE);
  217. writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE);
  218. ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64);
  219. ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96);
  220. setup_irq_channel(0x00010203,
  221. reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE);
  222. return 0;
  223. }
  224. IRQCHIP_DECLARE(ck_dual_intc, "csky,dual-apb-intc", ck_dual_intc_init);