irq-crossbar.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/irqchip/irq-crossbar.c
  4. *
  5. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  6. * Author: Sricharan R <r.sricharan@ti.com>
  7. */
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/slab.h>
  15. #define IRQ_FREE -1
  16. #define IRQ_RESERVED -2
  17. #define IRQ_SKIP -3
  18. #define GIC_IRQ_START 32
  19. /**
  20. * struct crossbar_device - crossbar device description
  21. * @lock: spinlock serializing access to @irq_map
  22. * @int_max: maximum number of supported interrupts
  23. * @safe_map: safe default value to initialize the crossbar
  24. * @max_crossbar_sources: Maximum number of crossbar sources
  25. * @irq_map: array of interrupts to crossbar number mapping
  26. * @crossbar_base: crossbar base address
  27. * @register_offsets: offsets for each irq number
  28. * @write: register write function pointer
  29. */
  30. struct crossbar_device {
  31. raw_spinlock_t lock;
  32. uint int_max;
  33. uint safe_map;
  34. uint max_crossbar_sources;
  35. uint *irq_map;
  36. void __iomem *crossbar_base;
  37. int *register_offsets;
  38. void (*write)(int, int);
  39. };
  40. static struct crossbar_device *cb;
  41. static void crossbar_writel(int irq_no, int cb_no)
  42. {
  43. writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  44. }
  45. static void crossbar_writew(int irq_no, int cb_no)
  46. {
  47. writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  48. }
  49. static void crossbar_writeb(int irq_no, int cb_no)
  50. {
  51. writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  52. }
  53. static struct irq_chip crossbar_chip = {
  54. .name = "CBAR",
  55. .irq_eoi = irq_chip_eoi_parent,
  56. .irq_mask = irq_chip_mask_parent,
  57. .irq_unmask = irq_chip_unmask_parent,
  58. .irq_retrigger = irq_chip_retrigger_hierarchy,
  59. .irq_set_type = irq_chip_set_type_parent,
  60. .flags = IRQCHIP_MASK_ON_SUSPEND |
  61. IRQCHIP_SKIP_SET_WAKE,
  62. #ifdef CONFIG_SMP
  63. .irq_set_affinity = irq_chip_set_affinity_parent,
  64. #endif
  65. };
  66. static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
  67. irq_hw_number_t hwirq)
  68. {
  69. struct irq_fwspec fwspec;
  70. int i;
  71. int err;
  72. if (!irq_domain_get_of_node(domain->parent))
  73. return -EINVAL;
  74. raw_spin_lock(&cb->lock);
  75. for (i = cb->int_max - 1; i >= 0; i--) {
  76. if (cb->irq_map[i] == IRQ_FREE) {
  77. cb->irq_map[i] = hwirq;
  78. break;
  79. }
  80. }
  81. raw_spin_unlock(&cb->lock);
  82. if (i < 0)
  83. return -ENODEV;
  84. fwspec.fwnode = domain->parent->fwnode;
  85. fwspec.param_count = 3;
  86. fwspec.param[0] = 0; /* SPI */
  87. fwspec.param[1] = i;
  88. fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
  89. err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  90. if (err)
  91. cb->irq_map[i] = IRQ_FREE;
  92. else
  93. cb->write(i, hwirq);
  94. return err;
  95. }
  96. static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
  97. unsigned int nr_irqs, void *data)
  98. {
  99. struct irq_fwspec *fwspec = data;
  100. irq_hw_number_t hwirq;
  101. int i;
  102. if (fwspec->param_count != 3)
  103. return -EINVAL; /* Not GIC compliant */
  104. if (fwspec->param[0] != 0)
  105. return -EINVAL; /* No PPI should point to this domain */
  106. hwirq = fwspec->param[1];
  107. if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
  108. return -EINVAL; /* Can't deal with this */
  109. for (i = 0; i < nr_irqs; i++) {
  110. int err = allocate_gic_irq(d, virq + i, hwirq + i);
  111. if (err)
  112. return err;
  113. irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
  114. &crossbar_chip, NULL);
  115. }
  116. return 0;
  117. }
  118. /**
  119. * crossbar_domain_free - unmap/free a crossbar<->irq connection
  120. * @domain: domain of irq to unmap
  121. * @virq: virq number
  122. * @nr_irqs: number of irqs to free
  123. *
  124. * We do not maintain a use count of total number of map/unmap
  125. * calls for a particular irq to find out if a irq can be really
  126. * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
  127. * after which irq is anyways unusable. So an explicit map has to be called
  128. * after that.
  129. */
  130. static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
  131. unsigned int nr_irqs)
  132. {
  133. int i;
  134. raw_spin_lock(&cb->lock);
  135. for (i = 0; i < nr_irqs; i++) {
  136. struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
  137. irq_domain_reset_irq_data(d);
  138. cb->irq_map[d->hwirq] = IRQ_FREE;
  139. cb->write(d->hwirq, cb->safe_map);
  140. }
  141. raw_spin_unlock(&cb->lock);
  142. }
  143. static int crossbar_domain_translate(struct irq_domain *d,
  144. struct irq_fwspec *fwspec,
  145. unsigned long *hwirq,
  146. unsigned int *type)
  147. {
  148. if (is_of_node(fwspec->fwnode)) {
  149. if (fwspec->param_count != 3)
  150. return -EINVAL;
  151. /* No PPI should point to this domain */
  152. if (fwspec->param[0] != 0)
  153. return -EINVAL;
  154. *hwirq = fwspec->param[1];
  155. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  156. return 0;
  157. }
  158. return -EINVAL;
  159. }
  160. static const struct irq_domain_ops crossbar_domain_ops = {
  161. .alloc = crossbar_domain_alloc,
  162. .free = crossbar_domain_free,
  163. .translate = crossbar_domain_translate,
  164. };
  165. static int __init crossbar_of_init(struct device_node *node)
  166. {
  167. u32 max = 0, entry, reg_size;
  168. int i, size, reserved = 0;
  169. const __be32 *irqsr;
  170. int ret = -ENOMEM;
  171. cb = kzalloc(sizeof(*cb), GFP_KERNEL);
  172. if (!cb)
  173. return ret;
  174. cb->crossbar_base = of_iomap(node, 0);
  175. if (!cb->crossbar_base)
  176. goto err_cb;
  177. of_property_read_u32(node, "ti,max-crossbar-sources",
  178. &cb->max_crossbar_sources);
  179. if (!cb->max_crossbar_sources) {
  180. pr_err("missing 'ti,max-crossbar-sources' property\n");
  181. ret = -EINVAL;
  182. goto err_base;
  183. }
  184. of_property_read_u32(node, "ti,max-irqs", &max);
  185. if (!max) {
  186. pr_err("missing 'ti,max-irqs' property\n");
  187. ret = -EINVAL;
  188. goto err_base;
  189. }
  190. cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
  191. if (!cb->irq_map)
  192. goto err_base;
  193. cb->int_max = max;
  194. for (i = 0; i < max; i++)
  195. cb->irq_map[i] = IRQ_FREE;
  196. /* Get and mark reserved irqs */
  197. irqsr = of_get_property(node, "ti,irqs-reserved", &size);
  198. if (irqsr) {
  199. size /= sizeof(__be32);
  200. for (i = 0; i < size; i++) {
  201. of_property_read_u32_index(node,
  202. "ti,irqs-reserved",
  203. i, &entry);
  204. if (entry >= max) {
  205. pr_err("Invalid reserved entry\n");
  206. ret = -EINVAL;
  207. goto err_irq_map;
  208. }
  209. cb->irq_map[entry] = IRQ_RESERVED;
  210. }
  211. }
  212. /* Skip irqs hardwired to bypass the crossbar */
  213. irqsr = of_get_property(node, "ti,irqs-skip", &size);
  214. if (irqsr) {
  215. size /= sizeof(__be32);
  216. for (i = 0; i < size; i++) {
  217. of_property_read_u32_index(node,
  218. "ti,irqs-skip",
  219. i, &entry);
  220. if (entry >= max) {
  221. pr_err("Invalid skip entry\n");
  222. ret = -EINVAL;
  223. goto err_irq_map;
  224. }
  225. cb->irq_map[entry] = IRQ_SKIP;
  226. }
  227. }
  228. cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
  229. if (!cb->register_offsets)
  230. goto err_irq_map;
  231. of_property_read_u32(node, "ti,reg-size", &reg_size);
  232. switch (reg_size) {
  233. case 1:
  234. cb->write = crossbar_writeb;
  235. break;
  236. case 2:
  237. cb->write = crossbar_writew;
  238. break;
  239. case 4:
  240. cb->write = crossbar_writel;
  241. break;
  242. default:
  243. pr_err("Invalid reg-size property\n");
  244. ret = -EINVAL;
  245. goto err_reg_offset;
  246. break;
  247. }
  248. /*
  249. * Register offsets are not linear because of the
  250. * reserved irqs. so find and store the offsets once.
  251. */
  252. for (i = 0; i < max; i++) {
  253. if (cb->irq_map[i] == IRQ_RESERVED)
  254. continue;
  255. cb->register_offsets[i] = reserved;
  256. reserved += reg_size;
  257. }
  258. of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
  259. /* Initialize the crossbar with safe map to start with */
  260. for (i = 0; i < max; i++) {
  261. if (cb->irq_map[i] == IRQ_RESERVED ||
  262. cb->irq_map[i] == IRQ_SKIP)
  263. continue;
  264. cb->write(i, cb->safe_map);
  265. }
  266. raw_spin_lock_init(&cb->lock);
  267. return 0;
  268. err_reg_offset:
  269. kfree(cb->register_offsets);
  270. err_irq_map:
  271. kfree(cb->irq_map);
  272. err_base:
  273. iounmap(cb->crossbar_base);
  274. err_cb:
  275. kfree(cb);
  276. cb = NULL;
  277. return ret;
  278. }
  279. static int __init irqcrossbar_init(struct device_node *node,
  280. struct device_node *parent)
  281. {
  282. struct irq_domain *parent_domain, *domain;
  283. int err;
  284. if (!parent) {
  285. pr_err("%pOF: no parent, giving up\n", node);
  286. return -ENODEV;
  287. }
  288. parent_domain = irq_find_host(parent);
  289. if (!parent_domain) {
  290. pr_err("%pOF: unable to obtain parent domain\n", node);
  291. return -ENXIO;
  292. }
  293. err = crossbar_of_init(node);
  294. if (err)
  295. return err;
  296. domain = irq_domain_add_hierarchy(parent_domain, 0,
  297. cb->max_crossbar_sources,
  298. node, &crossbar_domain_ops,
  299. NULL);
  300. if (!domain) {
  301. pr_err("%pOF: failed to allocated domain\n", node);
  302. return -ENOMEM;
  303. }
  304. return 0;
  305. }
  306. IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);