irq-clps711x.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * CLPS711X IRQ driver
  4. *
  5. * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/slab.h>
  14. #include <asm/exception.h>
  15. #include <asm/mach/irq.h>
  16. #define CLPS711X_INTSR1 (0x0240)
  17. #define CLPS711X_INTMR1 (0x0280)
  18. #define CLPS711X_BLEOI (0x0600)
  19. #define CLPS711X_MCEOI (0x0640)
  20. #define CLPS711X_TEOI (0x0680)
  21. #define CLPS711X_TC1EOI (0x06c0)
  22. #define CLPS711X_TC2EOI (0x0700)
  23. #define CLPS711X_RTCEOI (0x0740)
  24. #define CLPS711X_UMSEOI (0x0780)
  25. #define CLPS711X_COEOI (0x07c0)
  26. #define CLPS711X_INTSR2 (0x1240)
  27. #define CLPS711X_INTMR2 (0x1280)
  28. #define CLPS711X_SRXEOF (0x1600)
  29. #define CLPS711X_KBDEOI (0x1700)
  30. #define CLPS711X_INTSR3 (0x2240)
  31. #define CLPS711X_INTMR3 (0x2280)
  32. static const struct {
  33. #define CLPS711X_FLAG_EN (1 << 0)
  34. #define CLPS711X_FLAG_FIQ (1 << 1)
  35. unsigned int flags;
  36. phys_addr_t eoi;
  37. } clps711x_irqs[] = {
  38. [1] = { CLPS711X_FLAG_FIQ, CLPS711X_BLEOI, },
  39. [3] = { CLPS711X_FLAG_FIQ, CLPS711X_MCEOI, },
  40. [4] = { CLPS711X_FLAG_EN, CLPS711X_COEOI, },
  41. [5] = { CLPS711X_FLAG_EN, },
  42. [6] = { CLPS711X_FLAG_EN, },
  43. [7] = { CLPS711X_FLAG_EN, },
  44. [8] = { CLPS711X_FLAG_EN, CLPS711X_TC1EOI, },
  45. [9] = { CLPS711X_FLAG_EN, CLPS711X_TC2EOI, },
  46. [10] = { CLPS711X_FLAG_EN, CLPS711X_RTCEOI, },
  47. [11] = { CLPS711X_FLAG_EN, CLPS711X_TEOI, },
  48. [12] = { CLPS711X_FLAG_EN, },
  49. [13] = { CLPS711X_FLAG_EN, },
  50. [14] = { CLPS711X_FLAG_EN, CLPS711X_UMSEOI, },
  51. [15] = { CLPS711X_FLAG_EN, CLPS711X_SRXEOF, },
  52. [16] = { CLPS711X_FLAG_EN, CLPS711X_KBDEOI, },
  53. [17] = { CLPS711X_FLAG_EN, },
  54. [18] = { CLPS711X_FLAG_EN, },
  55. [28] = { CLPS711X_FLAG_EN, },
  56. [29] = { CLPS711X_FLAG_EN, },
  57. [32] = { CLPS711X_FLAG_FIQ, },
  58. };
  59. static struct {
  60. void __iomem *base;
  61. void __iomem *intmr[3];
  62. void __iomem *intsr[3];
  63. struct irq_domain *domain;
  64. struct irq_domain_ops ops;
  65. } *clps711x_intc;
  66. static asmlinkage void __exception_irq_entry clps711x_irqh(struct pt_regs *regs)
  67. {
  68. u32 irqstat;
  69. do {
  70. irqstat = readw_relaxed(clps711x_intc->intmr[0]) &
  71. readw_relaxed(clps711x_intc->intsr[0]);
  72. if (irqstat)
  73. handle_domain_irq(clps711x_intc->domain,
  74. fls(irqstat) - 1, regs);
  75. irqstat = readw_relaxed(clps711x_intc->intmr[1]) &
  76. readw_relaxed(clps711x_intc->intsr[1]);
  77. if (irqstat)
  78. handle_domain_irq(clps711x_intc->domain,
  79. fls(irqstat) - 1 + 16, regs);
  80. } while (irqstat);
  81. }
  82. static void clps711x_intc_eoi(struct irq_data *d)
  83. {
  84. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  85. writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi);
  86. }
  87. static void clps711x_intc_mask(struct irq_data *d)
  88. {
  89. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  90. void __iomem *intmr = clps711x_intc->intmr[hwirq / 16];
  91. u32 tmp;
  92. tmp = readl_relaxed(intmr);
  93. tmp &= ~(1 << (hwirq % 16));
  94. writel_relaxed(tmp, intmr);
  95. }
  96. static void clps711x_intc_unmask(struct irq_data *d)
  97. {
  98. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  99. void __iomem *intmr = clps711x_intc->intmr[hwirq / 16];
  100. u32 tmp;
  101. tmp = readl_relaxed(intmr);
  102. tmp |= 1 << (hwirq % 16);
  103. writel_relaxed(tmp, intmr);
  104. }
  105. static struct irq_chip clps711x_intc_chip = {
  106. .name = "clps711x-intc",
  107. .irq_eoi = clps711x_intc_eoi,
  108. .irq_mask = clps711x_intc_mask,
  109. .irq_unmask = clps711x_intc_unmask,
  110. };
  111. static int __init clps711x_intc_irq_map(struct irq_domain *h, unsigned int virq,
  112. irq_hw_number_t hw)
  113. {
  114. irq_flow_handler_t handler = handle_level_irq;
  115. unsigned int flags = 0;
  116. if (!clps711x_irqs[hw].flags)
  117. return 0;
  118. if (clps711x_irqs[hw].flags & CLPS711X_FLAG_FIQ) {
  119. handler = handle_bad_irq;
  120. flags |= IRQ_NOAUTOEN;
  121. } else if (clps711x_irqs[hw].eoi) {
  122. handler = handle_fasteoi_irq;
  123. }
  124. /* Clear down pending interrupt */
  125. if (clps711x_irqs[hw].eoi)
  126. writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi);
  127. irq_set_chip_and_handler(virq, &clps711x_intc_chip, handler);
  128. irq_modify_status(virq, IRQ_NOPROBE, flags);
  129. return 0;
  130. }
  131. static int __init _clps711x_intc_init(struct device_node *np,
  132. phys_addr_t base, resource_size_t size)
  133. {
  134. int err;
  135. clps711x_intc = kzalloc(sizeof(*clps711x_intc), GFP_KERNEL);
  136. if (!clps711x_intc)
  137. return -ENOMEM;
  138. clps711x_intc->base = ioremap(base, size);
  139. if (!clps711x_intc->base) {
  140. err = -ENOMEM;
  141. goto out_kfree;
  142. }
  143. clps711x_intc->intsr[0] = clps711x_intc->base + CLPS711X_INTSR1;
  144. clps711x_intc->intmr[0] = clps711x_intc->base + CLPS711X_INTMR1;
  145. clps711x_intc->intsr[1] = clps711x_intc->base + CLPS711X_INTSR2;
  146. clps711x_intc->intmr[1] = clps711x_intc->base + CLPS711X_INTMR2;
  147. clps711x_intc->intsr[2] = clps711x_intc->base + CLPS711X_INTSR3;
  148. clps711x_intc->intmr[2] = clps711x_intc->base + CLPS711X_INTMR3;
  149. /* Mask all interrupts */
  150. writel_relaxed(0, clps711x_intc->intmr[0]);
  151. writel_relaxed(0, clps711x_intc->intmr[1]);
  152. writel_relaxed(0, clps711x_intc->intmr[2]);
  153. err = irq_alloc_descs(-1, 0, ARRAY_SIZE(clps711x_irqs), numa_node_id());
  154. if (err < 0)
  155. goto out_iounmap;
  156. clps711x_intc->ops.map = clps711x_intc_irq_map;
  157. clps711x_intc->ops.xlate = irq_domain_xlate_onecell;
  158. clps711x_intc->domain =
  159. irq_domain_add_legacy(np, ARRAY_SIZE(clps711x_irqs),
  160. 0, 0, &clps711x_intc->ops, NULL);
  161. if (!clps711x_intc->domain) {
  162. err = -ENOMEM;
  163. goto out_irqfree;
  164. }
  165. irq_set_default_host(clps711x_intc->domain);
  166. set_handle_irq(clps711x_irqh);
  167. #ifdef CONFIG_FIQ
  168. init_FIQ(0);
  169. #endif
  170. return 0;
  171. out_irqfree:
  172. irq_free_descs(0, ARRAY_SIZE(clps711x_irqs));
  173. out_iounmap:
  174. iounmap(clps711x_intc->base);
  175. out_kfree:
  176. kfree(clps711x_intc);
  177. return err;
  178. }
  179. void __init clps711x_intc_init(phys_addr_t base, resource_size_t size)
  180. {
  181. BUG_ON(_clps711x_intc_init(NULL, base, size));
  182. }
  183. #ifdef CONFIG_IRQCHIP
  184. static int __init clps711x_intc_init_dt(struct device_node *np,
  185. struct device_node *parent)
  186. {
  187. struct resource res;
  188. int err;
  189. err = of_address_to_resource(np, 0, &res);
  190. if (err)
  191. return err;
  192. return _clps711x_intc_init(np, res.start, resource_size(&res));
  193. }
  194. IRQCHIP_DECLARE(clps711x, "cirrus,ep7209-intc", clps711x_intc_init_dt);
  195. #endif