irq-brcmstb-l2.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
  4. *
  5. * Copyright (C) 2014-2017 Broadcom
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/init.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/of.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/io.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/irqchip/chained_irq.h>
  23. struct brcmstb_intc_init_params {
  24. irq_flow_handler_t handler;
  25. int cpu_status;
  26. int cpu_clear;
  27. int cpu_mask_status;
  28. int cpu_mask_set;
  29. int cpu_mask_clear;
  30. };
  31. /* Register offsets in the L2 latched interrupt controller */
  32. static const struct brcmstb_intc_init_params l2_edge_intc_init = {
  33. .handler = handle_edge_irq,
  34. .cpu_status = 0x00,
  35. .cpu_clear = 0x08,
  36. .cpu_mask_status = 0x0c,
  37. .cpu_mask_set = 0x10,
  38. .cpu_mask_clear = 0x14
  39. };
  40. /* Register offsets in the L2 level interrupt controller */
  41. static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
  42. .handler = handle_level_irq,
  43. .cpu_status = 0x00,
  44. .cpu_clear = -1, /* Register not present */
  45. .cpu_mask_status = 0x04,
  46. .cpu_mask_set = 0x08,
  47. .cpu_mask_clear = 0x0C
  48. };
  49. /* L2 intc private data structure */
  50. struct brcmstb_l2_intc_data {
  51. struct irq_domain *domain;
  52. struct irq_chip_generic *gc;
  53. int status_offset;
  54. int mask_offset;
  55. bool can_wake;
  56. u32 saved_mask; /* for suspend/resume */
  57. };
  58. /**
  59. * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
  60. * @d: irq_data
  61. *
  62. * Chip has separate enable/disable registers instead of a single mask
  63. * register and pending interrupt is acknowledged by setting a bit.
  64. *
  65. * Note: This function is generic and could easily be added to the
  66. * generic irqchip implementation if there ever becomes a will to do so.
  67. * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
  68. *
  69. * e.g.: https://patchwork.kernel.org/patch/9831047/
  70. */
  71. static void brcmstb_l2_mask_and_ack(struct irq_data *d)
  72. {
  73. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  74. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  75. u32 mask = d->mask;
  76. irq_gc_lock(gc);
  77. irq_reg_writel(gc, mask, ct->regs.disable);
  78. *ct->mask_cache &= ~mask;
  79. irq_reg_writel(gc, mask, ct->regs.ack);
  80. irq_gc_unlock(gc);
  81. }
  82. static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
  83. {
  84. struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
  85. struct irq_chip *chip = irq_desc_get_chip(desc);
  86. unsigned int irq;
  87. u32 status;
  88. chained_irq_enter(chip, desc);
  89. status = irq_reg_readl(b->gc, b->status_offset) &
  90. ~(irq_reg_readl(b->gc, b->mask_offset));
  91. if (status == 0) {
  92. raw_spin_lock(&desc->lock);
  93. handle_bad_irq(desc);
  94. raw_spin_unlock(&desc->lock);
  95. goto out;
  96. }
  97. do {
  98. irq = ffs(status) - 1;
  99. status &= ~(1 << irq);
  100. generic_handle_irq(irq_linear_revmap(b->domain, irq));
  101. } while (status);
  102. out:
  103. chained_irq_exit(chip, desc);
  104. }
  105. static void brcmstb_l2_intc_suspend(struct irq_data *d)
  106. {
  107. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  108. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  109. struct brcmstb_l2_intc_data *b = gc->private;
  110. unsigned long flags;
  111. irq_gc_lock_irqsave(gc, flags);
  112. /* Save the current mask */
  113. b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
  114. if (b->can_wake) {
  115. /* Program the wakeup mask */
  116. irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
  117. irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
  118. }
  119. irq_gc_unlock_irqrestore(gc, flags);
  120. }
  121. static void brcmstb_l2_intc_resume(struct irq_data *d)
  122. {
  123. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  124. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  125. struct brcmstb_l2_intc_data *b = gc->private;
  126. unsigned long flags;
  127. irq_gc_lock_irqsave(gc, flags);
  128. if (ct->chip.irq_ack) {
  129. /* Clear unmasked non-wakeup interrupts */
  130. irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
  131. ct->regs.ack);
  132. }
  133. /* Restore the saved mask */
  134. irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
  135. irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
  136. irq_gc_unlock_irqrestore(gc, flags);
  137. }
  138. static int __init brcmstb_l2_intc_of_init(struct device_node *np,
  139. struct device_node *parent,
  140. const struct brcmstb_intc_init_params
  141. *init_params)
  142. {
  143. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  144. struct brcmstb_l2_intc_data *data;
  145. struct irq_chip_type *ct;
  146. int ret;
  147. unsigned int flags;
  148. int parent_irq;
  149. void __iomem *base;
  150. data = kzalloc(sizeof(*data), GFP_KERNEL);
  151. if (!data)
  152. return -ENOMEM;
  153. base = of_iomap(np, 0);
  154. if (!base) {
  155. pr_err("failed to remap intc L2 registers\n");
  156. ret = -ENOMEM;
  157. goto out_free;
  158. }
  159. /* Disable all interrupts by default */
  160. writel(0xffffffff, base + init_params->cpu_mask_set);
  161. /* Wakeup interrupts may be retained from S5 (cold boot) */
  162. data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
  163. if (!data->can_wake && (init_params->cpu_clear >= 0))
  164. writel(0xffffffff, base + init_params->cpu_clear);
  165. parent_irq = irq_of_parse_and_map(np, 0);
  166. if (!parent_irq) {
  167. pr_err("failed to find parent interrupt\n");
  168. ret = -EINVAL;
  169. goto out_unmap;
  170. }
  171. data->domain = irq_domain_add_linear(np, 32,
  172. &irq_generic_chip_ops, NULL);
  173. if (!data->domain) {
  174. ret = -ENOMEM;
  175. goto out_unmap;
  176. }
  177. /* MIPS chips strapped for BE will automagically configure the
  178. * peripheral registers for CPU-native byte order.
  179. */
  180. flags = 0;
  181. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  182. flags |= IRQ_GC_BE_IO;
  183. /* Allocate a single Generic IRQ chip for this node */
  184. ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
  185. np->full_name, init_params->handler, clr, 0, flags);
  186. if (ret) {
  187. pr_err("failed to allocate generic irq chip\n");
  188. goto out_free_domain;
  189. }
  190. /* Set the IRQ chaining logic */
  191. irq_set_chained_handler_and_data(parent_irq,
  192. brcmstb_l2_intc_irq_handle, data);
  193. data->gc = irq_get_domain_generic_chip(data->domain, 0);
  194. data->gc->reg_base = base;
  195. data->gc->private = data;
  196. data->status_offset = init_params->cpu_status;
  197. data->mask_offset = init_params->cpu_mask_status;
  198. ct = data->gc->chip_types;
  199. if (init_params->cpu_clear >= 0) {
  200. ct->regs.ack = init_params->cpu_clear;
  201. ct->chip.irq_ack = irq_gc_ack_set_bit;
  202. ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
  203. } else {
  204. /* No Ack - but still slightly more efficient to define this */
  205. ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
  206. }
  207. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  208. ct->regs.disable = init_params->cpu_mask_set;
  209. ct->regs.mask = init_params->cpu_mask_status;
  210. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  211. ct->regs.enable = init_params->cpu_mask_clear;
  212. ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
  213. ct->chip.irq_resume = brcmstb_l2_intc_resume;
  214. ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
  215. if (data->can_wake) {
  216. /* This IRQ chip can wake the system, set all child interrupts
  217. * in wake_enabled mask
  218. */
  219. data->gc->wake_enabled = 0xffffffff;
  220. ct->chip.irq_set_wake = irq_gc_set_wake;
  221. enable_irq_wake(parent_irq);
  222. }
  223. pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
  224. return 0;
  225. out_free_domain:
  226. irq_domain_remove(data->domain);
  227. out_unmap:
  228. iounmap(base);
  229. out_free:
  230. kfree(data);
  231. return ret;
  232. }
  233. static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
  234. struct device_node *parent)
  235. {
  236. return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
  237. }
  238. IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
  239. IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
  240. brcmstb_l2_edge_intc_of_init);
  241. IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
  242. brcmstb_l2_edge_intc_of_init);
  243. static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
  244. struct device_node *parent)
  245. {
  246. return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
  247. }
  248. IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
  249. brcmstb_l2_lvl_intc_of_init);