irq-bcm7120-l2.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Broadcom BCM7120 style Level 2 interrupt controller driver
  4. *
  5. * Copyright (C) 2014 Broadcom Corporation
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/init.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/of.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/io.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/reboot.h>
  22. #include <linux/bitops.h>
  23. #include <linux/irqchip.h>
  24. #include <linux/irqchip/chained_irq.h>
  25. /* Register offset in the L2 interrupt controller */
  26. #define IRQEN 0x00
  27. #define IRQSTAT 0x04
  28. #define MAX_WORDS 4
  29. #define MAX_MAPPINGS (MAX_WORDS * 2)
  30. #define IRQS_PER_WORD 32
  31. struct bcm7120_l1_intc_data {
  32. struct bcm7120_l2_intc_data *b;
  33. u32 irq_map_mask[MAX_WORDS];
  34. };
  35. struct bcm7120_l2_intc_data {
  36. unsigned int n_words;
  37. void __iomem *map_base[MAX_MAPPINGS];
  38. void __iomem *pair_base[MAX_WORDS];
  39. int en_offset[MAX_WORDS];
  40. int stat_offset[MAX_WORDS];
  41. struct irq_domain *domain;
  42. bool can_wake;
  43. u32 irq_fwd_mask[MAX_WORDS];
  44. struct bcm7120_l1_intc_data *l1_data;
  45. int num_parent_irqs;
  46. const __be32 *map_mask_prop;
  47. };
  48. static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
  49. {
  50. struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
  51. struct bcm7120_l2_intc_data *b = data->b;
  52. struct irq_chip *chip = irq_desc_get_chip(desc);
  53. unsigned int idx;
  54. chained_irq_enter(chip, desc);
  55. for (idx = 0; idx < b->n_words; idx++) {
  56. int base = idx * IRQS_PER_WORD;
  57. struct irq_chip_generic *gc =
  58. irq_get_domain_generic_chip(b->domain, base);
  59. unsigned long pending;
  60. int hwirq;
  61. irq_gc_lock(gc);
  62. pending = irq_reg_readl(gc, b->stat_offset[idx]) &
  63. gc->mask_cache &
  64. data->irq_map_mask[idx];
  65. irq_gc_unlock(gc);
  66. for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
  67. generic_handle_irq(irq_find_mapping(b->domain,
  68. base + hwirq));
  69. }
  70. }
  71. chained_irq_exit(chip, desc);
  72. }
  73. static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
  74. {
  75. struct bcm7120_l2_intc_data *b = gc->private;
  76. struct irq_chip_type *ct = gc->chip_types;
  77. irq_gc_lock(gc);
  78. if (b->can_wake)
  79. irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
  80. ct->regs.mask);
  81. irq_gc_unlock(gc);
  82. }
  83. static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
  84. {
  85. struct irq_chip_type *ct = gc->chip_types;
  86. /* Restore the saved mask */
  87. irq_gc_lock(gc);
  88. irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
  89. irq_gc_unlock(gc);
  90. }
  91. static int bcm7120_l2_intc_init_one(struct device_node *dn,
  92. struct bcm7120_l2_intc_data *data,
  93. int irq, u32 *valid_mask)
  94. {
  95. struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
  96. int parent_irq;
  97. unsigned int idx;
  98. parent_irq = irq_of_parse_and_map(dn, irq);
  99. if (!parent_irq) {
  100. pr_err("failed to map interrupt %d\n", irq);
  101. return -EINVAL;
  102. }
  103. /* For multiple parent IRQs with multiple words, this looks like:
  104. * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
  105. *
  106. * We need to associate a given parent interrupt with its corresponding
  107. * map_mask in order to mask the status register with it because we
  108. * have the same handler being called for multiple parent interrupts.
  109. *
  110. * This is typically something needed on BCM7xxx (STB chips).
  111. */
  112. for (idx = 0; idx < data->n_words; idx++) {
  113. if (data->map_mask_prop) {
  114. l1_data->irq_map_mask[idx] |=
  115. be32_to_cpup(data->map_mask_prop +
  116. irq * data->n_words + idx);
  117. } else {
  118. l1_data->irq_map_mask[idx] = 0xffffffff;
  119. }
  120. valid_mask[idx] |= l1_data->irq_map_mask[idx];
  121. }
  122. l1_data->b = data;
  123. irq_set_chained_handler_and_data(parent_irq,
  124. bcm7120_l2_intc_irq_handle, l1_data);
  125. if (data->can_wake)
  126. enable_irq_wake(parent_irq);
  127. return 0;
  128. }
  129. static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
  130. struct bcm7120_l2_intc_data *data)
  131. {
  132. int ret;
  133. data->map_base[0] = of_iomap(dn, 0);
  134. if (!data->map_base[0]) {
  135. pr_err("unable to map registers\n");
  136. return -ENOMEM;
  137. }
  138. data->pair_base[0] = data->map_base[0];
  139. data->en_offset[0] = IRQEN;
  140. data->stat_offset[0] = IRQSTAT;
  141. data->n_words = 1;
  142. ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
  143. data->irq_fwd_mask, data->n_words);
  144. if (ret != 0 && ret != -EINVAL) {
  145. /* property exists but has the wrong number of words */
  146. pr_err("invalid brcm,int-fwd-mask property\n");
  147. return -EINVAL;
  148. }
  149. data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
  150. if (!data->map_mask_prop ||
  151. (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
  152. pr_err("invalid brcm,int-map-mask property\n");
  153. return -EINVAL;
  154. }
  155. return 0;
  156. }
  157. static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
  158. struct bcm7120_l2_intc_data *data)
  159. {
  160. unsigned int gc_idx;
  161. for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
  162. unsigned int map_idx = gc_idx * 2;
  163. void __iomem *en = of_iomap(dn, map_idx + 0);
  164. void __iomem *stat = of_iomap(dn, map_idx + 1);
  165. void __iomem *base = min(en, stat);
  166. data->map_base[map_idx + 0] = en;
  167. data->map_base[map_idx + 1] = stat;
  168. if (!base)
  169. break;
  170. data->pair_base[gc_idx] = base;
  171. data->en_offset[gc_idx] = en - base;
  172. data->stat_offset[gc_idx] = stat - base;
  173. }
  174. if (!gc_idx) {
  175. pr_err("unable to map registers\n");
  176. return -EINVAL;
  177. }
  178. data->n_words = gc_idx;
  179. return 0;
  180. }
  181. static int __init bcm7120_l2_intc_probe(struct device_node *dn,
  182. struct device_node *parent,
  183. int (*iomap_regs_fn)(struct device_node *,
  184. struct bcm7120_l2_intc_data *),
  185. const char *intc_name)
  186. {
  187. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  188. struct bcm7120_l2_intc_data *data;
  189. struct irq_chip_generic *gc;
  190. struct irq_chip_type *ct;
  191. int ret = 0;
  192. unsigned int idx, irq, flags;
  193. u32 valid_mask[MAX_WORDS] = { };
  194. data = kzalloc(sizeof(*data), GFP_KERNEL);
  195. if (!data)
  196. return -ENOMEM;
  197. data->num_parent_irqs = of_irq_count(dn);
  198. if (data->num_parent_irqs <= 0) {
  199. pr_err("invalid number of parent interrupts\n");
  200. ret = -ENOMEM;
  201. goto out_unmap;
  202. }
  203. data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
  204. GFP_KERNEL);
  205. if (!data->l1_data) {
  206. ret = -ENOMEM;
  207. goto out_free_l1_data;
  208. }
  209. ret = iomap_regs_fn(dn, data);
  210. if (ret < 0)
  211. goto out_free_l1_data;
  212. data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
  213. for (irq = 0; irq < data->num_parent_irqs; irq++) {
  214. ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
  215. if (ret)
  216. goto out_free_l1_data;
  217. }
  218. data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
  219. &irq_generic_chip_ops, NULL);
  220. if (!data->domain) {
  221. ret = -ENOMEM;
  222. goto out_free_l1_data;
  223. }
  224. /* MIPS chips strapped for BE will automagically configure the
  225. * peripheral registers for CPU-native byte order.
  226. */
  227. flags = IRQ_GC_INIT_MASK_CACHE;
  228. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  229. flags |= IRQ_GC_BE_IO;
  230. ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
  231. dn->full_name, handle_level_irq, clr, 0, flags);
  232. if (ret) {
  233. pr_err("failed to allocate generic irq chip\n");
  234. goto out_free_domain;
  235. }
  236. for (idx = 0; idx < data->n_words; idx++) {
  237. irq = idx * IRQS_PER_WORD;
  238. gc = irq_get_domain_generic_chip(data->domain, irq);
  239. gc->unused = 0xffffffff & ~valid_mask[idx];
  240. gc->private = data;
  241. ct = gc->chip_types;
  242. gc->reg_base = data->pair_base[idx];
  243. ct->regs.mask = data->en_offset[idx];
  244. /* gc->reg_base is defined and so is gc->writel */
  245. irq_reg_writel(gc, data->irq_fwd_mask[idx],
  246. data->en_offset[idx]);
  247. ct->chip.irq_mask = irq_gc_mask_clr_bit;
  248. ct->chip.irq_unmask = irq_gc_mask_set_bit;
  249. ct->chip.irq_ack = irq_gc_noop;
  250. gc->suspend = bcm7120_l2_intc_suspend;
  251. gc->resume = bcm7120_l2_intc_resume;
  252. /*
  253. * Initialize mask-cache, in case we need it for
  254. * saving/restoring fwd mask even w/o any child interrupts
  255. * installed
  256. */
  257. gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
  258. if (data->can_wake) {
  259. /* This IRQ chip can wake the system, set all
  260. * relevant child interupts in wake_enabled mask
  261. */
  262. gc->wake_enabled = 0xffffffff;
  263. gc->wake_enabled &= ~gc->unused;
  264. ct->chip.irq_set_wake = irq_gc_set_wake;
  265. }
  266. }
  267. pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
  268. intc_name, dn, data->num_parent_irqs);
  269. return 0;
  270. out_free_domain:
  271. irq_domain_remove(data->domain);
  272. out_free_l1_data:
  273. kfree(data->l1_data);
  274. out_unmap:
  275. for (idx = 0; idx < MAX_MAPPINGS; idx++) {
  276. if (data->map_base[idx])
  277. iounmap(data->map_base[idx]);
  278. }
  279. kfree(data);
  280. return ret;
  281. }
  282. static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
  283. struct device_node *parent)
  284. {
  285. return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
  286. "BCM7120 L2");
  287. }
  288. static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
  289. struct device_node *parent)
  290. {
  291. return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
  292. "BCM3380 L2");
  293. }
  294. IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
  295. bcm7120_l2_intc_probe_7120);
  296. IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
  297. bcm7120_l2_intc_probe_3380);