irq-bcm6345-l1.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Broadcom BCM6345 style Level 1 interrupt controller driver
  4. *
  5. * Copyright (C) 2014 Broadcom Corporation
  6. * Copyright 2015 Simon Arlott
  7. *
  8. * This is based on the BCM7038 (which supports SMP) but with a single
  9. * enable register instead of separate mask/set/clear registers.
  10. *
  11. * The BCM3380 has a similar mask/status register layout, but each pair
  12. * of words is at separate locations (and SMP is not supported).
  13. *
  14. * ENABLE/STATUS words are packed next to each other for each CPU:
  15. *
  16. * BCM6368:
  17. * 0x1000_0020: CPU0_W0_ENABLE
  18. * 0x1000_0024: CPU0_W1_ENABLE
  19. * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
  20. * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
  21. * 0x1000_0030: CPU1_W0_ENABLE
  22. * 0x1000_0034: CPU1_W1_ENABLE
  23. * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
  24. * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
  25. *
  26. * BCM63168:
  27. * 0x1000_0020: CPU0_W0_ENABLE
  28. * 0x1000_0024: CPU0_W1_ENABLE
  29. * 0x1000_0028: CPU0_W2_ENABLE
  30. * 0x1000_002c: CPU0_W3_ENABLE
  31. * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
  32. * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
  33. * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
  34. * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
  35. * 0x1000_0040: CPU1_W0_ENABLE
  36. * 0x1000_0044: CPU1_W1_ENABLE
  37. * 0x1000_0048: CPU1_W2_ENABLE
  38. * 0x1000_004c: CPU1_W3_ENABLE
  39. * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
  40. * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
  41. * 0x1000_0058: CPU1_W2_STATUS IRQs 32-63
  42. * 0x1000_005c: CPU1_W3_STATUS IRQs 0-31
  43. *
  44. * IRQs are numbered in CPU native endian order
  45. * (which is big-endian in these examples)
  46. */
  47. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  48. #include <linux/bitops.h>
  49. #include <linux/cpumask.h>
  50. #include <linux/kernel.h>
  51. #include <linux/init.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/io.h>
  54. #include <linux/ioport.h>
  55. #include <linux/irq.h>
  56. #include <linux/irqdomain.h>
  57. #include <linux/module.h>
  58. #include <linux/of.h>
  59. #include <linux/of_irq.h>
  60. #include <linux/of_address.h>
  61. #include <linux/of_platform.h>
  62. #include <linux/platform_device.h>
  63. #include <linux/slab.h>
  64. #include <linux/smp.h>
  65. #include <linux/types.h>
  66. #include <linux/irqchip.h>
  67. #include <linux/irqchip/chained_irq.h>
  68. #define IRQS_PER_WORD 32
  69. #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2)
  70. struct bcm6345_l1_cpu;
  71. struct bcm6345_l1_chip {
  72. raw_spinlock_t lock;
  73. unsigned int n_words;
  74. struct irq_domain *domain;
  75. struct cpumask cpumask;
  76. struct bcm6345_l1_cpu *cpus[NR_CPUS];
  77. };
  78. struct bcm6345_l1_cpu {
  79. void __iomem *map_base;
  80. unsigned int parent_irq;
  81. u32 enable_cache[];
  82. };
  83. static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
  84. unsigned int word)
  85. {
  86. #ifdef __BIG_ENDIAN
  87. return (1 * intc->n_words - word - 1) * sizeof(u32);
  88. #else
  89. return (0 * intc->n_words + word) * sizeof(u32);
  90. #endif
  91. }
  92. static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
  93. unsigned int word)
  94. {
  95. #ifdef __BIG_ENDIAN
  96. return (2 * intc->n_words - word - 1) * sizeof(u32);
  97. #else
  98. return (1 * intc->n_words + word) * sizeof(u32);
  99. #endif
  100. }
  101. static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
  102. struct irq_data *d)
  103. {
  104. return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
  105. }
  106. static void bcm6345_l1_irq_handle(struct irq_desc *desc)
  107. {
  108. struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
  109. struct bcm6345_l1_cpu *cpu;
  110. struct irq_chip *chip = irq_desc_get_chip(desc);
  111. unsigned int idx;
  112. #ifdef CONFIG_SMP
  113. cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
  114. #else
  115. cpu = intc->cpus[0];
  116. #endif
  117. chained_irq_enter(chip, desc);
  118. for (idx = 0; idx < intc->n_words; idx++) {
  119. int base = idx * IRQS_PER_WORD;
  120. unsigned long pending;
  121. irq_hw_number_t hwirq;
  122. unsigned int irq;
  123. pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
  124. pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
  125. for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
  126. irq = irq_linear_revmap(intc->domain, base + hwirq);
  127. if (irq)
  128. generic_handle_irq(irq);
  129. else
  130. spurious_interrupt();
  131. }
  132. }
  133. chained_irq_exit(chip, desc);
  134. }
  135. static inline void __bcm6345_l1_unmask(struct irq_data *d)
  136. {
  137. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  138. u32 word = d->hwirq / IRQS_PER_WORD;
  139. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  140. unsigned int cpu_idx = cpu_for_irq(intc, d);
  141. intc->cpus[cpu_idx]->enable_cache[word] |= mask;
  142. __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
  143. intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
  144. }
  145. static inline void __bcm6345_l1_mask(struct irq_data *d)
  146. {
  147. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  148. u32 word = d->hwirq / IRQS_PER_WORD;
  149. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  150. unsigned int cpu_idx = cpu_for_irq(intc, d);
  151. intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
  152. __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
  153. intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
  154. }
  155. static void bcm6345_l1_unmask(struct irq_data *d)
  156. {
  157. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  158. unsigned long flags;
  159. raw_spin_lock_irqsave(&intc->lock, flags);
  160. __bcm6345_l1_unmask(d);
  161. raw_spin_unlock_irqrestore(&intc->lock, flags);
  162. }
  163. static void bcm6345_l1_mask(struct irq_data *d)
  164. {
  165. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  166. unsigned long flags;
  167. raw_spin_lock_irqsave(&intc->lock, flags);
  168. __bcm6345_l1_mask(d);
  169. raw_spin_unlock_irqrestore(&intc->lock, flags);
  170. }
  171. static int bcm6345_l1_set_affinity(struct irq_data *d,
  172. const struct cpumask *dest,
  173. bool force)
  174. {
  175. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  176. u32 word = d->hwirq / IRQS_PER_WORD;
  177. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  178. unsigned int old_cpu = cpu_for_irq(intc, d);
  179. unsigned int new_cpu;
  180. struct cpumask valid;
  181. unsigned long flags;
  182. bool enabled;
  183. if (!cpumask_and(&valid, &intc->cpumask, dest))
  184. return -EINVAL;
  185. new_cpu = cpumask_any_and(&valid, cpu_online_mask);
  186. if (new_cpu >= nr_cpu_ids)
  187. return -EINVAL;
  188. dest = cpumask_of(new_cpu);
  189. raw_spin_lock_irqsave(&intc->lock, flags);
  190. if (old_cpu != new_cpu) {
  191. enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
  192. if (enabled)
  193. __bcm6345_l1_mask(d);
  194. cpumask_copy(irq_data_get_affinity_mask(d), dest);
  195. if (enabled)
  196. __bcm6345_l1_unmask(d);
  197. } else {
  198. cpumask_copy(irq_data_get_affinity_mask(d), dest);
  199. }
  200. raw_spin_unlock_irqrestore(&intc->lock, flags);
  201. irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
  202. return IRQ_SET_MASK_OK_NOCOPY;
  203. }
  204. static int __init bcm6345_l1_init_one(struct device_node *dn,
  205. unsigned int idx,
  206. struct bcm6345_l1_chip *intc)
  207. {
  208. struct resource res;
  209. resource_size_t sz;
  210. struct bcm6345_l1_cpu *cpu;
  211. unsigned int i, n_words;
  212. if (of_address_to_resource(dn, idx, &res))
  213. return -EINVAL;
  214. sz = resource_size(&res);
  215. n_words = sz / REG_BYTES_PER_IRQ_WORD;
  216. if (!intc->n_words)
  217. intc->n_words = n_words;
  218. else if (intc->n_words != n_words)
  219. return -EINVAL;
  220. cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
  221. GFP_KERNEL);
  222. if (!cpu)
  223. return -ENOMEM;
  224. cpu->map_base = ioremap(res.start, sz);
  225. if (!cpu->map_base)
  226. return -ENOMEM;
  227. for (i = 0; i < n_words; i++) {
  228. cpu->enable_cache[i] = 0;
  229. __raw_writel(0, cpu->map_base + reg_enable(intc, i));
  230. }
  231. cpu->parent_irq = irq_of_parse_and_map(dn, idx);
  232. if (!cpu->parent_irq) {
  233. pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
  234. return -EINVAL;
  235. }
  236. irq_set_chained_handler_and_data(cpu->parent_irq,
  237. bcm6345_l1_irq_handle, intc);
  238. return 0;
  239. }
  240. static struct irq_chip bcm6345_l1_irq_chip = {
  241. .name = "bcm6345-l1",
  242. .irq_mask = bcm6345_l1_mask,
  243. .irq_unmask = bcm6345_l1_unmask,
  244. .irq_set_affinity = bcm6345_l1_set_affinity,
  245. };
  246. static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
  247. irq_hw_number_t hw_irq)
  248. {
  249. irq_set_chip_and_handler(virq,
  250. &bcm6345_l1_irq_chip, handle_percpu_irq);
  251. irq_set_chip_data(virq, d->host_data);
  252. irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
  253. return 0;
  254. }
  255. static const struct irq_domain_ops bcm6345_l1_domain_ops = {
  256. .xlate = irq_domain_xlate_onecell,
  257. .map = bcm6345_l1_map,
  258. };
  259. static int __init bcm6345_l1_of_init(struct device_node *dn,
  260. struct device_node *parent)
  261. {
  262. struct bcm6345_l1_chip *intc;
  263. unsigned int idx;
  264. int ret;
  265. intc = kzalloc(sizeof(*intc), GFP_KERNEL);
  266. if (!intc)
  267. return -ENOMEM;
  268. for_each_possible_cpu(idx) {
  269. ret = bcm6345_l1_init_one(dn, idx, intc);
  270. if (ret)
  271. pr_err("failed to init intc L1 for cpu %d: %d\n",
  272. idx, ret);
  273. else
  274. cpumask_set_cpu(idx, &intc->cpumask);
  275. }
  276. if (!cpumask_weight(&intc->cpumask)) {
  277. ret = -ENODEV;
  278. goto out_free;
  279. }
  280. raw_spin_lock_init(&intc->lock);
  281. intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
  282. &bcm6345_l1_domain_ops,
  283. intc);
  284. if (!intc->domain) {
  285. ret = -ENOMEM;
  286. goto out_unmap;
  287. }
  288. pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
  289. IRQS_PER_WORD * intc->n_words);
  290. for_each_cpu(idx, &intc->cpumask) {
  291. struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
  292. pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx,
  293. cpu->map_base, cpu->parent_irq);
  294. }
  295. return 0;
  296. out_unmap:
  297. for_each_possible_cpu(idx) {
  298. struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
  299. if (cpu) {
  300. if (cpu->map_base)
  301. iounmap(cpu->map_base);
  302. kfree(cpu);
  303. }
  304. }
  305. out_free:
  306. kfree(intc);
  307. return ret;
  308. }
  309. IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);