irq-atmel-aic5.c 11 KB

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  1. /*
  2. * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
  3. *
  4. * Copyright (C) 2004 SAN People
  5. * Copyright (C) 2004 ATMEL
  6. * Copyright (C) Rick Bronson
  7. * Copyright (C) 2014 Free Electrons
  8. *
  9. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/mm.h>
  18. #include <linux/bitmap.h>
  19. #include <linux/types.h>
  20. #include <linux/irq.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/irqdomain.h>
  26. #include <linux/err.h>
  27. #include <linux/slab.h>
  28. #include <linux/io.h>
  29. #include <asm/exception.h>
  30. #include <asm/mach/irq.h>
  31. #include "irq-atmel-aic-common.h"
  32. /* Number of irq lines managed by AIC */
  33. #define NR_AIC5_IRQS 128
  34. #define AT91_AIC5_SSR 0x0
  35. #define AT91_AIC5_INTSEL_MSK (0x7f << 0)
  36. #define AT91_AIC5_SMR 0x4
  37. #define AT91_AIC5_SVR 0x8
  38. #define AT91_AIC5_IVR 0x10
  39. #define AT91_AIC5_FVR 0x14
  40. #define AT91_AIC5_ISR 0x18
  41. #define AT91_AIC5_IPR0 0x20
  42. #define AT91_AIC5_IPR1 0x24
  43. #define AT91_AIC5_IPR2 0x28
  44. #define AT91_AIC5_IPR3 0x2c
  45. #define AT91_AIC5_IMR 0x30
  46. #define AT91_AIC5_CISR 0x34
  47. #define AT91_AIC5_IECR 0x40
  48. #define AT91_AIC5_IDCR 0x44
  49. #define AT91_AIC5_ICCR 0x48
  50. #define AT91_AIC5_ISCR 0x4c
  51. #define AT91_AIC5_EOICR 0x38
  52. #define AT91_AIC5_SPU 0x3c
  53. #define AT91_AIC5_DCR 0x6c
  54. #define AT91_AIC5_FFER 0x50
  55. #define AT91_AIC5_FFDR 0x54
  56. #define AT91_AIC5_FFSR 0x58
  57. static struct irq_domain *aic5_domain;
  58. static asmlinkage void __exception_irq_entry
  59. aic5_handle(struct pt_regs *regs)
  60. {
  61. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);
  62. u32 irqnr;
  63. u32 irqstat;
  64. irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);
  65. irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
  66. if (!irqstat)
  67. irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);
  68. else
  69. handle_domain_irq(aic5_domain, irqnr, regs);
  70. }
  71. static void aic5_mask(struct irq_data *d)
  72. {
  73. struct irq_domain *domain = d->domain;
  74. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  75. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  76. /*
  77. * Disable interrupt on AIC5. We always take the lock of the
  78. * first irq chip as all chips share the same registers.
  79. */
  80. irq_gc_lock(bgc);
  81. irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
  82. irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
  83. gc->mask_cache &= ~d->mask;
  84. irq_gc_unlock(bgc);
  85. }
  86. static void aic5_unmask(struct irq_data *d)
  87. {
  88. struct irq_domain *domain = d->domain;
  89. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  90. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  91. /*
  92. * Enable interrupt on AIC5. We always take the lock of the
  93. * first irq chip as all chips share the same registers.
  94. */
  95. irq_gc_lock(bgc);
  96. irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
  97. irq_reg_writel(gc, 1, AT91_AIC5_IECR);
  98. gc->mask_cache |= d->mask;
  99. irq_gc_unlock(bgc);
  100. }
  101. static int aic5_retrigger(struct irq_data *d)
  102. {
  103. struct irq_domain *domain = d->domain;
  104. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  105. /* Enable interrupt on AIC5 */
  106. irq_gc_lock(bgc);
  107. irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
  108. irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);
  109. irq_gc_unlock(bgc);
  110. return 1;
  111. }
  112. static int aic5_set_type(struct irq_data *d, unsigned type)
  113. {
  114. struct irq_domain *domain = d->domain;
  115. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  116. unsigned int smr;
  117. int ret;
  118. irq_gc_lock(bgc);
  119. irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
  120. smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
  121. ret = aic_common_set_type(d, type, &smr);
  122. if (!ret)
  123. irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
  124. irq_gc_unlock(bgc);
  125. return ret;
  126. }
  127. #ifdef CONFIG_PM
  128. static u32 *smr_cache;
  129. static void aic5_suspend(struct irq_data *d)
  130. {
  131. struct irq_domain *domain = d->domain;
  132. struct irq_domain_chip_generic *dgc = domain->gc;
  133. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  134. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  135. int i;
  136. u32 mask;
  137. if (smr_cache)
  138. for (i = 0; i < domain->revmap_size; i++) {
  139. irq_reg_writel(bgc, i, AT91_AIC5_SSR);
  140. smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);
  141. }
  142. irq_gc_lock(bgc);
  143. for (i = 0; i < dgc->irqs_per_chip; i++) {
  144. mask = 1 << i;
  145. if ((mask & gc->mask_cache) == (mask & gc->wake_active))
  146. continue;
  147. irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
  148. if (mask & gc->wake_active)
  149. irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
  150. else
  151. irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
  152. }
  153. irq_gc_unlock(bgc);
  154. }
  155. static void aic5_resume(struct irq_data *d)
  156. {
  157. struct irq_domain *domain = d->domain;
  158. struct irq_domain_chip_generic *dgc = domain->gc;
  159. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  160. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  161. int i;
  162. u32 mask;
  163. irq_gc_lock(bgc);
  164. if (smr_cache) {
  165. irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);
  166. for (i = 0; i < domain->revmap_size; i++) {
  167. irq_reg_writel(bgc, i, AT91_AIC5_SSR);
  168. irq_reg_writel(bgc, i, AT91_AIC5_SVR);
  169. irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);
  170. }
  171. }
  172. for (i = 0; i < dgc->irqs_per_chip; i++) {
  173. mask = 1 << i;
  174. if (!smr_cache &&
  175. ((mask & gc->mask_cache) == (mask & gc->wake_active)))
  176. continue;
  177. irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
  178. if (mask & gc->mask_cache)
  179. irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
  180. else
  181. irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
  182. }
  183. irq_gc_unlock(bgc);
  184. }
  185. static void aic5_pm_shutdown(struct irq_data *d)
  186. {
  187. struct irq_domain *domain = d->domain;
  188. struct irq_domain_chip_generic *dgc = domain->gc;
  189. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
  190. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  191. int i;
  192. irq_gc_lock(bgc);
  193. for (i = 0; i < dgc->irqs_per_chip; i++) {
  194. irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
  195. irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
  196. irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
  197. }
  198. irq_gc_unlock(bgc);
  199. }
  200. #else
  201. #define aic5_suspend NULL
  202. #define aic5_resume NULL
  203. #define aic5_pm_shutdown NULL
  204. #endif /* CONFIG_PM */
  205. static void __init aic5_hw_init(struct irq_domain *domain)
  206. {
  207. struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
  208. int i;
  209. /*
  210. * Perform 8 End Of Interrupt Command to make sure AIC
  211. * will not Lock out nIRQ
  212. */
  213. for (i = 0; i < 8; i++)
  214. irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
  215. /*
  216. * Spurious Interrupt ID in Spurious Vector Register.
  217. * When there is no current interrupt, the IRQ Vector Register
  218. * reads the value stored in AIC_SPU
  219. */
  220. irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);
  221. /* No debugging in AIC: Debug (Protect) Control Register */
  222. irq_reg_writel(gc, 0, AT91_AIC5_DCR);
  223. /* Disable and clear all interrupts initially */
  224. for (i = 0; i < domain->revmap_size; i++) {
  225. irq_reg_writel(gc, i, AT91_AIC5_SSR);
  226. irq_reg_writel(gc, i, AT91_AIC5_SVR);
  227. irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
  228. irq_reg_writel(gc, 1, AT91_AIC5_ICCR);
  229. }
  230. }
  231. static int aic5_irq_domain_xlate(struct irq_domain *d,
  232. struct device_node *ctrlr,
  233. const u32 *intspec, unsigned int intsize,
  234. irq_hw_number_t *out_hwirq,
  235. unsigned int *out_type)
  236. {
  237. struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);
  238. unsigned long flags;
  239. unsigned smr;
  240. int ret;
  241. if (!bgc)
  242. return -EINVAL;
  243. ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
  244. out_hwirq, out_type);
  245. if (ret)
  246. return ret;
  247. irq_gc_lock_irqsave(bgc, flags);
  248. irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
  249. smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
  250. aic_common_set_priority(intspec[2], &smr);
  251. irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
  252. irq_gc_unlock_irqrestore(bgc, flags);
  253. return ret;
  254. }
  255. static const struct irq_domain_ops aic5_irq_ops = {
  256. .map = irq_map_generic_chip,
  257. .xlate = aic5_irq_domain_xlate,
  258. };
  259. static void __init sama5d3_aic_irq_fixup(void)
  260. {
  261. aic_common_rtc_irq_fixup();
  262. }
  263. static void __init sam9x60_aic_irq_fixup(void)
  264. {
  265. aic_common_rtc_irq_fixup();
  266. aic_common_rtt_irq_fixup();
  267. }
  268. static const struct of_device_id aic5_irq_fixups[] __initconst = {
  269. { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
  270. { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
  271. { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup },
  272. { /* sentinel */ },
  273. };
  274. static int __init aic5_of_init(struct device_node *node,
  275. struct device_node *parent,
  276. int nirqs)
  277. {
  278. struct irq_chip_generic *gc;
  279. struct irq_domain *domain;
  280. int nchips;
  281. int i;
  282. if (nirqs > NR_AIC5_IRQS)
  283. return -EINVAL;
  284. if (aic5_domain)
  285. return -EEXIST;
  286. domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
  287. nirqs, aic5_irq_fixups);
  288. if (IS_ERR(domain))
  289. return PTR_ERR(domain);
  290. aic5_domain = domain;
  291. nchips = aic5_domain->revmap_size / 32;
  292. for (i = 0; i < nchips; i++) {
  293. gc = irq_get_domain_generic_chip(domain, i * 32);
  294. gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
  295. gc->chip_types[0].chip.irq_mask = aic5_mask;
  296. gc->chip_types[0].chip.irq_unmask = aic5_unmask;
  297. gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
  298. gc->chip_types[0].chip.irq_set_type = aic5_set_type;
  299. gc->chip_types[0].chip.irq_suspend = aic5_suspend;
  300. gc->chip_types[0].chip.irq_resume = aic5_resume;
  301. gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
  302. }
  303. aic5_hw_init(domain);
  304. set_handle_irq(aic5_handle);
  305. return 0;
  306. }
  307. #define NR_SAMA5D2_IRQS 77
  308. static int __init sama5d2_aic5_of_init(struct device_node *node,
  309. struct device_node *parent)
  310. {
  311. #ifdef CONFIG_PM
  312. smr_cache = kcalloc(DIV_ROUND_UP(NR_SAMA5D2_IRQS, 32) * 32,
  313. sizeof(*smr_cache), GFP_KERNEL);
  314. if (!smr_cache)
  315. return -ENOMEM;
  316. #endif
  317. return aic5_of_init(node, parent, NR_SAMA5D2_IRQS);
  318. }
  319. IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init);
  320. #define NR_SAMA5D3_IRQS 48
  321. static int __init sama5d3_aic5_of_init(struct device_node *node,
  322. struct device_node *parent)
  323. {
  324. return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
  325. }
  326. IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
  327. #define NR_SAMA5D4_IRQS 68
  328. static int __init sama5d4_aic5_of_init(struct device_node *node,
  329. struct device_node *parent)
  330. {
  331. return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
  332. }
  333. IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
  334. #define NR_SAM9X60_IRQS 50
  335. static int __init sam9x60_aic5_of_init(struct device_node *node,
  336. struct device_node *parent)
  337. {
  338. return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
  339. }
  340. IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);