irq-atmel-aic-common.c 6.0 KB

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  1. /*
  2. * Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
  3. * irq-atmel-aic and irq-atmel-aic5 drivers
  4. *
  5. * Copyright (C) 2004 SAN People
  6. * Copyright (C) 2004 ATMEL
  7. * Copyright (C) Rick Bronson
  8. * Copyright (C) 2014 Free Electrons
  9. *
  10. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/irqdomain.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/slab.h>
  23. #include "irq-atmel-aic-common.h"
  24. #define AT91_AIC_PRIOR GENMASK(2, 0)
  25. #define AT91_AIC_IRQ_MIN_PRIORITY 0
  26. #define AT91_AIC_IRQ_MAX_PRIORITY 7
  27. #define AT91_AIC_SRCTYPE GENMASK(6, 5)
  28. #define AT91_AIC_SRCTYPE_LOW (0 << 5)
  29. #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
  30. #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
  31. #define AT91_AIC_SRCTYPE_RISING (3 << 5)
  32. struct aic_chip_data {
  33. u32 ext_irqs;
  34. };
  35. static void aic_common_shutdown(struct irq_data *d)
  36. {
  37. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  38. ct->chip.irq_mask(d);
  39. }
  40. int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
  41. {
  42. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  43. struct aic_chip_data *aic = gc->private;
  44. unsigned aic_type;
  45. switch (type) {
  46. case IRQ_TYPE_LEVEL_HIGH:
  47. aic_type = AT91_AIC_SRCTYPE_HIGH;
  48. break;
  49. case IRQ_TYPE_EDGE_RISING:
  50. aic_type = AT91_AIC_SRCTYPE_RISING;
  51. break;
  52. case IRQ_TYPE_LEVEL_LOW:
  53. if (!(d->mask & aic->ext_irqs))
  54. return -EINVAL;
  55. aic_type = AT91_AIC_SRCTYPE_LOW;
  56. break;
  57. case IRQ_TYPE_EDGE_FALLING:
  58. if (!(d->mask & aic->ext_irqs))
  59. return -EINVAL;
  60. aic_type = AT91_AIC_SRCTYPE_FALLING;
  61. break;
  62. default:
  63. return -EINVAL;
  64. }
  65. *val &= ~AT91_AIC_SRCTYPE;
  66. *val |= aic_type;
  67. return 0;
  68. }
  69. void aic_common_set_priority(int priority, unsigned *val)
  70. {
  71. *val &= ~AT91_AIC_PRIOR;
  72. *val |= priority;
  73. }
  74. int aic_common_irq_domain_xlate(struct irq_domain *d,
  75. struct device_node *ctrlr,
  76. const u32 *intspec,
  77. unsigned int intsize,
  78. irq_hw_number_t *out_hwirq,
  79. unsigned int *out_type)
  80. {
  81. if (WARN_ON(intsize < 3))
  82. return -EINVAL;
  83. if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
  84. (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
  85. return -EINVAL;
  86. *out_hwirq = intspec[0];
  87. *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
  88. return 0;
  89. }
  90. static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
  91. {
  92. struct device_node *node = irq_domain_get_of_node(domain);
  93. struct irq_chip_generic *gc;
  94. struct aic_chip_data *aic;
  95. struct property *prop;
  96. const __be32 *p;
  97. u32 hwirq;
  98. gc = irq_get_domain_generic_chip(domain, 0);
  99. aic = gc->private;
  100. aic->ext_irqs |= 1;
  101. of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
  102. gc = irq_get_domain_generic_chip(domain, hwirq);
  103. if (!gc) {
  104. pr_warn("AIC: external irq %d >= %d skip it\n",
  105. hwirq, domain->revmap_size);
  106. continue;
  107. }
  108. aic = gc->private;
  109. aic->ext_irqs |= (1 << (hwirq % 32));
  110. }
  111. }
  112. #define AT91_RTC_IDR 0x24
  113. #define AT91_RTC_IMR 0x28
  114. #define AT91_RTC_IRQ_MASK 0x1f
  115. void __init aic_common_rtc_irq_fixup(void)
  116. {
  117. struct device_node *np;
  118. void __iomem *regs;
  119. np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-rtc");
  120. if (!np)
  121. np = of_find_compatible_node(NULL, NULL,
  122. "atmel,at91sam9x5-rtc");
  123. if (!np)
  124. return;
  125. regs = of_iomap(np, 0);
  126. of_node_put(np);
  127. if (!regs)
  128. return;
  129. writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
  130. iounmap(regs);
  131. }
  132. #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
  133. #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
  134. #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
  135. void __init aic_common_rtt_irq_fixup(void)
  136. {
  137. struct device_node *np;
  138. void __iomem *regs;
  139. /*
  140. * The at91sam9263 SoC has 2 instances of the RTT block, hence we
  141. * iterate over the DT to find each occurrence.
  142. */
  143. for_each_compatible_node(np, NULL, "atmel,at91sam9260-rtt") {
  144. regs = of_iomap(np, 0);
  145. if (!regs)
  146. continue;
  147. writel(readl(regs + AT91_RTT_MR) &
  148. ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN),
  149. regs + AT91_RTT_MR);
  150. iounmap(regs);
  151. }
  152. }
  153. static void __init aic_common_irq_fixup(const struct of_device_id *matches)
  154. {
  155. struct device_node *root = of_find_node_by_path("/");
  156. const struct of_device_id *match;
  157. if (!root)
  158. return;
  159. match = of_match_node(matches, root);
  160. if (match) {
  161. void (*fixup)(void) = match->data;
  162. fixup();
  163. }
  164. of_node_put(root);
  165. }
  166. struct irq_domain *__init aic_common_of_init(struct device_node *node,
  167. const struct irq_domain_ops *ops,
  168. const char *name, int nirqs,
  169. const struct of_device_id *matches)
  170. {
  171. struct irq_chip_generic *gc;
  172. struct irq_domain *domain;
  173. struct aic_chip_data *aic;
  174. void __iomem *reg_base;
  175. int nchips;
  176. int ret;
  177. int i;
  178. nchips = DIV_ROUND_UP(nirqs, 32);
  179. reg_base = of_iomap(node, 0);
  180. if (!reg_base)
  181. return ERR_PTR(-ENOMEM);
  182. aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
  183. if (!aic) {
  184. ret = -ENOMEM;
  185. goto err_iounmap;
  186. }
  187. domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
  188. if (!domain) {
  189. ret = -ENOMEM;
  190. goto err_free_aic;
  191. }
  192. ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
  193. handle_fasteoi_irq,
  194. IRQ_NOREQUEST | IRQ_NOPROBE |
  195. IRQ_NOAUTOEN, 0, 0);
  196. if (ret)
  197. goto err_domain_remove;
  198. for (i = 0; i < nchips; i++) {
  199. gc = irq_get_domain_generic_chip(domain, i * 32);
  200. gc->reg_base = reg_base;
  201. gc->unused = 0;
  202. gc->wake_enabled = ~0;
  203. gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
  204. gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
  205. gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
  206. gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
  207. gc->private = &aic[i];
  208. }
  209. aic_common_ext_irq_of_init(domain);
  210. aic_common_irq_fixup(matches);
  211. return domain;
  212. err_domain_remove:
  213. irq_domain_remove(domain);
  214. err_free_aic:
  215. kfree(aic);
  216. err_iounmap:
  217. iounmap(reg_base);
  218. return ERR_PTR(ret);
  219. }