irq-alpine-msi.c 7.0 KB

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  1. /*
  2. * Annapurna Labs MSIX support services
  3. *
  4. * Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
  5. *
  6. * Antoine Tenart <antoine.tenart@free-electrons.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/irqchip.h>
  14. #include <linux/irqchip/arm-gic.h>
  15. #include <linux/msi.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_pci.h>
  20. #include <linux/pci.h>
  21. #include <linux/slab.h>
  22. #include <asm/irq.h>
  23. #include <asm/msi.h>
  24. /* MSIX message address format: local GIC target */
  25. #define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16)
  26. struct alpine_msix_data {
  27. spinlock_t msi_map_lock;
  28. phys_addr_t addr;
  29. u32 spi_first; /* The SGI number that MSIs start */
  30. u32 num_spis; /* The number of SGIs for MSIs */
  31. unsigned long *msi_map;
  32. };
  33. static void alpine_msix_mask_msi_irq(struct irq_data *d)
  34. {
  35. pci_msi_mask_irq(d);
  36. irq_chip_mask_parent(d);
  37. }
  38. static void alpine_msix_unmask_msi_irq(struct irq_data *d)
  39. {
  40. pci_msi_unmask_irq(d);
  41. irq_chip_unmask_parent(d);
  42. }
  43. static struct irq_chip alpine_msix_irq_chip = {
  44. .name = "MSIx",
  45. .irq_mask = alpine_msix_mask_msi_irq,
  46. .irq_unmask = alpine_msix_unmask_msi_irq,
  47. .irq_eoi = irq_chip_eoi_parent,
  48. .irq_set_affinity = irq_chip_set_affinity_parent,
  49. };
  50. static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
  51. {
  52. int first;
  53. spin_lock(&priv->msi_map_lock);
  54. first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
  55. num_req, 0);
  56. if (first >= priv->num_spis) {
  57. spin_unlock(&priv->msi_map_lock);
  58. return -ENOSPC;
  59. }
  60. bitmap_set(priv->msi_map, first, num_req);
  61. spin_unlock(&priv->msi_map_lock);
  62. return priv->spi_first + first;
  63. }
  64. static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
  65. int num_req)
  66. {
  67. int first = sgi - priv->spi_first;
  68. spin_lock(&priv->msi_map_lock);
  69. bitmap_clear(priv->msi_map, first, num_req);
  70. spin_unlock(&priv->msi_map_lock);
  71. }
  72. static void alpine_msix_compose_msi_msg(struct irq_data *data,
  73. struct msi_msg *msg)
  74. {
  75. struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
  76. phys_addr_t msg_addr = priv->addr;
  77. msg_addr |= (data->hwirq << 3);
  78. msg->address_hi = upper_32_bits(msg_addr);
  79. msg->address_lo = lower_32_bits(msg_addr);
  80. msg->data = 0;
  81. }
  82. static struct msi_domain_info alpine_msix_domain_info = {
  83. .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  84. MSI_FLAG_PCI_MSIX,
  85. .chip = &alpine_msix_irq_chip,
  86. };
  87. static struct irq_chip middle_irq_chip = {
  88. .name = "alpine_msix_middle",
  89. .irq_mask = irq_chip_mask_parent,
  90. .irq_unmask = irq_chip_unmask_parent,
  91. .irq_eoi = irq_chip_eoi_parent,
  92. .irq_set_affinity = irq_chip_set_affinity_parent,
  93. .irq_compose_msi_msg = alpine_msix_compose_msi_msg,
  94. };
  95. static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
  96. unsigned int virq, int sgi)
  97. {
  98. struct irq_fwspec fwspec;
  99. struct irq_data *d;
  100. int ret;
  101. if (!is_of_node(domain->parent->fwnode))
  102. return -EINVAL;
  103. fwspec.fwnode = domain->parent->fwnode;
  104. fwspec.param_count = 3;
  105. fwspec.param[0] = 0;
  106. fwspec.param[1] = sgi;
  107. fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
  108. ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
  109. if (ret)
  110. return ret;
  111. d = irq_domain_get_irq_data(domain->parent, virq);
  112. d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
  113. return 0;
  114. }
  115. static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
  116. unsigned int virq,
  117. unsigned int nr_irqs, void *args)
  118. {
  119. struct alpine_msix_data *priv = domain->host_data;
  120. int sgi, err, i;
  121. sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
  122. if (sgi < 0)
  123. return sgi;
  124. for (i = 0; i < nr_irqs; i++) {
  125. err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
  126. if (err)
  127. goto err_sgi;
  128. irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
  129. &middle_irq_chip, priv);
  130. }
  131. return 0;
  132. err_sgi:
  133. irq_domain_free_irqs_parent(domain, virq, i - 1);
  134. alpine_msix_free_sgi(priv, sgi, nr_irqs);
  135. return err;
  136. }
  137. static void alpine_msix_middle_domain_free(struct irq_domain *domain,
  138. unsigned int virq,
  139. unsigned int nr_irqs)
  140. {
  141. struct irq_data *d = irq_domain_get_irq_data(domain, virq);
  142. struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
  143. irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  144. alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
  145. }
  146. static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
  147. .alloc = alpine_msix_middle_domain_alloc,
  148. .free = alpine_msix_middle_domain_free,
  149. };
  150. static int alpine_msix_init_domains(struct alpine_msix_data *priv,
  151. struct device_node *node)
  152. {
  153. struct irq_domain *middle_domain, *msi_domain, *gic_domain;
  154. struct device_node *gic_node;
  155. gic_node = of_irq_find_parent(node);
  156. if (!gic_node) {
  157. pr_err("Failed to find the GIC node\n");
  158. return -ENODEV;
  159. }
  160. gic_domain = irq_find_host(gic_node);
  161. if (!gic_domain) {
  162. pr_err("Failed to find the GIC domain\n");
  163. return -ENXIO;
  164. }
  165. middle_domain = irq_domain_add_tree(NULL,
  166. &alpine_msix_middle_domain_ops,
  167. priv);
  168. if (!middle_domain) {
  169. pr_err("Failed to create the MSIX middle domain\n");
  170. return -ENOMEM;
  171. }
  172. middle_domain->parent = gic_domain;
  173. msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
  174. &alpine_msix_domain_info,
  175. middle_domain);
  176. if (!msi_domain) {
  177. pr_err("Failed to create MSI domain\n");
  178. irq_domain_remove(middle_domain);
  179. return -ENOMEM;
  180. }
  181. return 0;
  182. }
  183. static int alpine_msix_init(struct device_node *node,
  184. struct device_node *parent)
  185. {
  186. struct alpine_msix_data *priv;
  187. struct resource res;
  188. int ret;
  189. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  190. if (!priv)
  191. return -ENOMEM;
  192. spin_lock_init(&priv->msi_map_lock);
  193. ret = of_address_to_resource(node, 0, &res);
  194. if (ret) {
  195. pr_err("Failed to allocate resource\n");
  196. goto err_priv;
  197. }
  198. /*
  199. * The 20 least significant bits of addr provide direct information
  200. * regarding the interrupt destination.
  201. *
  202. * To select the primary GIC as the target GIC, bits [18:17] must be set
  203. * to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
  204. */
  205. priv->addr = res.start & GENMASK_ULL(63,20);
  206. priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
  207. if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
  208. pr_err("Unable to parse MSI base\n");
  209. ret = -EINVAL;
  210. goto err_priv;
  211. }
  212. if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
  213. pr_err("Unable to parse MSI numbers\n");
  214. ret = -EINVAL;
  215. goto err_priv;
  216. }
  217. priv->msi_map = kcalloc(BITS_TO_LONGS(priv->num_spis),
  218. sizeof(*priv->msi_map),
  219. GFP_KERNEL);
  220. if (!priv->msi_map) {
  221. ret = -ENOMEM;
  222. goto err_priv;
  223. }
  224. pr_debug("Registering %d msixs, starting at %d\n",
  225. priv->num_spis, priv->spi_first);
  226. ret = alpine_msix_init_domains(priv, node);
  227. if (ret)
  228. goto err_map;
  229. return 0;
  230. err_map:
  231. kfree(priv->msi_map);
  232. err_priv:
  233. kfree(priv);
  234. return ret;
  235. }
  236. IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);