exynos-combiner.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Combiner irqchip for EXYNOS
  7. */
  8. #include <linux/err.h>
  9. #include <linux/export.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/slab.h>
  13. #include <linux/syscore_ops.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #define COMBINER_ENABLE_SET 0x0
  21. #define COMBINER_ENABLE_CLEAR 0x4
  22. #define COMBINER_INT_STATUS 0xC
  23. #define IRQ_IN_COMBINER 8
  24. static DEFINE_SPINLOCK(irq_controller_lock);
  25. struct combiner_chip_data {
  26. unsigned int hwirq_offset;
  27. unsigned int irq_mask;
  28. void __iomem *base;
  29. unsigned int parent_irq;
  30. #ifdef CONFIG_PM
  31. u32 pm_save;
  32. #endif
  33. };
  34. static struct combiner_chip_data *combiner_data;
  35. static struct irq_domain *combiner_irq_domain;
  36. static unsigned int max_nr = 20;
  37. static inline void __iomem *combiner_base(struct irq_data *data)
  38. {
  39. struct combiner_chip_data *combiner_data =
  40. irq_data_get_irq_chip_data(data);
  41. return combiner_data->base;
  42. }
  43. static void combiner_mask_irq(struct irq_data *data)
  44. {
  45. u32 mask = 1 << (data->hwirq % 32);
  46. writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
  47. }
  48. static void combiner_unmask_irq(struct irq_data *data)
  49. {
  50. u32 mask = 1 << (data->hwirq % 32);
  51. writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
  52. }
  53. static void combiner_handle_cascade_irq(struct irq_desc *desc)
  54. {
  55. struct combiner_chip_data *chip_data = irq_desc_get_handler_data(desc);
  56. struct irq_chip *chip = irq_desc_get_chip(desc);
  57. unsigned int cascade_irq, combiner_irq;
  58. unsigned long status;
  59. chained_irq_enter(chip, desc);
  60. spin_lock(&irq_controller_lock);
  61. status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
  62. spin_unlock(&irq_controller_lock);
  63. status &= chip_data->irq_mask;
  64. if (status == 0)
  65. goto out;
  66. combiner_irq = chip_data->hwirq_offset + __ffs(status);
  67. cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
  68. if (unlikely(!cascade_irq))
  69. handle_bad_irq(desc);
  70. else
  71. generic_handle_irq(cascade_irq);
  72. out:
  73. chained_irq_exit(chip, desc);
  74. }
  75. #ifdef CONFIG_SMP
  76. static int combiner_set_affinity(struct irq_data *d,
  77. const struct cpumask *mask_val, bool force)
  78. {
  79. struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  80. struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
  81. struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
  82. if (chip && chip->irq_set_affinity)
  83. return chip->irq_set_affinity(data, mask_val, force);
  84. else
  85. return -EINVAL;
  86. }
  87. #endif
  88. static struct irq_chip combiner_chip = {
  89. .name = "COMBINER",
  90. .irq_mask = combiner_mask_irq,
  91. .irq_unmask = combiner_unmask_irq,
  92. #ifdef CONFIG_SMP
  93. .irq_set_affinity = combiner_set_affinity,
  94. #endif
  95. };
  96. static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
  97. unsigned int irq)
  98. {
  99. irq_set_chained_handler_and_data(irq, combiner_handle_cascade_irq,
  100. combiner_data);
  101. }
  102. static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
  103. unsigned int combiner_nr,
  104. void __iomem *base, unsigned int irq)
  105. {
  106. combiner_data->base = base;
  107. combiner_data->hwirq_offset = (combiner_nr & ~3) * IRQ_IN_COMBINER;
  108. combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
  109. combiner_data->parent_irq = irq;
  110. /* Disable all interrupts */
  111. writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
  112. }
  113. static int combiner_irq_domain_xlate(struct irq_domain *d,
  114. struct device_node *controller,
  115. const u32 *intspec, unsigned int intsize,
  116. unsigned long *out_hwirq,
  117. unsigned int *out_type)
  118. {
  119. if (irq_domain_get_of_node(d) != controller)
  120. return -EINVAL;
  121. if (intsize < 2)
  122. return -EINVAL;
  123. *out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
  124. *out_type = 0;
  125. return 0;
  126. }
  127. static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
  128. irq_hw_number_t hw)
  129. {
  130. struct combiner_chip_data *combiner_data = d->host_data;
  131. irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
  132. irq_set_chip_data(irq, &combiner_data[hw >> 3]);
  133. irq_set_probe(irq);
  134. return 0;
  135. }
  136. static const struct irq_domain_ops combiner_irq_domain_ops = {
  137. .xlate = combiner_irq_domain_xlate,
  138. .map = combiner_irq_domain_map,
  139. };
  140. static void __init combiner_init(void __iomem *combiner_base,
  141. struct device_node *np)
  142. {
  143. int i, irq;
  144. unsigned int nr_irq;
  145. nr_irq = max_nr * IRQ_IN_COMBINER;
  146. combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
  147. if (!combiner_data) {
  148. pr_warn("%s: could not allocate combiner data\n", __func__);
  149. return;
  150. }
  151. combiner_irq_domain = irq_domain_add_linear(np, nr_irq,
  152. &combiner_irq_domain_ops, combiner_data);
  153. if (WARN_ON(!combiner_irq_domain)) {
  154. pr_warn("%s: irq domain init failed\n", __func__);
  155. return;
  156. }
  157. for (i = 0; i < max_nr; i++) {
  158. irq = irq_of_parse_and_map(np, i);
  159. combiner_init_one(&combiner_data[i], i,
  160. combiner_base + (i >> 2) * 0x10, irq);
  161. combiner_cascade_irq(&combiner_data[i], irq);
  162. }
  163. }
  164. #ifdef CONFIG_PM
  165. /**
  166. * combiner_suspend - save interrupt combiner state before suspend
  167. *
  168. * Save the interrupt enable set register for all combiner groups since
  169. * the state is lost when the system enters into a sleep state.
  170. *
  171. */
  172. static int combiner_suspend(void)
  173. {
  174. int i;
  175. for (i = 0; i < max_nr; i++)
  176. combiner_data[i].pm_save =
  177. readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
  178. return 0;
  179. }
  180. /**
  181. * combiner_resume - restore interrupt combiner state after resume
  182. *
  183. * Restore the interrupt enable set register for all combiner groups since
  184. * the state is lost when the system enters into a sleep state on suspend.
  185. *
  186. */
  187. static void combiner_resume(void)
  188. {
  189. int i;
  190. for (i = 0; i < max_nr; i++) {
  191. writel_relaxed(combiner_data[i].irq_mask,
  192. combiner_data[i].base + COMBINER_ENABLE_CLEAR);
  193. writel_relaxed(combiner_data[i].pm_save,
  194. combiner_data[i].base + COMBINER_ENABLE_SET);
  195. }
  196. }
  197. #else
  198. #define combiner_suspend NULL
  199. #define combiner_resume NULL
  200. #endif
  201. static struct syscore_ops combiner_syscore_ops = {
  202. .suspend = combiner_suspend,
  203. .resume = combiner_resume,
  204. };
  205. static int __init combiner_of_init(struct device_node *np,
  206. struct device_node *parent)
  207. {
  208. void __iomem *combiner_base;
  209. combiner_base = of_iomap(np, 0);
  210. if (!combiner_base) {
  211. pr_err("%s: failed to map combiner registers\n", __func__);
  212. return -ENXIO;
  213. }
  214. if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
  215. pr_info("%s: number of combiners not specified, "
  216. "setting default as %d.\n",
  217. __func__, max_nr);
  218. }
  219. combiner_init(combiner_base, np);
  220. register_syscore_ops(&combiner_syscore_ops);
  221. return 0;
  222. }
  223. IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
  224. combiner_of_init);