irq_remapping.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531
  1. // SPDX-License-Identifier: GPL-2.0
  2. #define pr_fmt(fmt) "DMAR-IR: " fmt
  3. #include <linux/interrupt.h>
  4. #include <linux/dmar.h>
  5. #include <linux/spinlock.h>
  6. #include <linux/slab.h>
  7. #include <linux/jiffies.h>
  8. #include <linux/hpet.h>
  9. #include <linux/pci.h>
  10. #include <linux/irq.h>
  11. #include <linux/intel-iommu.h>
  12. #include <linux/acpi.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/crash_dump.h>
  15. #include <asm/io_apic.h>
  16. #include <asm/apic.h>
  17. #include <asm/smp.h>
  18. #include <asm/cpu.h>
  19. #include <asm/irq_remapping.h>
  20. #include <asm/pci-direct.h>
  21. #include <asm/msidef.h>
  22. #include "../irq_remapping.h"
  23. enum irq_mode {
  24. IRQ_REMAPPING,
  25. IRQ_POSTING,
  26. };
  27. struct ioapic_scope {
  28. struct intel_iommu *iommu;
  29. unsigned int id;
  30. unsigned int bus; /* PCI bus number */
  31. unsigned int devfn; /* PCI devfn number */
  32. };
  33. struct hpet_scope {
  34. struct intel_iommu *iommu;
  35. u8 id;
  36. unsigned int bus;
  37. unsigned int devfn;
  38. };
  39. struct irq_2_iommu {
  40. struct intel_iommu *iommu;
  41. u16 irte_index;
  42. u16 sub_handle;
  43. u8 irte_mask;
  44. enum irq_mode mode;
  45. };
  46. struct intel_ir_data {
  47. struct irq_2_iommu irq_2_iommu;
  48. struct irte irte_entry;
  49. union {
  50. struct msi_msg msi_entry;
  51. };
  52. };
  53. #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
  54. #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
  55. static int __read_mostly eim_mode;
  56. static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  57. static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  58. /*
  59. * Lock ordering:
  60. * ->dmar_global_lock
  61. * ->irq_2_ir_lock
  62. * ->qi->q_lock
  63. * ->iommu->register_lock
  64. * Note:
  65. * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
  66. * in single-threaded environment with interrupt disabled, so no need to tabke
  67. * the dmar_global_lock.
  68. */
  69. DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
  70. static const struct irq_domain_ops intel_ir_domain_ops;
  71. static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
  72. static int __init parse_ioapics_under_ir(void);
  73. static bool ir_pre_enabled(struct intel_iommu *iommu)
  74. {
  75. return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
  76. }
  77. static void clear_ir_pre_enabled(struct intel_iommu *iommu)
  78. {
  79. iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
  80. }
  81. static void init_ir_status(struct intel_iommu *iommu)
  82. {
  83. u32 gsts;
  84. gsts = readl(iommu->reg + DMAR_GSTS_REG);
  85. if (gsts & DMA_GSTS_IRES)
  86. iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
  87. }
  88. static int alloc_irte(struct intel_iommu *iommu,
  89. struct irq_2_iommu *irq_iommu, u16 count)
  90. {
  91. struct ir_table *table = iommu->ir_table;
  92. unsigned int mask = 0;
  93. unsigned long flags;
  94. int index;
  95. if (!count || !irq_iommu)
  96. return -1;
  97. if (count > 1) {
  98. count = __roundup_pow_of_two(count);
  99. mask = ilog2(count);
  100. }
  101. if (mask > ecap_max_handle_mask(iommu->ecap)) {
  102. pr_err("Requested mask %x exceeds the max invalidation handle"
  103. " mask value %Lx\n", mask,
  104. ecap_max_handle_mask(iommu->ecap));
  105. return -1;
  106. }
  107. raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  108. index = bitmap_find_free_region(table->bitmap,
  109. INTR_REMAP_TABLE_ENTRIES, mask);
  110. if (index < 0) {
  111. pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
  112. } else {
  113. irq_iommu->iommu = iommu;
  114. irq_iommu->irte_index = index;
  115. irq_iommu->sub_handle = 0;
  116. irq_iommu->irte_mask = mask;
  117. irq_iommu->mode = IRQ_REMAPPING;
  118. }
  119. raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  120. return index;
  121. }
  122. static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
  123. {
  124. struct qi_desc desc;
  125. desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
  126. | QI_IEC_SELECTIVE;
  127. desc.qw1 = 0;
  128. desc.qw2 = 0;
  129. desc.qw3 = 0;
  130. return qi_submit_sync(iommu, &desc, 1, 0);
  131. }
  132. static int modify_irte(struct irq_2_iommu *irq_iommu,
  133. struct irte *irte_modified)
  134. {
  135. struct intel_iommu *iommu;
  136. unsigned long flags;
  137. struct irte *irte;
  138. int rc, index;
  139. if (!irq_iommu)
  140. return -1;
  141. raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  142. iommu = irq_iommu->iommu;
  143. index = irq_iommu->irte_index + irq_iommu->sub_handle;
  144. irte = &iommu->ir_table->base[index];
  145. #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
  146. if ((irte->pst == 1) || (irte_modified->pst == 1)) {
  147. bool ret;
  148. ret = cmpxchg_double(&irte->low, &irte->high,
  149. irte->low, irte->high,
  150. irte_modified->low, irte_modified->high);
  151. /*
  152. * We use cmpxchg16 to atomically update the 128-bit IRTE,
  153. * and it cannot be updated by the hardware or other processors
  154. * behind us, so the return value of cmpxchg16 should be the
  155. * same as the old value.
  156. */
  157. WARN_ON(!ret);
  158. } else
  159. #endif
  160. {
  161. set_64bit(&irte->low, irte_modified->low);
  162. set_64bit(&irte->high, irte_modified->high);
  163. }
  164. __iommu_flush_cache(iommu, irte, sizeof(*irte));
  165. rc = qi_flush_iec(iommu, index, 0);
  166. /* Update iommu mode according to the IRTE mode */
  167. irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
  168. raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  169. return rc;
  170. }
  171. static struct irq_domain *map_hpet_to_ir(u8 hpet_id)
  172. {
  173. int i;
  174. for (i = 0; i < MAX_HPET_TBS; i++) {
  175. if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
  176. return ir_hpet[i].iommu->ir_domain;
  177. }
  178. return NULL;
  179. }
  180. static struct intel_iommu *map_ioapic_to_iommu(int apic)
  181. {
  182. int i;
  183. for (i = 0; i < MAX_IO_APICS; i++) {
  184. if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
  185. return ir_ioapic[i].iommu;
  186. }
  187. return NULL;
  188. }
  189. static struct irq_domain *map_ioapic_to_ir(int apic)
  190. {
  191. struct intel_iommu *iommu = map_ioapic_to_iommu(apic);
  192. return iommu ? iommu->ir_domain : NULL;
  193. }
  194. static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
  195. {
  196. struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
  197. return drhd ? drhd->iommu->ir_msi_domain : NULL;
  198. }
  199. static int clear_entries(struct irq_2_iommu *irq_iommu)
  200. {
  201. struct irte *start, *entry, *end;
  202. struct intel_iommu *iommu;
  203. int index;
  204. if (irq_iommu->sub_handle)
  205. return 0;
  206. iommu = irq_iommu->iommu;
  207. index = irq_iommu->irte_index;
  208. start = iommu->ir_table->base + index;
  209. end = start + (1 << irq_iommu->irte_mask);
  210. for (entry = start; entry < end; entry++) {
  211. set_64bit(&entry->low, 0);
  212. set_64bit(&entry->high, 0);
  213. }
  214. bitmap_release_region(iommu->ir_table->bitmap, index,
  215. irq_iommu->irte_mask);
  216. return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
  217. }
  218. /*
  219. * source validation type
  220. */
  221. #define SVT_NO_VERIFY 0x0 /* no verification is required */
  222. #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
  223. #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
  224. /*
  225. * source-id qualifier
  226. */
  227. #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
  228. #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
  229. * the third least significant bit
  230. */
  231. #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
  232. * the second and third least significant bits
  233. */
  234. #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
  235. * the least three significant bits
  236. */
  237. /*
  238. * set SVT, SQ and SID fields of irte to verify
  239. * source ids of interrupt requests
  240. */
  241. static void set_irte_sid(struct irte *irte, unsigned int svt,
  242. unsigned int sq, unsigned int sid)
  243. {
  244. if (disable_sourceid_checking)
  245. svt = SVT_NO_VERIFY;
  246. irte->svt = svt;
  247. irte->sq = sq;
  248. irte->sid = sid;
  249. }
  250. /*
  251. * Set an IRTE to match only the bus number. Interrupt requests that reference
  252. * this IRTE must have a requester-id whose bus number is between or equal
  253. * to the start_bus and end_bus arguments.
  254. */
  255. static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
  256. unsigned int end_bus)
  257. {
  258. set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
  259. (start_bus << 8) | end_bus);
  260. }
  261. static int set_ioapic_sid(struct irte *irte, int apic)
  262. {
  263. int i;
  264. u16 sid = 0;
  265. if (!irte)
  266. return -1;
  267. down_read(&dmar_global_lock);
  268. for (i = 0; i < MAX_IO_APICS; i++) {
  269. if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
  270. sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
  271. break;
  272. }
  273. }
  274. up_read(&dmar_global_lock);
  275. if (sid == 0) {
  276. pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
  277. return -1;
  278. }
  279. set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
  280. return 0;
  281. }
  282. static int set_hpet_sid(struct irte *irte, u8 id)
  283. {
  284. int i;
  285. u16 sid = 0;
  286. if (!irte)
  287. return -1;
  288. down_read(&dmar_global_lock);
  289. for (i = 0; i < MAX_HPET_TBS; i++) {
  290. if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
  291. sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
  292. break;
  293. }
  294. }
  295. up_read(&dmar_global_lock);
  296. if (sid == 0) {
  297. pr_warn("Failed to set source-id of HPET block (%d)\n", id);
  298. return -1;
  299. }
  300. /*
  301. * Should really use SQ_ALL_16. Some platforms are broken.
  302. * While we figure out the right quirks for these broken platforms, use
  303. * SQ_13_IGNORE_3 for now.
  304. */
  305. set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
  306. return 0;
  307. }
  308. struct set_msi_sid_data {
  309. struct pci_dev *pdev;
  310. u16 alias;
  311. int count;
  312. int busmatch_count;
  313. };
  314. static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
  315. {
  316. struct set_msi_sid_data *data = opaque;
  317. if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
  318. data->busmatch_count++;
  319. data->pdev = pdev;
  320. data->alias = alias;
  321. data->count++;
  322. return 0;
  323. }
  324. static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
  325. {
  326. struct set_msi_sid_data data;
  327. if (!irte || !dev)
  328. return -1;
  329. data.count = 0;
  330. data.busmatch_count = 0;
  331. pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
  332. /*
  333. * DMA alias provides us with a PCI device and alias. The only case
  334. * where the it will return an alias on a different bus than the
  335. * device is the case of a PCIe-to-PCI bridge, where the alias is for
  336. * the subordinate bus. In this case we can only verify the bus.
  337. *
  338. * If there are multiple aliases, all with the same bus number,
  339. * then all we can do is verify the bus. This is typical in NTB
  340. * hardware which use proxy IDs where the device will generate traffic
  341. * from multiple devfn numbers on the same bus.
  342. *
  343. * If the alias device is on a different bus than our source device
  344. * then we have a topology based alias, use it.
  345. *
  346. * Otherwise, the alias is for a device DMA quirk and we cannot
  347. * assume that MSI uses the same requester ID. Therefore use the
  348. * original device.
  349. */
  350. if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
  351. set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
  352. dev->bus->number);
  353. else if (data.count >= 2 && data.busmatch_count == data.count)
  354. set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
  355. else if (data.pdev->bus->number != dev->bus->number)
  356. set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
  357. else
  358. set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
  359. pci_dev_id(dev));
  360. return 0;
  361. }
  362. static int iommu_load_old_irte(struct intel_iommu *iommu)
  363. {
  364. struct irte *old_ir_table;
  365. phys_addr_t irt_phys;
  366. unsigned int i;
  367. size_t size;
  368. u64 irta;
  369. /* Check whether the old ir-table has the same size as ours */
  370. irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
  371. if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
  372. != INTR_REMAP_TABLE_REG_SIZE)
  373. return -EINVAL;
  374. irt_phys = irta & VTD_PAGE_MASK;
  375. size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
  376. /* Map the old IR table */
  377. old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
  378. if (!old_ir_table)
  379. return -ENOMEM;
  380. /* Copy data over */
  381. memcpy(iommu->ir_table->base, old_ir_table, size);
  382. __iommu_flush_cache(iommu, iommu->ir_table->base, size);
  383. /*
  384. * Now check the table for used entries and mark those as
  385. * allocated in the bitmap
  386. */
  387. for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
  388. if (iommu->ir_table->base[i].present)
  389. bitmap_set(iommu->ir_table->bitmap, i, 1);
  390. }
  391. memunmap(old_ir_table);
  392. return 0;
  393. }
  394. static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
  395. {
  396. unsigned long flags;
  397. u64 addr;
  398. u32 sts;
  399. addr = virt_to_phys((void *)iommu->ir_table->base);
  400. raw_spin_lock_irqsave(&iommu->register_lock, flags);
  401. dmar_writeq(iommu->reg + DMAR_IRTA_REG,
  402. (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
  403. /* Set interrupt-remapping table pointer */
  404. writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
  405. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  406. readl, (sts & DMA_GSTS_IRTPS), sts);
  407. raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
  408. /*
  409. * Global invalidation of interrupt entry cache to make sure the
  410. * hardware uses the new irq remapping table.
  411. */
  412. qi_global_iec(iommu);
  413. }
  414. static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
  415. {
  416. unsigned long flags;
  417. u32 sts;
  418. raw_spin_lock_irqsave(&iommu->register_lock, flags);
  419. /* Enable interrupt-remapping */
  420. iommu->gcmd |= DMA_GCMD_IRE;
  421. writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
  422. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  423. readl, (sts & DMA_GSTS_IRES), sts);
  424. /* Block compatibility-format MSIs */
  425. if (sts & DMA_GSTS_CFIS) {
  426. iommu->gcmd &= ~DMA_GCMD_CFI;
  427. writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
  428. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  429. readl, !(sts & DMA_GSTS_CFIS), sts);
  430. }
  431. /*
  432. * With CFI clear in the Global Command register, we should be
  433. * protected from dangerous (i.e. compatibility) interrupts
  434. * regardless of x2apic status. Check just to be sure.
  435. */
  436. if (sts & DMA_GSTS_CFIS)
  437. WARN(1, KERN_WARNING
  438. "Compatibility-format IRQs enabled despite intr remapping;\n"
  439. "you are vulnerable to IRQ injection.\n");
  440. raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
  441. }
  442. static int intel_setup_irq_remapping(struct intel_iommu *iommu)
  443. {
  444. struct ir_table *ir_table;
  445. struct fwnode_handle *fn;
  446. unsigned long *bitmap;
  447. struct page *pages;
  448. if (iommu->ir_table)
  449. return 0;
  450. ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
  451. if (!ir_table)
  452. return -ENOMEM;
  453. pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
  454. INTR_REMAP_PAGE_ORDER);
  455. if (!pages) {
  456. pr_err("IR%d: failed to allocate pages of order %d\n",
  457. iommu->seq_id, INTR_REMAP_PAGE_ORDER);
  458. goto out_free_table;
  459. }
  460. bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
  461. if (bitmap == NULL) {
  462. pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
  463. goto out_free_pages;
  464. }
  465. fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
  466. if (!fn)
  467. goto out_free_bitmap;
  468. iommu->ir_domain =
  469. irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
  470. 0, INTR_REMAP_TABLE_ENTRIES,
  471. fn, &intel_ir_domain_ops,
  472. iommu);
  473. if (!iommu->ir_domain) {
  474. pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
  475. goto out_free_fwnode;
  476. }
  477. iommu->ir_msi_domain =
  478. arch_create_remap_msi_irq_domain(iommu->ir_domain,
  479. "INTEL-IR-MSI",
  480. iommu->seq_id);
  481. ir_table->base = page_address(pages);
  482. ir_table->bitmap = bitmap;
  483. iommu->ir_table = ir_table;
  484. /*
  485. * If the queued invalidation is already initialized,
  486. * shouldn't disable it.
  487. */
  488. if (!iommu->qi) {
  489. /*
  490. * Clear previous faults.
  491. */
  492. dmar_fault(-1, iommu);
  493. dmar_disable_qi(iommu);
  494. if (dmar_enable_qi(iommu)) {
  495. pr_err("Failed to enable queued invalidation\n");
  496. goto out_free_ir_domain;
  497. }
  498. }
  499. init_ir_status(iommu);
  500. if (ir_pre_enabled(iommu)) {
  501. if (!is_kdump_kernel()) {
  502. pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
  503. iommu->name);
  504. clear_ir_pre_enabled(iommu);
  505. iommu_disable_irq_remapping(iommu);
  506. } else if (iommu_load_old_irte(iommu))
  507. pr_err("Failed to copy IR table for %s from previous kernel\n",
  508. iommu->name);
  509. else
  510. pr_info("Copied IR table for %s from previous kernel\n",
  511. iommu->name);
  512. }
  513. iommu_set_irq_remapping(iommu, eim_mode);
  514. return 0;
  515. out_free_ir_domain:
  516. if (iommu->ir_msi_domain)
  517. irq_domain_remove(iommu->ir_msi_domain);
  518. iommu->ir_msi_domain = NULL;
  519. irq_domain_remove(iommu->ir_domain);
  520. iommu->ir_domain = NULL;
  521. out_free_fwnode:
  522. irq_domain_free_fwnode(fn);
  523. out_free_bitmap:
  524. bitmap_free(bitmap);
  525. out_free_pages:
  526. __free_pages(pages, INTR_REMAP_PAGE_ORDER);
  527. out_free_table:
  528. kfree(ir_table);
  529. iommu->ir_table = NULL;
  530. return -ENOMEM;
  531. }
  532. static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
  533. {
  534. struct fwnode_handle *fn;
  535. if (iommu && iommu->ir_table) {
  536. if (iommu->ir_msi_domain) {
  537. fn = iommu->ir_msi_domain->fwnode;
  538. irq_domain_remove(iommu->ir_msi_domain);
  539. irq_domain_free_fwnode(fn);
  540. iommu->ir_msi_domain = NULL;
  541. }
  542. if (iommu->ir_domain) {
  543. fn = iommu->ir_domain->fwnode;
  544. irq_domain_remove(iommu->ir_domain);
  545. irq_domain_free_fwnode(fn);
  546. iommu->ir_domain = NULL;
  547. }
  548. free_pages((unsigned long)iommu->ir_table->base,
  549. INTR_REMAP_PAGE_ORDER);
  550. bitmap_free(iommu->ir_table->bitmap);
  551. kfree(iommu->ir_table);
  552. iommu->ir_table = NULL;
  553. }
  554. }
  555. /*
  556. * Disable Interrupt Remapping.
  557. */
  558. static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
  559. {
  560. unsigned long flags;
  561. u32 sts;
  562. if (!ecap_ir_support(iommu->ecap))
  563. return;
  564. /*
  565. * global invalidation of interrupt entry cache before disabling
  566. * interrupt-remapping.
  567. */
  568. qi_global_iec(iommu);
  569. raw_spin_lock_irqsave(&iommu->register_lock, flags);
  570. sts = readl(iommu->reg + DMAR_GSTS_REG);
  571. if (!(sts & DMA_GSTS_IRES))
  572. goto end;
  573. iommu->gcmd &= ~DMA_GCMD_IRE;
  574. writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
  575. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  576. readl, !(sts & DMA_GSTS_IRES), sts);
  577. end:
  578. raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
  579. }
  580. static int __init dmar_x2apic_optout(void)
  581. {
  582. struct acpi_table_dmar *dmar;
  583. dmar = (struct acpi_table_dmar *)dmar_tbl;
  584. if (!dmar || no_x2apic_optout)
  585. return 0;
  586. return dmar->flags & DMAR_X2APIC_OPT_OUT;
  587. }
  588. static void __init intel_cleanup_irq_remapping(void)
  589. {
  590. struct dmar_drhd_unit *drhd;
  591. struct intel_iommu *iommu;
  592. for_each_iommu(iommu, drhd) {
  593. if (ecap_ir_support(iommu->ecap)) {
  594. iommu_disable_irq_remapping(iommu);
  595. intel_teardown_irq_remapping(iommu);
  596. }
  597. }
  598. if (x2apic_supported())
  599. pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
  600. }
  601. static int __init intel_prepare_irq_remapping(void)
  602. {
  603. struct dmar_drhd_unit *drhd;
  604. struct intel_iommu *iommu;
  605. int eim = 0;
  606. if (irq_remap_broken) {
  607. pr_warn("This system BIOS has enabled interrupt remapping\n"
  608. "on a chipset that contains an erratum making that\n"
  609. "feature unstable. To maintain system stability\n"
  610. "interrupt remapping is being disabled. Please\n"
  611. "contact your BIOS vendor for an update\n");
  612. add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
  613. return -ENODEV;
  614. }
  615. if (dmar_table_init() < 0)
  616. return -ENODEV;
  617. if (!dmar_ir_support())
  618. return -ENODEV;
  619. if (parse_ioapics_under_ir()) {
  620. pr_info("Not enabling interrupt remapping\n");
  621. goto error;
  622. }
  623. /* First make sure all IOMMUs support IRQ remapping */
  624. for_each_iommu(iommu, drhd)
  625. if (!ecap_ir_support(iommu->ecap))
  626. goto error;
  627. /* Detect remapping mode: lapic or x2apic */
  628. if (x2apic_supported()) {
  629. eim = !dmar_x2apic_optout();
  630. if (!eim) {
  631. pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
  632. pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
  633. }
  634. }
  635. for_each_iommu(iommu, drhd) {
  636. if (eim && !ecap_eim_support(iommu->ecap)) {
  637. pr_info("%s does not support EIM\n", iommu->name);
  638. eim = 0;
  639. }
  640. }
  641. eim_mode = eim;
  642. if (eim)
  643. pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
  644. /* Do the initializations early */
  645. for_each_iommu(iommu, drhd) {
  646. if (intel_setup_irq_remapping(iommu)) {
  647. pr_err("Failed to setup irq remapping for %s\n",
  648. iommu->name);
  649. goto error;
  650. }
  651. }
  652. return 0;
  653. error:
  654. intel_cleanup_irq_remapping();
  655. return -ENODEV;
  656. }
  657. /*
  658. * Set Posted-Interrupts capability.
  659. */
  660. static inline void set_irq_posting_cap(void)
  661. {
  662. struct dmar_drhd_unit *drhd;
  663. struct intel_iommu *iommu;
  664. if (!disable_irq_post) {
  665. /*
  666. * If IRTE is in posted format, the 'pda' field goes across the
  667. * 64-bit boundary, we need use cmpxchg16b to atomically update
  668. * it. We only expose posted-interrupt when X86_FEATURE_CX16
  669. * is supported. Actually, hardware platforms supporting PI
  670. * should have X86_FEATURE_CX16 support, this has been confirmed
  671. * with Intel hardware guys.
  672. */
  673. if (boot_cpu_has(X86_FEATURE_CX16))
  674. intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
  675. for_each_iommu(iommu, drhd)
  676. if (!cap_pi_support(iommu->cap)) {
  677. intel_irq_remap_ops.capability &=
  678. ~(1 << IRQ_POSTING_CAP);
  679. break;
  680. }
  681. }
  682. }
  683. static int __init intel_enable_irq_remapping(void)
  684. {
  685. struct dmar_drhd_unit *drhd;
  686. struct intel_iommu *iommu;
  687. bool setup = false;
  688. /*
  689. * Setup Interrupt-remapping for all the DRHD's now.
  690. */
  691. for_each_iommu(iommu, drhd) {
  692. if (!ir_pre_enabled(iommu))
  693. iommu_enable_irq_remapping(iommu);
  694. setup = true;
  695. }
  696. if (!setup)
  697. goto error;
  698. irq_remapping_enabled = 1;
  699. set_irq_posting_cap();
  700. pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
  701. return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
  702. error:
  703. intel_cleanup_irq_remapping();
  704. return -1;
  705. }
  706. static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
  707. struct intel_iommu *iommu,
  708. struct acpi_dmar_hardware_unit *drhd)
  709. {
  710. struct acpi_dmar_pci_path *path;
  711. u8 bus;
  712. int count, free = -1;
  713. bus = scope->bus;
  714. path = (struct acpi_dmar_pci_path *)(scope + 1);
  715. count = (scope->length - sizeof(struct acpi_dmar_device_scope))
  716. / sizeof(struct acpi_dmar_pci_path);
  717. while (--count > 0) {
  718. /*
  719. * Access PCI directly due to the PCI
  720. * subsystem isn't initialized yet.
  721. */
  722. bus = read_pci_config_byte(bus, path->device, path->function,
  723. PCI_SECONDARY_BUS);
  724. path++;
  725. }
  726. for (count = 0; count < MAX_HPET_TBS; count++) {
  727. if (ir_hpet[count].iommu == iommu &&
  728. ir_hpet[count].id == scope->enumeration_id)
  729. return 0;
  730. else if (ir_hpet[count].iommu == NULL && free == -1)
  731. free = count;
  732. }
  733. if (free == -1) {
  734. pr_warn("Exceeded Max HPET blocks\n");
  735. return -ENOSPC;
  736. }
  737. ir_hpet[free].iommu = iommu;
  738. ir_hpet[free].id = scope->enumeration_id;
  739. ir_hpet[free].bus = bus;
  740. ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
  741. pr_info("HPET id %d under DRHD base 0x%Lx\n",
  742. scope->enumeration_id, drhd->address);
  743. return 0;
  744. }
  745. static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
  746. struct intel_iommu *iommu,
  747. struct acpi_dmar_hardware_unit *drhd)
  748. {
  749. struct acpi_dmar_pci_path *path;
  750. u8 bus;
  751. int count, free = -1;
  752. bus = scope->bus;
  753. path = (struct acpi_dmar_pci_path *)(scope + 1);
  754. count = (scope->length - sizeof(struct acpi_dmar_device_scope))
  755. / sizeof(struct acpi_dmar_pci_path);
  756. while (--count > 0) {
  757. /*
  758. * Access PCI directly due to the PCI
  759. * subsystem isn't initialized yet.
  760. */
  761. bus = read_pci_config_byte(bus, path->device, path->function,
  762. PCI_SECONDARY_BUS);
  763. path++;
  764. }
  765. for (count = 0; count < MAX_IO_APICS; count++) {
  766. if (ir_ioapic[count].iommu == iommu &&
  767. ir_ioapic[count].id == scope->enumeration_id)
  768. return 0;
  769. else if (ir_ioapic[count].iommu == NULL && free == -1)
  770. free = count;
  771. }
  772. if (free == -1) {
  773. pr_warn("Exceeded Max IO APICS\n");
  774. return -ENOSPC;
  775. }
  776. ir_ioapic[free].bus = bus;
  777. ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
  778. ir_ioapic[free].iommu = iommu;
  779. ir_ioapic[free].id = scope->enumeration_id;
  780. pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
  781. scope->enumeration_id, drhd->address, iommu->seq_id);
  782. return 0;
  783. }
  784. static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
  785. struct intel_iommu *iommu)
  786. {
  787. int ret = 0;
  788. struct acpi_dmar_hardware_unit *drhd;
  789. struct acpi_dmar_device_scope *scope;
  790. void *start, *end;
  791. drhd = (struct acpi_dmar_hardware_unit *)header;
  792. start = (void *)(drhd + 1);
  793. end = ((void *)drhd) + header->length;
  794. while (start < end && ret == 0) {
  795. scope = start;
  796. if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
  797. ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
  798. else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
  799. ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
  800. start += scope->length;
  801. }
  802. return ret;
  803. }
  804. static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
  805. {
  806. int i;
  807. for (i = 0; i < MAX_HPET_TBS; i++)
  808. if (ir_hpet[i].iommu == iommu)
  809. ir_hpet[i].iommu = NULL;
  810. for (i = 0; i < MAX_IO_APICS; i++)
  811. if (ir_ioapic[i].iommu == iommu)
  812. ir_ioapic[i].iommu = NULL;
  813. }
  814. /*
  815. * Finds the assocaition between IOAPIC's and its Interrupt-remapping
  816. * hardware unit.
  817. */
  818. static int __init parse_ioapics_under_ir(void)
  819. {
  820. struct dmar_drhd_unit *drhd;
  821. struct intel_iommu *iommu;
  822. bool ir_supported = false;
  823. int ioapic_idx;
  824. for_each_iommu(iommu, drhd) {
  825. int ret;
  826. if (!ecap_ir_support(iommu->ecap))
  827. continue;
  828. ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
  829. if (ret)
  830. return ret;
  831. ir_supported = true;
  832. }
  833. if (!ir_supported)
  834. return -ENODEV;
  835. for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
  836. int ioapic_id = mpc_ioapic_id(ioapic_idx);
  837. if (!map_ioapic_to_iommu(ioapic_id)) {
  838. pr_err(FW_BUG "ioapic %d has no mapping iommu, "
  839. "interrupt remapping will be disabled\n",
  840. ioapic_id);
  841. return -1;
  842. }
  843. }
  844. return 0;
  845. }
  846. static int __init ir_dev_scope_init(void)
  847. {
  848. int ret;
  849. if (!irq_remapping_enabled)
  850. return 0;
  851. down_write(&dmar_global_lock);
  852. ret = dmar_dev_scope_init();
  853. up_write(&dmar_global_lock);
  854. return ret;
  855. }
  856. rootfs_initcall(ir_dev_scope_init);
  857. static void disable_irq_remapping(void)
  858. {
  859. struct dmar_drhd_unit *drhd;
  860. struct intel_iommu *iommu = NULL;
  861. /*
  862. * Disable Interrupt-remapping for all the DRHD's now.
  863. */
  864. for_each_iommu(iommu, drhd) {
  865. if (!ecap_ir_support(iommu->ecap))
  866. continue;
  867. iommu_disable_irq_remapping(iommu);
  868. }
  869. /*
  870. * Clear Posted-Interrupts capability.
  871. */
  872. if (!disable_irq_post)
  873. intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
  874. }
  875. static int reenable_irq_remapping(int eim)
  876. {
  877. struct dmar_drhd_unit *drhd;
  878. bool setup = false;
  879. struct intel_iommu *iommu = NULL;
  880. for_each_iommu(iommu, drhd)
  881. if (iommu->qi)
  882. dmar_reenable_qi(iommu);
  883. /*
  884. * Setup Interrupt-remapping for all the DRHD's now.
  885. */
  886. for_each_iommu(iommu, drhd) {
  887. if (!ecap_ir_support(iommu->ecap))
  888. continue;
  889. /* Set up interrupt remapping for iommu.*/
  890. iommu_set_irq_remapping(iommu, eim);
  891. iommu_enable_irq_remapping(iommu);
  892. setup = true;
  893. }
  894. if (!setup)
  895. goto error;
  896. set_irq_posting_cap();
  897. return 0;
  898. error:
  899. /*
  900. * handle error condition gracefully here!
  901. */
  902. return -1;
  903. }
  904. /*
  905. * Store the MSI remapping domain pointer in the device if enabled.
  906. *
  907. * This is called from dmar_pci_bus_add_dev() so it works even when DMA
  908. * remapping is disabled. Only update the pointer if the device is not
  909. * already handled by a non default PCI/MSI interrupt domain. This protects
  910. * e.g. VMD devices.
  911. */
  912. void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
  913. {
  914. if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev))
  915. return;
  916. dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
  917. }
  918. static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
  919. {
  920. memset(irte, 0, sizeof(*irte));
  921. irte->present = 1;
  922. irte->dst_mode = apic->irq_dest_mode;
  923. /*
  924. * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
  925. * actual level or edge trigger will be setup in the IO-APIC
  926. * RTE. This will help simplify level triggered irq migration.
  927. * For more details, see the comments (in io_apic.c) explainig IO-APIC
  928. * irq migration in the presence of interrupt-remapping.
  929. */
  930. irte->trigger_mode = 0;
  931. irte->dlvry_mode = apic->irq_delivery_mode;
  932. irte->vector = vector;
  933. irte->dest_id = IRTE_DEST(dest);
  934. irte->redir_hint = 1;
  935. }
  936. static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
  937. {
  938. if (!info)
  939. return NULL;
  940. switch (info->type) {
  941. case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT:
  942. return map_ioapic_to_ir(info->devid);
  943. case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT:
  944. return map_hpet_to_ir(info->devid);
  945. default:
  946. WARN_ON_ONCE(1);
  947. return NULL;
  948. }
  949. }
  950. struct irq_remap_ops intel_irq_remap_ops = {
  951. .prepare = intel_prepare_irq_remapping,
  952. .enable = intel_enable_irq_remapping,
  953. .disable = disable_irq_remapping,
  954. .reenable = reenable_irq_remapping,
  955. .enable_faulting = enable_drhd_fault_handling,
  956. .get_irq_domain = intel_get_irq_domain,
  957. };
  958. static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
  959. {
  960. struct intel_ir_data *ir_data = irqd->chip_data;
  961. struct irte *irte = &ir_data->irte_entry;
  962. struct irq_cfg *cfg = irqd_cfg(irqd);
  963. /*
  964. * Atomically updates the IRTE with the new destination, vector
  965. * and flushes the interrupt entry cache.
  966. */
  967. irte->vector = cfg->vector;
  968. irte->dest_id = IRTE_DEST(cfg->dest_apicid);
  969. /* Update the hardware only if the interrupt is in remapped mode. */
  970. if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
  971. modify_irte(&ir_data->irq_2_iommu, irte);
  972. }
  973. /*
  974. * Migrate the IO-APIC irq in the presence of intr-remapping.
  975. *
  976. * For both level and edge triggered, irq migration is a simple atomic
  977. * update(of vector and cpu destination) of IRTE and flush the hardware cache.
  978. *
  979. * For level triggered, we eliminate the io-apic RTE modification (with the
  980. * updated vector information), by using a virtual vector (io-apic pin number).
  981. * Real vector that is used for interrupting cpu will be coming from
  982. * the interrupt-remapping table entry.
  983. *
  984. * As the migration is a simple atomic update of IRTE, the same mechanism
  985. * is used to migrate MSI irq's in the presence of interrupt-remapping.
  986. */
  987. static int
  988. intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
  989. bool force)
  990. {
  991. struct irq_data *parent = data->parent_data;
  992. struct irq_cfg *cfg = irqd_cfg(data);
  993. int ret;
  994. ret = parent->chip->irq_set_affinity(parent, mask, force);
  995. if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
  996. return ret;
  997. intel_ir_reconfigure_irte(data, false);
  998. /*
  999. * After this point, all the interrupts will start arriving
  1000. * at the new destination. So, time to cleanup the previous
  1001. * vector allocation.
  1002. */
  1003. send_cleanup_vector(cfg);
  1004. return IRQ_SET_MASK_OK_DONE;
  1005. }
  1006. static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
  1007. struct msi_msg *msg)
  1008. {
  1009. struct intel_ir_data *ir_data = irq_data->chip_data;
  1010. *msg = ir_data->msi_entry;
  1011. }
  1012. static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
  1013. {
  1014. struct intel_ir_data *ir_data = data->chip_data;
  1015. struct vcpu_data *vcpu_pi_info = info;
  1016. /* stop posting interrupts, back to remapping mode */
  1017. if (!vcpu_pi_info) {
  1018. modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
  1019. } else {
  1020. struct irte irte_pi;
  1021. /*
  1022. * We are not caching the posted interrupt entry. We
  1023. * copy the data from the remapped entry and modify
  1024. * the fields which are relevant for posted mode. The
  1025. * cached remapped entry is used for switching back to
  1026. * remapped mode.
  1027. */
  1028. memset(&irte_pi, 0, sizeof(irte_pi));
  1029. dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
  1030. /* Update the posted mode fields */
  1031. irte_pi.p_pst = 1;
  1032. irte_pi.p_urgent = 0;
  1033. irte_pi.p_vector = vcpu_pi_info->vector;
  1034. irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
  1035. (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
  1036. irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
  1037. ~(-1UL << PDA_HIGH_BIT);
  1038. modify_irte(&ir_data->irq_2_iommu, &irte_pi);
  1039. }
  1040. return 0;
  1041. }
  1042. static struct irq_chip intel_ir_chip = {
  1043. .name = "INTEL-IR",
  1044. .irq_ack = apic_ack_irq,
  1045. .irq_set_affinity = intel_ir_set_affinity,
  1046. .irq_compose_msi_msg = intel_ir_compose_msi_msg,
  1047. .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
  1048. };
  1049. static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
  1050. struct irq_cfg *irq_cfg,
  1051. struct irq_alloc_info *info,
  1052. int index, int sub_handle)
  1053. {
  1054. struct IR_IO_APIC_route_entry *entry;
  1055. struct irte *irte = &data->irte_entry;
  1056. struct msi_msg *msg = &data->msi_entry;
  1057. prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
  1058. switch (info->type) {
  1059. case X86_IRQ_ALLOC_TYPE_IOAPIC:
  1060. /* Set source-id of interrupt request */
  1061. set_ioapic_sid(irte, info->devid);
  1062. apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
  1063. info->devid, irte->present, irte->fpd,
  1064. irte->dst_mode, irte->redir_hint,
  1065. irte->trigger_mode, irte->dlvry_mode,
  1066. irte->avail, irte->vector, irte->dest_id,
  1067. irte->sid, irte->sq, irte->svt);
  1068. entry = (struct IR_IO_APIC_route_entry *)info->ioapic.entry;
  1069. info->ioapic.entry = NULL;
  1070. memset(entry, 0, sizeof(*entry));
  1071. entry->index2 = (index >> 15) & 0x1;
  1072. entry->zero = 0;
  1073. entry->format = 1;
  1074. entry->index = (index & 0x7fff);
  1075. /*
  1076. * IO-APIC RTE will be configured with virtual vector.
  1077. * irq handler will do the explicit EOI to the io-apic.
  1078. */
  1079. entry->vector = info->ioapic.pin;
  1080. entry->mask = 0; /* enable IRQ */
  1081. entry->trigger = info->ioapic.trigger;
  1082. entry->polarity = info->ioapic.polarity;
  1083. if (info->ioapic.trigger)
  1084. entry->mask = 1; /* Mask level triggered irqs. */
  1085. break;
  1086. case X86_IRQ_ALLOC_TYPE_HPET:
  1087. case X86_IRQ_ALLOC_TYPE_PCI_MSI:
  1088. case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
  1089. if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
  1090. set_hpet_sid(irte, info->devid);
  1091. else
  1092. set_msi_sid(irte, msi_desc_to_pci_dev(info->desc));
  1093. msg->address_hi = MSI_ADDR_BASE_HI;
  1094. msg->data = sub_handle;
  1095. msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
  1096. MSI_ADDR_IR_SHV |
  1097. MSI_ADDR_IR_INDEX1(index) |
  1098. MSI_ADDR_IR_INDEX2(index);
  1099. break;
  1100. default:
  1101. BUG_ON(1);
  1102. break;
  1103. }
  1104. }
  1105. static void intel_free_irq_resources(struct irq_domain *domain,
  1106. unsigned int virq, unsigned int nr_irqs)
  1107. {
  1108. struct irq_data *irq_data;
  1109. struct intel_ir_data *data;
  1110. struct irq_2_iommu *irq_iommu;
  1111. unsigned long flags;
  1112. int i;
  1113. for (i = 0; i < nr_irqs; i++) {
  1114. irq_data = irq_domain_get_irq_data(domain, virq + i);
  1115. if (irq_data && irq_data->chip_data) {
  1116. data = irq_data->chip_data;
  1117. irq_iommu = &data->irq_2_iommu;
  1118. raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  1119. clear_entries(irq_iommu);
  1120. raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  1121. irq_domain_reset_irq_data(irq_data);
  1122. kfree(data);
  1123. }
  1124. }
  1125. }
  1126. static int intel_irq_remapping_alloc(struct irq_domain *domain,
  1127. unsigned int virq, unsigned int nr_irqs,
  1128. void *arg)
  1129. {
  1130. struct intel_iommu *iommu = domain->host_data;
  1131. struct irq_alloc_info *info = arg;
  1132. struct intel_ir_data *data, *ird;
  1133. struct irq_data *irq_data;
  1134. struct irq_cfg *irq_cfg;
  1135. int i, ret, index;
  1136. if (!info || !iommu)
  1137. return -EINVAL;
  1138. if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
  1139. info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
  1140. return -EINVAL;
  1141. /*
  1142. * With IRQ remapping enabled, don't need contiguous CPU vectors
  1143. * to support multiple MSI interrupts.
  1144. */
  1145. if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
  1146. info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
  1147. ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
  1148. if (ret < 0)
  1149. return ret;
  1150. ret = -ENOMEM;
  1151. data = kzalloc(sizeof(*data), GFP_KERNEL);
  1152. if (!data)
  1153. goto out_free_parent;
  1154. down_read(&dmar_global_lock);
  1155. index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
  1156. up_read(&dmar_global_lock);
  1157. if (index < 0) {
  1158. pr_warn("Failed to allocate IRTE\n");
  1159. kfree(data);
  1160. goto out_free_parent;
  1161. }
  1162. for (i = 0; i < nr_irqs; i++) {
  1163. irq_data = irq_domain_get_irq_data(domain, virq + i);
  1164. irq_cfg = irqd_cfg(irq_data);
  1165. if (!irq_data || !irq_cfg) {
  1166. if (!i)
  1167. kfree(data);
  1168. ret = -EINVAL;
  1169. goto out_free_data;
  1170. }
  1171. if (i > 0) {
  1172. ird = kzalloc(sizeof(*ird), GFP_KERNEL);
  1173. if (!ird)
  1174. goto out_free_data;
  1175. /* Initialize the common data */
  1176. ird->irq_2_iommu = data->irq_2_iommu;
  1177. ird->irq_2_iommu.sub_handle = i;
  1178. } else {
  1179. ird = data;
  1180. }
  1181. irq_data->hwirq = (index << 16) + i;
  1182. irq_data->chip_data = ird;
  1183. irq_data->chip = &intel_ir_chip;
  1184. intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
  1185. irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
  1186. }
  1187. return 0;
  1188. out_free_data:
  1189. intel_free_irq_resources(domain, virq, i);
  1190. out_free_parent:
  1191. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  1192. return ret;
  1193. }
  1194. static void intel_irq_remapping_free(struct irq_domain *domain,
  1195. unsigned int virq, unsigned int nr_irqs)
  1196. {
  1197. intel_free_irq_resources(domain, virq, nr_irqs);
  1198. irq_domain_free_irqs_common(domain, virq, nr_irqs);
  1199. }
  1200. static int intel_irq_remapping_activate(struct irq_domain *domain,
  1201. struct irq_data *irq_data, bool reserve)
  1202. {
  1203. intel_ir_reconfigure_irte(irq_data, true);
  1204. return 0;
  1205. }
  1206. static void intel_irq_remapping_deactivate(struct irq_domain *domain,
  1207. struct irq_data *irq_data)
  1208. {
  1209. struct intel_ir_data *data = irq_data->chip_data;
  1210. struct irte entry;
  1211. memset(&entry, 0, sizeof(entry));
  1212. modify_irte(&data->irq_2_iommu, &entry);
  1213. }
  1214. static const struct irq_domain_ops intel_ir_domain_ops = {
  1215. .alloc = intel_irq_remapping_alloc,
  1216. .free = intel_irq_remapping_free,
  1217. .activate = intel_irq_remapping_activate,
  1218. .deactivate = intel_irq_remapping_deactivate,
  1219. };
  1220. /*
  1221. * Support of Interrupt Remapping Unit Hotplug
  1222. */
  1223. static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
  1224. {
  1225. int ret;
  1226. int eim = x2apic_enabled();
  1227. if (eim && !ecap_eim_support(iommu->ecap)) {
  1228. pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
  1229. iommu->reg_phys, iommu->ecap);
  1230. return -ENODEV;
  1231. }
  1232. if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
  1233. pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
  1234. iommu->reg_phys);
  1235. return -ENODEV;
  1236. }
  1237. /* TODO: check all IOAPICs are covered by IOMMU */
  1238. /* Setup Interrupt-remapping now. */
  1239. ret = intel_setup_irq_remapping(iommu);
  1240. if (ret) {
  1241. pr_err("Failed to setup irq remapping for %s\n",
  1242. iommu->name);
  1243. intel_teardown_irq_remapping(iommu);
  1244. ir_remove_ioapic_hpet_scope(iommu);
  1245. } else {
  1246. iommu_enable_irq_remapping(iommu);
  1247. }
  1248. return ret;
  1249. }
  1250. int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
  1251. {
  1252. int ret = 0;
  1253. struct intel_iommu *iommu = dmaru->iommu;
  1254. if (!irq_remapping_enabled)
  1255. return 0;
  1256. if (iommu == NULL)
  1257. return -EINVAL;
  1258. if (!ecap_ir_support(iommu->ecap))
  1259. return 0;
  1260. if (irq_remapping_cap(IRQ_POSTING_CAP) &&
  1261. !cap_pi_support(iommu->cap))
  1262. return -EBUSY;
  1263. if (insert) {
  1264. if (!iommu->ir_table)
  1265. ret = dmar_ir_add(dmaru, iommu);
  1266. } else {
  1267. if (iommu->ir_table) {
  1268. if (!bitmap_empty(iommu->ir_table->bitmap,
  1269. INTR_REMAP_TABLE_ENTRIES)) {
  1270. ret = -EBUSY;
  1271. } else {
  1272. iommu_disable_irq_remapping(iommu);
  1273. intel_teardown_irq_remapping(iommu);
  1274. ir_remove_ioapic_hpet_scope(iommu);
  1275. }
  1276. }
  1277. }
  1278. return ret;
  1279. }