debugfs.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright © 2018 Intel Corporation.
  4. *
  5. * Authors: Gayatri Kammela <gayatri.kammela@intel.com>
  6. * Sohil Mehta <sohil.mehta@intel.com>
  7. * Jacob Pan <jacob.jun.pan@linux.intel.com>
  8. * Lu Baolu <baolu.lu@linux.intel.com>
  9. */
  10. #include <linux/debugfs.h>
  11. #include <linux/dmar.h>
  12. #include <linux/intel-iommu.h>
  13. #include <linux/pci.h>
  14. #include <asm/irq_remapping.h>
  15. #include "pasid.h"
  16. struct tbl_walk {
  17. u16 bus;
  18. u16 devfn;
  19. u32 pasid;
  20. struct root_entry *rt_entry;
  21. struct context_entry *ctx_entry;
  22. struct pasid_entry *pasid_tbl_entry;
  23. };
  24. struct iommu_regset {
  25. int offset;
  26. const char *regs;
  27. };
  28. #define IOMMU_REGSET_ENTRY(_reg_) \
  29. { DMAR_##_reg_##_REG, __stringify(_reg_) }
  30. static const struct iommu_regset iommu_regs_32[] = {
  31. IOMMU_REGSET_ENTRY(VER),
  32. IOMMU_REGSET_ENTRY(GCMD),
  33. IOMMU_REGSET_ENTRY(GSTS),
  34. IOMMU_REGSET_ENTRY(FSTS),
  35. IOMMU_REGSET_ENTRY(FECTL),
  36. IOMMU_REGSET_ENTRY(FEDATA),
  37. IOMMU_REGSET_ENTRY(FEADDR),
  38. IOMMU_REGSET_ENTRY(FEUADDR),
  39. IOMMU_REGSET_ENTRY(PMEN),
  40. IOMMU_REGSET_ENTRY(PLMBASE),
  41. IOMMU_REGSET_ENTRY(PLMLIMIT),
  42. IOMMU_REGSET_ENTRY(ICS),
  43. IOMMU_REGSET_ENTRY(PRS),
  44. IOMMU_REGSET_ENTRY(PECTL),
  45. IOMMU_REGSET_ENTRY(PEDATA),
  46. IOMMU_REGSET_ENTRY(PEADDR),
  47. IOMMU_REGSET_ENTRY(PEUADDR),
  48. };
  49. static const struct iommu_regset iommu_regs_64[] = {
  50. IOMMU_REGSET_ENTRY(CAP),
  51. IOMMU_REGSET_ENTRY(ECAP),
  52. IOMMU_REGSET_ENTRY(RTADDR),
  53. IOMMU_REGSET_ENTRY(CCMD),
  54. IOMMU_REGSET_ENTRY(AFLOG),
  55. IOMMU_REGSET_ENTRY(PHMBASE),
  56. IOMMU_REGSET_ENTRY(PHMLIMIT),
  57. IOMMU_REGSET_ENTRY(IQH),
  58. IOMMU_REGSET_ENTRY(IQT),
  59. IOMMU_REGSET_ENTRY(IQA),
  60. IOMMU_REGSET_ENTRY(IRTA),
  61. IOMMU_REGSET_ENTRY(PQH),
  62. IOMMU_REGSET_ENTRY(PQT),
  63. IOMMU_REGSET_ENTRY(PQA),
  64. IOMMU_REGSET_ENTRY(MTRRCAP),
  65. IOMMU_REGSET_ENTRY(MTRRDEF),
  66. IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
  67. IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
  68. IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
  69. IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
  70. IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
  71. IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
  72. IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
  73. IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
  74. IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
  75. IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
  76. IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
  77. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
  78. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
  79. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
  80. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
  81. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
  82. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
  83. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
  84. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
  85. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
  86. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
  87. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
  88. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
  89. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
  90. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
  91. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
  92. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
  93. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
  94. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
  95. IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
  96. IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
  97. IOMMU_REGSET_ENTRY(VCCAP),
  98. IOMMU_REGSET_ENTRY(VCMD),
  99. IOMMU_REGSET_ENTRY(VCRSP),
  100. };
  101. static int iommu_regset_show(struct seq_file *m, void *unused)
  102. {
  103. struct dmar_drhd_unit *drhd;
  104. struct intel_iommu *iommu;
  105. unsigned long flag;
  106. int i, ret = 0;
  107. u64 value;
  108. rcu_read_lock();
  109. for_each_active_iommu(iommu, drhd) {
  110. if (!drhd->reg_base_addr) {
  111. seq_puts(m, "IOMMU: Invalid base address\n");
  112. ret = -EINVAL;
  113. goto out;
  114. }
  115. seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
  116. iommu->name, drhd->reg_base_addr);
  117. seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
  118. /*
  119. * Publish the contents of the 64-bit hardware registers
  120. * by adding the offset to the pointer (virtual address).
  121. */
  122. raw_spin_lock_irqsave(&iommu->register_lock, flag);
  123. for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
  124. value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
  125. seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
  126. iommu_regs_32[i].regs, iommu_regs_32[i].offset,
  127. value);
  128. }
  129. for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
  130. value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
  131. seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
  132. iommu_regs_64[i].regs, iommu_regs_64[i].offset,
  133. value);
  134. }
  135. raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
  136. seq_putc(m, '\n');
  137. }
  138. out:
  139. rcu_read_unlock();
  140. return ret;
  141. }
  142. DEFINE_SHOW_ATTRIBUTE(iommu_regset);
  143. static inline void print_tbl_walk(struct seq_file *m)
  144. {
  145. struct tbl_walk *tbl_wlk = m->private;
  146. seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
  147. tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
  148. PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
  149. tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
  150. tbl_wlk->ctx_entry->lo);
  151. /*
  152. * A legacy mode DMAR doesn't support PASID, hence default it to -1
  153. * indicating that it's invalid. Also, default all PASID related fields
  154. * to 0.
  155. */
  156. if (!tbl_wlk->pasid_tbl_entry)
  157. seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
  158. (u64)0, (u64)0, (u64)0);
  159. else
  160. seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
  161. tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
  162. tbl_wlk->pasid_tbl_entry->val[1],
  163. tbl_wlk->pasid_tbl_entry->val[0]);
  164. }
  165. static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
  166. u16 dir_idx)
  167. {
  168. struct tbl_walk *tbl_wlk = m->private;
  169. u8 tbl_idx;
  170. for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
  171. if (pasid_pte_is_present(tbl_entry)) {
  172. tbl_wlk->pasid_tbl_entry = tbl_entry;
  173. tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
  174. print_tbl_walk(m);
  175. }
  176. tbl_entry++;
  177. }
  178. }
  179. static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
  180. u16 pasid_dir_size)
  181. {
  182. struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
  183. struct pasid_entry *pasid_tbl;
  184. u16 dir_idx;
  185. for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
  186. pasid_tbl = get_pasid_table_from_pde(dir_entry);
  187. if (pasid_tbl)
  188. pasid_tbl_walk(m, pasid_tbl, dir_idx);
  189. dir_entry++;
  190. }
  191. }
  192. static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
  193. {
  194. struct context_entry *context;
  195. u16 devfn, pasid_dir_size;
  196. u64 pasid_dir_ptr;
  197. for (devfn = 0; devfn < 256; devfn++) {
  198. struct tbl_walk tbl_wlk = {0};
  199. /*
  200. * Scalable mode root entry points to upper scalable mode
  201. * context table and lower scalable mode context table. Each
  202. * scalable mode context table has 128 context entries where as
  203. * legacy mode context table has 256 context entries. So in
  204. * scalable mode, the context entries for former 128 devices are
  205. * in the lower scalable mode context table, while the latter
  206. * 128 devices are in the upper scalable mode context table.
  207. * In scalable mode, when devfn > 127, iommu_context_addr()
  208. * automatically refers to upper scalable mode context table and
  209. * hence the caller doesn't have to worry about differences
  210. * between scalable mode and non scalable mode.
  211. */
  212. context = iommu_context_addr(iommu, bus, devfn, 0);
  213. if (!context)
  214. return;
  215. if (!context_present(context))
  216. continue;
  217. tbl_wlk.bus = bus;
  218. tbl_wlk.devfn = devfn;
  219. tbl_wlk.rt_entry = &iommu->root_entry[bus];
  220. tbl_wlk.ctx_entry = context;
  221. m->private = &tbl_wlk;
  222. if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
  223. pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
  224. pasid_dir_size = get_pasid_dir_size(context);
  225. pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
  226. continue;
  227. }
  228. print_tbl_walk(m);
  229. }
  230. }
  231. static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
  232. {
  233. unsigned long flags;
  234. u16 bus;
  235. spin_lock_irqsave(&iommu->lock, flags);
  236. seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
  237. (u64)virt_to_phys(iommu->root_entry));
  238. seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
  239. /*
  240. * No need to check if the root entry is present or not because
  241. * iommu_context_addr() performs the same check before returning
  242. * context entry.
  243. */
  244. for (bus = 0; bus < 256; bus++)
  245. ctx_tbl_walk(m, iommu, bus);
  246. spin_unlock_irqrestore(&iommu->lock, flags);
  247. }
  248. static int dmar_translation_struct_show(struct seq_file *m, void *unused)
  249. {
  250. struct dmar_drhd_unit *drhd;
  251. struct intel_iommu *iommu;
  252. u32 sts;
  253. rcu_read_lock();
  254. for_each_active_iommu(iommu, drhd) {
  255. sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
  256. if (!(sts & DMA_GSTS_TES)) {
  257. seq_printf(m, "DMA Remapping is not enabled on %s\n",
  258. iommu->name);
  259. continue;
  260. }
  261. root_tbl_walk(m, iommu);
  262. seq_putc(m, '\n');
  263. }
  264. rcu_read_unlock();
  265. return 0;
  266. }
  267. DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
  268. static inline unsigned long level_to_directory_size(int level)
  269. {
  270. return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
  271. }
  272. static inline void
  273. dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
  274. {
  275. seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n",
  276. iova >> VTD_PAGE_SHIFT, path[5], path[4],
  277. path[3], path[2], path[1]);
  278. }
  279. static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
  280. int level, unsigned long start,
  281. u64 *path)
  282. {
  283. int i;
  284. if (level > 5 || level < 1)
  285. return;
  286. for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
  287. i++, pde++, start += level_to_directory_size(level)) {
  288. if (!dma_pte_present(pde))
  289. continue;
  290. path[level] = pde->val;
  291. if (dma_pte_superpage(pde) || level == 1)
  292. dump_page_info(m, start, path);
  293. else
  294. pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
  295. level - 1, start, path);
  296. path[level] = 0;
  297. }
  298. }
  299. static int show_device_domain_translation(struct device *dev, void *data)
  300. {
  301. struct dmar_domain *domain = find_domain(dev);
  302. struct seq_file *m = data;
  303. u64 path[6] = { 0 };
  304. if (!domain)
  305. return 0;
  306. seq_printf(m, "Device %s with pasid %d @0x%llx\n",
  307. dev_name(dev), domain->default_pasid,
  308. (u64)virt_to_phys(domain->pgd));
  309. seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n");
  310. pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path);
  311. seq_putc(m, '\n');
  312. return 0;
  313. }
  314. static int domain_translation_struct_show(struct seq_file *m, void *unused)
  315. {
  316. unsigned long flags;
  317. int ret;
  318. spin_lock_irqsave(&device_domain_lock, flags);
  319. ret = bus_for_each_dev(&pci_bus_type, NULL, m,
  320. show_device_domain_translation);
  321. spin_unlock_irqrestore(&device_domain_lock, flags);
  322. return ret;
  323. }
  324. DEFINE_SHOW_ATTRIBUTE(domain_translation_struct);
  325. static void invalidation_queue_entry_show(struct seq_file *m,
  326. struct intel_iommu *iommu)
  327. {
  328. int index, shift = qi_shift(iommu);
  329. struct qi_desc *desc;
  330. int offset;
  331. if (ecap_smts(iommu->ecap))
  332. seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n");
  333. else
  334. seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n");
  335. for (index = 0; index < QI_LENGTH; index++) {
  336. offset = index << shift;
  337. desc = iommu->qi->desc + offset;
  338. if (ecap_smts(iommu->ecap))
  339. seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n",
  340. index, desc->qw0, desc->qw1,
  341. desc->qw2, desc->qw3,
  342. iommu->qi->desc_status[index]);
  343. else
  344. seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n",
  345. index, desc->qw0, desc->qw1,
  346. iommu->qi->desc_status[index]);
  347. }
  348. }
  349. static int invalidation_queue_show(struct seq_file *m, void *unused)
  350. {
  351. struct dmar_drhd_unit *drhd;
  352. struct intel_iommu *iommu;
  353. unsigned long flags;
  354. struct q_inval *qi;
  355. int shift;
  356. rcu_read_lock();
  357. for_each_active_iommu(iommu, drhd) {
  358. qi = iommu->qi;
  359. shift = qi_shift(iommu);
  360. if (!qi || !ecap_qis(iommu->ecap))
  361. continue;
  362. seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
  363. raw_spin_lock_irqsave(&qi->q_lock, flags);
  364. seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
  365. (u64)virt_to_phys(qi->desc),
  366. dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
  367. dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
  368. invalidation_queue_entry_show(m, iommu);
  369. raw_spin_unlock_irqrestore(&qi->q_lock, flags);
  370. seq_putc(m, '\n');
  371. }
  372. rcu_read_unlock();
  373. return 0;
  374. }
  375. DEFINE_SHOW_ATTRIBUTE(invalidation_queue);
  376. #ifdef CONFIG_IRQ_REMAP
  377. static void ir_tbl_remap_entry_show(struct seq_file *m,
  378. struct intel_iommu *iommu)
  379. {
  380. struct irte *ri_entry;
  381. unsigned long flags;
  382. int idx;
  383. seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n");
  384. raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  385. for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
  386. ri_entry = &iommu->ir_table->base[idx];
  387. if (!ri_entry->present || ri_entry->p_pst)
  388. continue;
  389. seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n",
  390. idx, PCI_BUS_NUM(ri_entry->sid),
  391. PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
  392. ri_entry->dest_id, ri_entry->vector,
  393. ri_entry->high, ri_entry->low);
  394. }
  395. raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  396. }
  397. static void ir_tbl_posted_entry_show(struct seq_file *m,
  398. struct intel_iommu *iommu)
  399. {
  400. struct irte *pi_entry;
  401. unsigned long flags;
  402. int idx;
  403. seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n");
  404. raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
  405. for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
  406. pi_entry = &iommu->ir_table->base[idx];
  407. if (!pi_entry->present || !pi_entry->p_pst)
  408. continue;
  409. seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n",
  410. idx, PCI_BUS_NUM(pi_entry->sid),
  411. PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
  412. pi_entry->pda_h, pi_entry->pda_l << 6,
  413. pi_entry->vector, pi_entry->high,
  414. pi_entry->low);
  415. }
  416. raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
  417. }
  418. /*
  419. * For active IOMMUs go through the Interrupt remapping
  420. * table and print valid entries in a table format for
  421. * Remapped and Posted Interrupts.
  422. */
  423. static int ir_translation_struct_show(struct seq_file *m, void *unused)
  424. {
  425. struct dmar_drhd_unit *drhd;
  426. struct intel_iommu *iommu;
  427. u64 irta;
  428. u32 sts;
  429. rcu_read_lock();
  430. for_each_active_iommu(iommu, drhd) {
  431. if (!ecap_ir_support(iommu->ecap))
  432. continue;
  433. seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
  434. iommu->name);
  435. sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
  436. if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
  437. irta = virt_to_phys(iommu->ir_table->base);
  438. seq_printf(m, " IR table address:%llx\n", irta);
  439. ir_tbl_remap_entry_show(m, iommu);
  440. } else {
  441. seq_puts(m, "Interrupt Remapping is not enabled\n");
  442. }
  443. seq_putc(m, '\n');
  444. }
  445. seq_puts(m, "****\n\n");
  446. for_each_active_iommu(iommu, drhd) {
  447. if (!cap_pi_support(iommu->cap))
  448. continue;
  449. seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
  450. iommu->name);
  451. if (iommu->ir_table) {
  452. irta = virt_to_phys(iommu->ir_table->base);
  453. seq_printf(m, " IR table address:%llx\n", irta);
  454. ir_tbl_posted_entry_show(m, iommu);
  455. } else {
  456. seq_puts(m, "Interrupt Remapping is not enabled\n");
  457. }
  458. seq_putc(m, '\n');
  459. }
  460. rcu_read_unlock();
  461. return 0;
  462. }
  463. DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
  464. #endif
  465. void __init intel_iommu_debugfs_init(void)
  466. {
  467. struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
  468. iommu_debugfs_dir);
  469. debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
  470. &iommu_regset_fops);
  471. debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
  472. NULL, &dmar_translation_struct_fops);
  473. debugfs_create_file("domain_translation_struct", 0444,
  474. intel_iommu_debug, NULL,
  475. &domain_translation_struct_fops);
  476. debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug,
  477. NULL, &invalidation_queue_fops);
  478. #ifdef CONFIG_IRQ_REMAP
  479. debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
  480. NULL, &ir_translation_struct_fops);
  481. #endif
  482. }