fsl_pamu.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. *
  4. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  5. */
  6. #ifndef __FSL_PAMU_H
  7. #define __FSL_PAMU_H
  8. #include <linux/iommu.h>
  9. #include <linux/pci.h>
  10. #include <asm/fsl_pamu_stash.h>
  11. /* Bit Field macros
  12. * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load
  13. */
  14. #define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m)))
  15. #define get_bf(v, m) (((v) & (m)) >> m##_SHIFT)
  16. /* PAMU CCSR space */
  17. #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
  18. #define PAMU_PE 0x40000000 /* enable PAMU */
  19. /* PAMU_OFFSET to the next pamu space in ccsr */
  20. #define PAMU_OFFSET 0x1000
  21. #define PAMU_MMAP_REGS_BASE 0
  22. struct pamu_mmap_regs {
  23. u32 ppbah;
  24. u32 ppbal;
  25. u32 pplah;
  26. u32 pplal;
  27. u32 spbah;
  28. u32 spbal;
  29. u32 splah;
  30. u32 splal;
  31. u32 obah;
  32. u32 obal;
  33. u32 olah;
  34. u32 olal;
  35. };
  36. /* PAMU Error Registers */
  37. #define PAMU_POES1 0x0040
  38. #define PAMU_POES2 0x0044
  39. #define PAMU_POEAH 0x0048
  40. #define PAMU_POEAL 0x004C
  41. #define PAMU_AVS1 0x0050
  42. #define PAMU_AVS1_AV 0x1
  43. #define PAMU_AVS1_OTV 0x6
  44. #define PAMU_AVS1_APV 0x78
  45. #define PAMU_AVS1_WAV 0x380
  46. #define PAMU_AVS1_LAV 0x1c00
  47. #define PAMU_AVS1_GCV 0x2000
  48. #define PAMU_AVS1_PDV 0x4000
  49. #define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
  50. | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
  51. #define PAMU_AVS1_LIODN_SHIFT 16
  52. #define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
  53. #define PAMU_AVS2 0x0054
  54. #define PAMU_AVAH 0x0058
  55. #define PAMU_AVAL 0x005C
  56. #define PAMU_EECTL 0x0060
  57. #define PAMU_EEDIS 0x0064
  58. #define PAMU_EEINTEN 0x0068
  59. #define PAMU_EEDET 0x006C
  60. #define PAMU_EEATTR 0x0070
  61. #define PAMU_EEAHI 0x0074
  62. #define PAMU_EEALO 0x0078
  63. #define PAMU_EEDHI 0X007C
  64. #define PAMU_EEDLO 0x0080
  65. #define PAMU_EECC 0x0084
  66. #define PAMU_UDAD 0x0090
  67. /* PAMU Revision Registers */
  68. #define PAMU_PR1 0x0BF8
  69. #define PAMU_PR2 0x0BFC
  70. /* PAMU version mask */
  71. #define PAMU_PR1_MASK 0xffff
  72. /* PAMU Capabilities Registers */
  73. #define PAMU_PC1 0x0C00
  74. #define PAMU_PC2 0x0C04
  75. #define PAMU_PC3 0x0C08
  76. #define PAMU_PC4 0x0C0C
  77. /* PAMU Control Register */
  78. #define PAMU_PC 0x0C10
  79. /* PAMU control defs */
  80. #define PAMU_CONTROL 0x0C10
  81. #define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */
  82. #define PAMU_PC_PE 0x40000000 /* PAMU enable bit */
  83. #define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
  84. #define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
  85. #define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
  86. #define PAMU_PFA1 0x0C14
  87. #define PAMU_PFA2 0x0C18
  88. #define PAMU_PC2_MLIODN(X) ((X) >> 16)
  89. #define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
  90. /* PAMU Interrupt control and Status Register */
  91. #define PAMU_PICS 0x0C1C
  92. #define PAMU_ACCESS_VIOLATION_STAT 0x8
  93. #define PAMU_ACCESS_VIOLATION_ENABLE 0x4
  94. /* PAMU Debug Registers */
  95. #define PAMU_PD1 0x0F00
  96. #define PAMU_PD2 0x0F04
  97. #define PAMU_PD3 0x0F08
  98. #define PAMU_PD4 0x0F0C
  99. #define PAACE_AP_PERMS_DENIED 0x0
  100. #define PAACE_AP_PERMS_QUERY 0x1
  101. #define PAACE_AP_PERMS_UPDATE 0x2
  102. #define PAACE_AP_PERMS_ALL 0x3
  103. #define PAACE_DD_TO_HOST 0x0
  104. #define PAACE_DD_TO_IO 0x1
  105. #define PAACE_PT_PRIMARY 0x0
  106. #define PAACE_PT_SECONDARY 0x1
  107. #define PAACE_V_INVALID 0x0
  108. #define PAACE_V_VALID 0x1
  109. #define PAACE_MW_SUBWINDOWS 0x1
  110. #define PAACE_WSE_4K 0xB
  111. #define PAACE_WSE_8K 0xC
  112. #define PAACE_WSE_16K 0xD
  113. #define PAACE_WSE_32K 0xE
  114. #define PAACE_WSE_64K 0xF
  115. #define PAACE_WSE_128K 0x10
  116. #define PAACE_WSE_256K 0x11
  117. #define PAACE_WSE_512K 0x12
  118. #define PAACE_WSE_1M 0x13
  119. #define PAACE_WSE_2M 0x14
  120. #define PAACE_WSE_4M 0x15
  121. #define PAACE_WSE_8M 0x16
  122. #define PAACE_WSE_16M 0x17
  123. #define PAACE_WSE_32M 0x18
  124. #define PAACE_WSE_64M 0x19
  125. #define PAACE_WSE_128M 0x1A
  126. #define PAACE_WSE_256M 0x1B
  127. #define PAACE_WSE_512M 0x1C
  128. #define PAACE_WSE_1G 0x1D
  129. #define PAACE_WSE_2G 0x1E
  130. #define PAACE_WSE_4G 0x1F
  131. #define PAACE_DID_PCI_EXPRESS_1 0x00
  132. #define PAACE_DID_PCI_EXPRESS_2 0x01
  133. #define PAACE_DID_PCI_EXPRESS_3 0x02
  134. #define PAACE_DID_PCI_EXPRESS_4 0x03
  135. #define PAACE_DID_LOCAL_BUS 0x04
  136. #define PAACE_DID_SRIO 0x0C
  137. #define PAACE_DID_MEM_1 0x10
  138. #define PAACE_DID_MEM_2 0x11
  139. #define PAACE_DID_MEM_3 0x12
  140. #define PAACE_DID_MEM_4 0x13
  141. #define PAACE_DID_MEM_1_2 0x14
  142. #define PAACE_DID_MEM_3_4 0x15
  143. #define PAACE_DID_MEM_1_4 0x16
  144. #define PAACE_DID_BM_SW_PORTAL 0x18
  145. #define PAACE_DID_PAMU 0x1C
  146. #define PAACE_DID_CAAM 0x21
  147. #define PAACE_DID_QM_SW_PORTAL 0x3C
  148. #define PAACE_DID_CORE0_INST 0x80
  149. #define PAACE_DID_CORE0_DATA 0x81
  150. #define PAACE_DID_CORE1_INST 0x82
  151. #define PAACE_DID_CORE1_DATA 0x83
  152. #define PAACE_DID_CORE2_INST 0x84
  153. #define PAACE_DID_CORE2_DATA 0x85
  154. #define PAACE_DID_CORE3_INST 0x86
  155. #define PAACE_DID_CORE3_DATA 0x87
  156. #define PAACE_DID_CORE4_INST 0x88
  157. #define PAACE_DID_CORE4_DATA 0x89
  158. #define PAACE_DID_CORE5_INST 0x8A
  159. #define PAACE_DID_CORE5_DATA 0x8B
  160. #define PAACE_DID_CORE6_INST 0x8C
  161. #define PAACE_DID_CORE6_DATA 0x8D
  162. #define PAACE_DID_CORE7_INST 0x8E
  163. #define PAACE_DID_CORE7_DATA 0x8F
  164. #define PAACE_DID_BROADCAST 0xFF
  165. #define PAACE_ATM_NO_XLATE 0x00
  166. #define PAACE_ATM_WINDOW_XLATE 0x01
  167. #define PAACE_ATM_PAGE_XLATE 0x02
  168. #define PAACE_ATM_WIN_PG_XLATE (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
  169. #define PAACE_OTM_NO_XLATE 0x00
  170. #define PAACE_OTM_IMMEDIATE 0x01
  171. #define PAACE_OTM_INDEXED 0x02
  172. #define PAACE_OTM_RESERVED 0x03
  173. #define PAACE_M_COHERENCE_REQ 0x01
  174. #define PAACE_PID_0 0x0
  175. #define PAACE_PID_1 0x1
  176. #define PAACE_PID_2 0x2
  177. #define PAACE_PID_3 0x3
  178. #define PAACE_PID_4 0x4
  179. #define PAACE_PID_5 0x5
  180. #define PAACE_PID_6 0x6
  181. #define PAACE_PID_7 0x7
  182. #define PAACE_TCEF_FORMAT0_8B 0x00
  183. #define PAACE_TCEF_FORMAT1_RSVD 0x01
  184. /*
  185. * Hard coded value for the PAACT size to accommodate
  186. * maximum LIODN value generated by u-boot.
  187. */
  188. #define PAACE_NUMBER_ENTRIES 0x500
  189. /* Hard coded value for the SPAACT size */
  190. #define SPAACE_NUMBER_ENTRIES 0x800
  191. #define OME_NUMBER_ENTRIES 16
  192. /* PAACE Bit Field Defines */
  193. #define PPAACE_AF_WBAL 0xfffff000
  194. #define PPAACE_AF_WBAL_SHIFT 12
  195. #define PPAACE_AF_WSE 0x00000fc0
  196. #define PPAACE_AF_WSE_SHIFT 6
  197. #define PPAACE_AF_MW 0x00000020
  198. #define PPAACE_AF_MW_SHIFT 5
  199. #define SPAACE_AF_LIODN 0xffff0000
  200. #define SPAACE_AF_LIODN_SHIFT 16
  201. #define PAACE_AF_AP 0x00000018
  202. #define PAACE_AF_AP_SHIFT 3
  203. #define PAACE_AF_DD 0x00000004
  204. #define PAACE_AF_DD_SHIFT 2
  205. #define PAACE_AF_PT 0x00000002
  206. #define PAACE_AF_PT_SHIFT 1
  207. #define PAACE_AF_V 0x00000001
  208. #define PAACE_AF_V_SHIFT 0
  209. #define PAACE_DA_HOST_CR 0x80
  210. #define PAACE_DA_HOST_CR_SHIFT 7
  211. #define PAACE_IA_CID 0x00FF0000
  212. #define PAACE_IA_CID_SHIFT 16
  213. #define PAACE_IA_WCE 0x000000F0
  214. #define PAACE_IA_WCE_SHIFT 4
  215. #define PAACE_IA_ATM 0x0000000C
  216. #define PAACE_IA_ATM_SHIFT 2
  217. #define PAACE_IA_OTM 0x00000003
  218. #define PAACE_IA_OTM_SHIFT 0
  219. #define PAACE_WIN_TWBAL 0xfffff000
  220. #define PAACE_WIN_TWBAL_SHIFT 12
  221. #define PAACE_WIN_SWSE 0x00000fc0
  222. #define PAACE_WIN_SWSE_SHIFT 6
  223. /* PAMU Data Structures */
  224. /* primary / secondary paact structure */
  225. struct paace {
  226. /* PAACE Offset 0x00 */
  227. u32 wbah; /* only valid for Primary PAACE */
  228. u32 addr_bitfields; /* See P/S PAACE_AF_* */
  229. /* PAACE Offset 0x08 */
  230. /* Interpretation of first 32 bits dependent on DD above */
  231. union {
  232. struct {
  233. /* Destination ID, see PAACE_DID_* defines */
  234. u8 did;
  235. /* Partition ID */
  236. u8 pid;
  237. /* Snoop ID */
  238. u8 snpid;
  239. /* coherency_required : 1 reserved : 7 */
  240. u8 coherency_required; /* See PAACE_DA_* */
  241. } to_host;
  242. struct {
  243. /* Destination ID, see PAACE_DID_* defines */
  244. u8 did;
  245. u8 reserved1;
  246. u16 reserved2;
  247. } to_io;
  248. } domain_attr;
  249. /* Implementation attributes + window count + address & operation translation modes */
  250. u32 impl_attr; /* See PAACE_IA_* */
  251. /* PAACE Offset 0x10 */
  252. /* Translated window base address */
  253. u32 twbah;
  254. u32 win_bitfields; /* See PAACE_WIN_* */
  255. /* PAACE Offset 0x18 */
  256. /* first secondary paace entry */
  257. u32 fspi; /* only valid for Primary PAACE */
  258. union {
  259. struct {
  260. u8 ioea;
  261. u8 moea;
  262. u8 ioeb;
  263. u8 moeb;
  264. } immed_ot;
  265. struct {
  266. u16 reserved;
  267. u16 omi;
  268. } index_ot;
  269. } op_encode;
  270. /* PAACE Offsets 0x20-0x38 */
  271. u32 reserved[8]; /* not currently implemented */
  272. };
  273. /* OME : Operation mapping entry
  274. * MOE : Mapped Operation Encodings
  275. * The operation mapping table is table containing operation mapping entries (OME).
  276. * The index of a particular OME is programmed in the PAACE entry for translation
  277. * in bound I/O operations corresponding to an LIODN. The OMT is used for translation
  278. * specifically in case of the indexed translation mode. Each OME contains a 128
  279. * byte mapped operation encoding (MOE), where each byte represents an MOE.
  280. */
  281. #define NUM_MOE 128
  282. struct ome {
  283. u8 moe[NUM_MOE];
  284. } __packed;
  285. #define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES)
  286. #define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES)
  287. #define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES)
  288. #define PAMU_PAGE_SHIFT 12
  289. #define PAMU_PAGE_SIZE 4096ULL
  290. #define IOE_READ 0x00
  291. #define IOE_READ_IDX 0x00
  292. #define IOE_WRITE 0x81
  293. #define IOE_WRITE_IDX 0x01
  294. #define IOE_EREAD0 0x82 /* Enhanced read type 0 */
  295. #define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
  296. #define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
  297. #define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
  298. #define IOE_DIRECT0 0x84 /* Directive type 0 */
  299. #define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
  300. #define IOE_EREAD1 0x85 /* Enhanced read type 1 */
  301. #define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
  302. #define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
  303. #define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
  304. #define IOE_DIRECT1 0x87 /* Directive type 1 */
  305. #define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
  306. #define IOE_RAC 0x8c /* Read with Atomic clear */
  307. #define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
  308. #define IOE_RAS 0x8d /* Read with Atomic set */
  309. #define IOE_RAS_IDX 0x0d /* Read with Atomic set */
  310. #define IOE_RAD 0x8e /* Read with Atomic decrement */
  311. #define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
  312. #define IOE_RAI 0x8f /* Read with Atomic increment */
  313. #define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
  314. #define EOE_READ 0x00
  315. #define EOE_WRITE 0x01
  316. #define EOE_RAC 0x0c /* Read with Atomic clear */
  317. #define EOE_RAS 0x0d /* Read with Atomic set */
  318. #define EOE_RAD 0x0e /* Read with Atomic decrement */
  319. #define EOE_RAI 0x0f /* Read with Atomic increment */
  320. #define EOE_LDEC 0x10 /* Load external cache */
  321. #define EOE_LDECL 0x11 /* Load external cache with stash lock */
  322. #define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
  323. #define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
  324. #define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
  325. #define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
  326. #define EOE_RSA 0x16 /* Read with stash allocate */
  327. #define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
  328. #define EOE_READI 0x18 /* Read with invalidate */
  329. #define EOE_RWNITC 0x19 /* Read with no intention to cache */
  330. #define EOE_WCI 0x1a /* Write cache inhibited */
  331. #define EOE_WWSA 0x1b /* Write with stash allocate */
  332. #define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
  333. #define EOE_WWSAO 0x1d /* Write with stash allocate only */
  334. #define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
  335. #define EOE_VALID 0x80
  336. /* Function prototypes */
  337. int pamu_domain_init(void);
  338. int pamu_enable_liodn(int liodn);
  339. int pamu_disable_liodn(int liodn);
  340. void pamu_free_subwins(int liodn);
  341. int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
  342. u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid,
  343. u32 subwin_cnt, int prot);
  344. int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
  345. phys_addr_t subwin_size, u32 omi, unsigned long rpn,
  346. uint32_t snoopid, u32 stashid, int enable, int prot);
  347. u32 get_stash_id(u32 stash_dest_hint, u32 vcpu);
  348. void get_ome_index(u32 *omi_index, struct device *dev);
  349. int pamu_update_paace_stash(int liodn, u32 subwin, u32 value);
  350. int pamu_disable_spaace(int liodn, u32 subwin);
  351. u32 pamu_get_max_subwin_cnt(void);
  352. #endif /* __FSL_PAMU_H */