exynos-iommu.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. */
  6. #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  7. #define DEBUG
  8. #endif
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/iommu.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kmemleak.h>
  16. #include <linux/list.h>
  17. #include <linux/of.h>
  18. #include <linux/of_iommu.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/dma-iommu.h>
  24. typedef u32 sysmmu_iova_t;
  25. typedef u32 sysmmu_pte_t;
  26. /* We do not consider super section mapping (16MB) */
  27. #define SECT_ORDER 20
  28. #define LPAGE_ORDER 16
  29. #define SPAGE_ORDER 12
  30. #define SECT_SIZE (1 << SECT_ORDER)
  31. #define LPAGE_SIZE (1 << LPAGE_ORDER)
  32. #define SPAGE_SIZE (1 << SPAGE_ORDER)
  33. #define SECT_MASK (~(SECT_SIZE - 1))
  34. #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  35. #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  36. #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  37. ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  38. #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  39. #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  40. #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  41. ((*(sent) & 3) == 1))
  42. #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  43. #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  44. #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  45. #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  46. /*
  47. * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  48. * v5.0 introduced support for 36bit physical address space by shifting
  49. * all page entry values by 4 bits.
  50. * All SYSMMU controllers in the system support the address spaces of the same
  51. * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  52. * value (0 or 4).
  53. */
  54. static short PG_ENT_SHIFT = -1;
  55. #define SYSMMU_PG_ENT_SHIFT 0
  56. #define SYSMMU_V5_PG_ENT_SHIFT 4
  57. static const sysmmu_pte_t *LV1_PROT;
  58. static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
  59. ((0 << 15) | (0 << 10)), /* no access */
  60. ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
  61. ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
  62. ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
  63. };
  64. static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
  65. (0 << 4), /* no access */
  66. (1 << 4), /* IOMMU_READ only */
  67. (2 << 4), /* IOMMU_WRITE only */
  68. (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
  69. };
  70. static const sysmmu_pte_t *LV2_PROT;
  71. static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
  72. ((0 << 9) | (0 << 4)), /* no access */
  73. ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
  74. ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
  75. ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
  76. };
  77. static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
  78. (0 << 2), /* no access */
  79. (1 << 2), /* IOMMU_READ only */
  80. (2 << 2), /* IOMMU_WRITE only */
  81. (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
  82. };
  83. #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
  84. #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  85. #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  86. #define section_offs(iova) (iova & (SECT_SIZE - 1))
  87. #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
  88. #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
  89. #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
  90. #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
  91. #define NUM_LV1ENTRIES 4096
  92. #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  93. static u32 lv1ent_offset(sysmmu_iova_t iova)
  94. {
  95. return iova >> SECT_ORDER;
  96. }
  97. static u32 lv2ent_offset(sysmmu_iova_t iova)
  98. {
  99. return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  100. }
  101. #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  102. #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  103. #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  104. #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
  105. #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
  106. #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
  107. #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
  108. #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
  109. #define CTRL_ENABLE 0x5
  110. #define CTRL_BLOCK 0x7
  111. #define CTRL_DISABLE 0x0
  112. #define CFG_LRU 0x1
  113. #define CFG_EAP (1 << 2)
  114. #define CFG_QOS(n) ((n & 0xF) << 7)
  115. #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */
  116. #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
  117. #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
  118. /* common registers */
  119. #define REG_MMU_CTRL 0x000
  120. #define REG_MMU_CFG 0x004
  121. #define REG_MMU_STATUS 0x008
  122. #define REG_MMU_VERSION 0x034
  123. #define MMU_MAJ_VER(val) ((val) >> 7)
  124. #define MMU_MIN_VER(val) ((val) & 0x7F)
  125. #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
  126. #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F))
  127. /* v1.x - v3.x registers */
  128. #define REG_MMU_FLUSH 0x00C
  129. #define REG_MMU_FLUSH_ENTRY 0x010
  130. #define REG_PT_BASE_ADDR 0x014
  131. #define REG_INT_STATUS 0x018
  132. #define REG_INT_CLEAR 0x01C
  133. #define REG_PAGE_FAULT_ADDR 0x024
  134. #define REG_AW_FAULT_ADDR 0x028
  135. #define REG_AR_FAULT_ADDR 0x02C
  136. #define REG_DEFAULT_SLAVE_ADDR 0x030
  137. /* v5.x registers */
  138. #define REG_V5_PT_BASE_PFN 0x00C
  139. #define REG_V5_MMU_FLUSH_ALL 0x010
  140. #define REG_V5_MMU_FLUSH_ENTRY 0x014
  141. #define REG_V5_MMU_FLUSH_RANGE 0x018
  142. #define REG_V5_MMU_FLUSH_START 0x020
  143. #define REG_V5_MMU_FLUSH_END 0x024
  144. #define REG_V5_INT_STATUS 0x060
  145. #define REG_V5_INT_CLEAR 0x064
  146. #define REG_V5_FAULT_AR_VA 0x070
  147. #define REG_V5_FAULT_AW_VA 0x080
  148. #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL)
  149. static struct device *dma_dev;
  150. static struct kmem_cache *lv2table_kmem_cache;
  151. static sysmmu_pte_t *zero_lv2_table;
  152. #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
  153. static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
  154. {
  155. return pgtable + lv1ent_offset(iova);
  156. }
  157. static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
  158. {
  159. return (sysmmu_pte_t *)phys_to_virt(
  160. lv2table_base(sent)) + lv2ent_offset(iova);
  161. }
  162. /*
  163. * IOMMU fault information register
  164. */
  165. struct sysmmu_fault_info {
  166. unsigned int bit; /* bit number in STATUS register */
  167. unsigned short addr_reg; /* register to read VA fault address */
  168. const char *name; /* human readable fault name */
  169. unsigned int type; /* fault type for report_iommu_fault */
  170. };
  171. static const struct sysmmu_fault_info sysmmu_faults[] = {
  172. { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
  173. { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
  174. { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
  175. { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
  176. { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
  177. { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
  178. { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
  179. { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
  180. };
  181. static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
  182. { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
  183. { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
  184. { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
  185. { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
  186. { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
  187. { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
  188. { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
  189. { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
  190. { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
  191. { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
  192. };
  193. /*
  194. * This structure is attached to dev->iommu->priv of the master device
  195. * on device add, contains a list of SYSMMU controllers defined by device tree,
  196. * which are bound to given master device. It is usually referenced by 'owner'
  197. * pointer.
  198. */
  199. struct exynos_iommu_owner {
  200. struct list_head controllers; /* list of sysmmu_drvdata.owner_node */
  201. struct iommu_domain *domain; /* domain this device is attached */
  202. struct mutex rpm_lock; /* for runtime pm of all sysmmus */
  203. };
  204. /*
  205. * This structure exynos specific generalization of struct iommu_domain.
  206. * It contains list of SYSMMU controllers from all master devices, which has
  207. * been attached to this domain and page tables of IO address space defined by
  208. * it. It is usually referenced by 'domain' pointer.
  209. */
  210. struct exynos_iommu_domain {
  211. struct list_head clients; /* list of sysmmu_drvdata.domain_node */
  212. sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
  213. short *lv2entcnt; /* free lv2 entry counter for each section */
  214. spinlock_t lock; /* lock for modyfying list of clients */
  215. spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
  216. struct iommu_domain domain; /* generic domain data structure */
  217. };
  218. /*
  219. * This structure hold all data of a single SYSMMU controller, this includes
  220. * hw resources like registers and clocks, pointers and list nodes to connect
  221. * it to all other structures, internal state and parameters read from device
  222. * tree. It is usually referenced by 'data' pointer.
  223. */
  224. struct sysmmu_drvdata {
  225. struct device *sysmmu; /* SYSMMU controller device */
  226. struct device *master; /* master device (owner) */
  227. struct device_link *link; /* runtime PM link to master */
  228. void __iomem *sfrbase; /* our registers */
  229. struct clk *clk; /* SYSMMU's clock */
  230. struct clk *aclk; /* SYSMMU's aclk clock */
  231. struct clk *pclk; /* SYSMMU's pclk clock */
  232. struct clk *clk_master; /* master's device clock */
  233. spinlock_t lock; /* lock for modyfying state */
  234. bool active; /* current status */
  235. struct exynos_iommu_domain *domain; /* domain we belong to */
  236. struct list_head domain_node; /* node for domain clients list */
  237. struct list_head owner_node; /* node for owner controllers list */
  238. phys_addr_t pgtable; /* assigned page table structure */
  239. unsigned int version; /* our version */
  240. struct iommu_device iommu; /* IOMMU core handle */
  241. };
  242. static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
  243. {
  244. return container_of(dom, struct exynos_iommu_domain, domain);
  245. }
  246. static void sysmmu_unblock(struct sysmmu_drvdata *data)
  247. {
  248. writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
  249. }
  250. static bool sysmmu_block(struct sysmmu_drvdata *data)
  251. {
  252. int i = 120;
  253. writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
  254. while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
  255. --i;
  256. if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
  257. sysmmu_unblock(data);
  258. return false;
  259. }
  260. return true;
  261. }
  262. static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
  263. {
  264. if (MMU_MAJ_VER(data->version) < 5)
  265. writel(0x1, data->sfrbase + REG_MMU_FLUSH);
  266. else
  267. writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
  268. }
  269. static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
  270. sysmmu_iova_t iova, unsigned int num_inv)
  271. {
  272. unsigned int i;
  273. if (MMU_MAJ_VER(data->version) < 5) {
  274. for (i = 0; i < num_inv; i++) {
  275. writel((iova & SPAGE_MASK) | 1,
  276. data->sfrbase + REG_MMU_FLUSH_ENTRY);
  277. iova += SPAGE_SIZE;
  278. }
  279. } else {
  280. if (num_inv == 1) {
  281. writel((iova & SPAGE_MASK) | 1,
  282. data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
  283. } else {
  284. writel((iova & SPAGE_MASK),
  285. data->sfrbase + REG_V5_MMU_FLUSH_START);
  286. writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE,
  287. data->sfrbase + REG_V5_MMU_FLUSH_END);
  288. writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE);
  289. }
  290. }
  291. }
  292. static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
  293. {
  294. if (MMU_MAJ_VER(data->version) < 5)
  295. writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
  296. else
  297. writel(pgd >> PAGE_SHIFT,
  298. data->sfrbase + REG_V5_PT_BASE_PFN);
  299. __sysmmu_tlb_invalidate(data);
  300. }
  301. static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
  302. {
  303. BUG_ON(clk_prepare_enable(data->clk_master));
  304. BUG_ON(clk_prepare_enable(data->clk));
  305. BUG_ON(clk_prepare_enable(data->pclk));
  306. BUG_ON(clk_prepare_enable(data->aclk));
  307. }
  308. static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
  309. {
  310. clk_disable_unprepare(data->aclk);
  311. clk_disable_unprepare(data->pclk);
  312. clk_disable_unprepare(data->clk);
  313. clk_disable_unprepare(data->clk_master);
  314. }
  315. static void __sysmmu_get_version(struct sysmmu_drvdata *data)
  316. {
  317. u32 ver;
  318. __sysmmu_enable_clocks(data);
  319. ver = readl(data->sfrbase + REG_MMU_VERSION);
  320. /* controllers on some SoCs don't report proper version */
  321. if (ver == 0x80000001u)
  322. data->version = MAKE_MMU_VER(1, 0);
  323. else
  324. data->version = MMU_RAW_VER(ver);
  325. dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
  326. MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
  327. __sysmmu_disable_clocks(data);
  328. }
  329. static void show_fault_information(struct sysmmu_drvdata *data,
  330. const struct sysmmu_fault_info *finfo,
  331. sysmmu_iova_t fault_addr)
  332. {
  333. sysmmu_pte_t *ent;
  334. dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n",
  335. dev_name(data->master), finfo->name, fault_addr);
  336. dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable);
  337. ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
  338. dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
  339. if (lv1ent_page(ent)) {
  340. ent = page_entry(ent, fault_addr);
  341. dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
  342. }
  343. }
  344. static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
  345. {
  346. /* SYSMMU is in blocked state when interrupt occurred. */
  347. struct sysmmu_drvdata *data = dev_id;
  348. const struct sysmmu_fault_info *finfo;
  349. unsigned int i, n, itype;
  350. sysmmu_iova_t fault_addr = -1;
  351. unsigned short reg_status, reg_clear;
  352. int ret = -ENOSYS;
  353. WARN_ON(!data->active);
  354. if (MMU_MAJ_VER(data->version) < 5) {
  355. reg_status = REG_INT_STATUS;
  356. reg_clear = REG_INT_CLEAR;
  357. finfo = sysmmu_faults;
  358. n = ARRAY_SIZE(sysmmu_faults);
  359. } else {
  360. reg_status = REG_V5_INT_STATUS;
  361. reg_clear = REG_V5_INT_CLEAR;
  362. finfo = sysmmu_v5_faults;
  363. n = ARRAY_SIZE(sysmmu_v5_faults);
  364. }
  365. spin_lock(&data->lock);
  366. clk_enable(data->clk_master);
  367. itype = __ffs(readl(data->sfrbase + reg_status));
  368. for (i = 0; i < n; i++, finfo++)
  369. if (finfo->bit == itype)
  370. break;
  371. /* unknown/unsupported fault */
  372. BUG_ON(i == n);
  373. /* print debug message */
  374. fault_addr = readl(data->sfrbase + finfo->addr_reg);
  375. show_fault_information(data, finfo, fault_addr);
  376. if (data->domain)
  377. ret = report_iommu_fault(&data->domain->domain,
  378. data->master, fault_addr, finfo->type);
  379. /* fault is not recovered by fault handler */
  380. BUG_ON(ret != 0);
  381. writel(1 << itype, data->sfrbase + reg_clear);
  382. sysmmu_unblock(data);
  383. clk_disable(data->clk_master);
  384. spin_unlock(&data->lock);
  385. return IRQ_HANDLED;
  386. }
  387. static void __sysmmu_disable(struct sysmmu_drvdata *data)
  388. {
  389. unsigned long flags;
  390. clk_enable(data->clk_master);
  391. spin_lock_irqsave(&data->lock, flags);
  392. writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
  393. writel(0, data->sfrbase + REG_MMU_CFG);
  394. data->active = false;
  395. spin_unlock_irqrestore(&data->lock, flags);
  396. __sysmmu_disable_clocks(data);
  397. }
  398. static void __sysmmu_init_config(struct sysmmu_drvdata *data)
  399. {
  400. unsigned int cfg;
  401. if (data->version <= MAKE_MMU_VER(3, 1))
  402. cfg = CFG_LRU | CFG_QOS(15);
  403. else if (data->version <= MAKE_MMU_VER(3, 2))
  404. cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
  405. else
  406. cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
  407. cfg |= CFG_EAP; /* enable access protection bits check */
  408. writel(cfg, data->sfrbase + REG_MMU_CFG);
  409. }
  410. static void __sysmmu_enable(struct sysmmu_drvdata *data)
  411. {
  412. unsigned long flags;
  413. __sysmmu_enable_clocks(data);
  414. spin_lock_irqsave(&data->lock, flags);
  415. writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
  416. __sysmmu_init_config(data);
  417. __sysmmu_set_ptbase(data, data->pgtable);
  418. writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
  419. data->active = true;
  420. spin_unlock_irqrestore(&data->lock, flags);
  421. /*
  422. * SYSMMU driver keeps master's clock enabled only for the short
  423. * time, while accessing the registers. For performing address
  424. * translation during DMA transaction it relies on the client
  425. * driver to enable it.
  426. */
  427. clk_disable(data->clk_master);
  428. }
  429. static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
  430. sysmmu_iova_t iova)
  431. {
  432. unsigned long flags;
  433. spin_lock_irqsave(&data->lock, flags);
  434. if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
  435. clk_enable(data->clk_master);
  436. if (sysmmu_block(data)) {
  437. if (data->version >= MAKE_MMU_VER(5, 0))
  438. __sysmmu_tlb_invalidate(data);
  439. else
  440. __sysmmu_tlb_invalidate_entry(data, iova, 1);
  441. sysmmu_unblock(data);
  442. }
  443. clk_disable(data->clk_master);
  444. }
  445. spin_unlock_irqrestore(&data->lock, flags);
  446. }
  447. static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
  448. sysmmu_iova_t iova, size_t size)
  449. {
  450. unsigned long flags;
  451. spin_lock_irqsave(&data->lock, flags);
  452. if (data->active) {
  453. unsigned int num_inv = 1;
  454. clk_enable(data->clk_master);
  455. /*
  456. * L2TLB invalidation required
  457. * 4KB page: 1 invalidation
  458. * 64KB page: 16 invalidations
  459. * 1MB page: 64 invalidations
  460. * because it is set-associative TLB
  461. * with 8-way and 64 sets.
  462. * 1MB page can be cached in one of all sets.
  463. * 64KB page can be one of 16 consecutive sets.
  464. */
  465. if (MMU_MAJ_VER(data->version) == 2)
  466. num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
  467. if (sysmmu_block(data)) {
  468. __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
  469. sysmmu_unblock(data);
  470. }
  471. clk_disable(data->clk_master);
  472. }
  473. spin_unlock_irqrestore(&data->lock, flags);
  474. }
  475. static const struct iommu_ops exynos_iommu_ops;
  476. static int exynos_sysmmu_probe(struct platform_device *pdev)
  477. {
  478. int irq, ret;
  479. struct device *dev = &pdev->dev;
  480. struct sysmmu_drvdata *data;
  481. struct resource *res;
  482. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  483. if (!data)
  484. return -ENOMEM;
  485. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  486. data->sfrbase = devm_ioremap_resource(dev, res);
  487. if (IS_ERR(data->sfrbase))
  488. return PTR_ERR(data->sfrbase);
  489. irq = platform_get_irq(pdev, 0);
  490. if (irq <= 0)
  491. return irq;
  492. ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
  493. dev_name(dev), data);
  494. if (ret) {
  495. dev_err(dev, "Unabled to register handler of irq %d\n", irq);
  496. return ret;
  497. }
  498. data->clk = devm_clk_get(dev, "sysmmu");
  499. if (PTR_ERR(data->clk) == -ENOENT)
  500. data->clk = NULL;
  501. else if (IS_ERR(data->clk))
  502. return PTR_ERR(data->clk);
  503. data->aclk = devm_clk_get(dev, "aclk");
  504. if (PTR_ERR(data->aclk) == -ENOENT)
  505. data->aclk = NULL;
  506. else if (IS_ERR(data->aclk))
  507. return PTR_ERR(data->aclk);
  508. data->pclk = devm_clk_get(dev, "pclk");
  509. if (PTR_ERR(data->pclk) == -ENOENT)
  510. data->pclk = NULL;
  511. else if (IS_ERR(data->pclk))
  512. return PTR_ERR(data->pclk);
  513. if (!data->clk && (!data->aclk || !data->pclk)) {
  514. dev_err(dev, "Failed to get device clock(s)!\n");
  515. return -ENOSYS;
  516. }
  517. data->clk_master = devm_clk_get(dev, "master");
  518. if (PTR_ERR(data->clk_master) == -ENOENT)
  519. data->clk_master = NULL;
  520. else if (IS_ERR(data->clk_master))
  521. return PTR_ERR(data->clk_master);
  522. data->sysmmu = dev;
  523. spin_lock_init(&data->lock);
  524. ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
  525. dev_name(data->sysmmu));
  526. if (ret)
  527. return ret;
  528. iommu_device_set_ops(&data->iommu, &exynos_iommu_ops);
  529. iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode);
  530. ret = iommu_device_register(&data->iommu);
  531. if (ret)
  532. return ret;
  533. platform_set_drvdata(pdev, data);
  534. __sysmmu_get_version(data);
  535. if (PG_ENT_SHIFT < 0) {
  536. if (MMU_MAJ_VER(data->version) < 5) {
  537. PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
  538. LV1_PROT = SYSMMU_LV1_PROT;
  539. LV2_PROT = SYSMMU_LV2_PROT;
  540. } else {
  541. PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
  542. LV1_PROT = SYSMMU_V5_LV1_PROT;
  543. LV2_PROT = SYSMMU_V5_LV2_PROT;
  544. }
  545. }
  546. /*
  547. * use the first registered sysmmu device for performing
  548. * dma mapping operations on iommu page tables (cpu cache flush)
  549. */
  550. if (!dma_dev)
  551. dma_dev = &pdev->dev;
  552. pm_runtime_enable(dev);
  553. return 0;
  554. }
  555. static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
  556. {
  557. struct sysmmu_drvdata *data = dev_get_drvdata(dev);
  558. struct device *master = data->master;
  559. if (master) {
  560. struct exynos_iommu_owner *owner = dev_iommu_priv_get(master);
  561. mutex_lock(&owner->rpm_lock);
  562. if (data->domain) {
  563. dev_dbg(data->sysmmu, "saving state\n");
  564. __sysmmu_disable(data);
  565. }
  566. mutex_unlock(&owner->rpm_lock);
  567. }
  568. return 0;
  569. }
  570. static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
  571. {
  572. struct sysmmu_drvdata *data = dev_get_drvdata(dev);
  573. struct device *master = data->master;
  574. if (master) {
  575. struct exynos_iommu_owner *owner = dev_iommu_priv_get(master);
  576. mutex_lock(&owner->rpm_lock);
  577. if (data->domain) {
  578. dev_dbg(data->sysmmu, "restoring state\n");
  579. __sysmmu_enable(data);
  580. }
  581. mutex_unlock(&owner->rpm_lock);
  582. }
  583. return 0;
  584. }
  585. static const struct dev_pm_ops sysmmu_pm_ops = {
  586. SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
  587. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  588. pm_runtime_force_resume)
  589. };
  590. static const struct of_device_id sysmmu_of_match[] = {
  591. { .compatible = "samsung,exynos-sysmmu", },
  592. { },
  593. };
  594. static struct platform_driver exynos_sysmmu_driver __refdata = {
  595. .probe = exynos_sysmmu_probe,
  596. .driver = {
  597. .name = "exynos-sysmmu",
  598. .of_match_table = sysmmu_of_match,
  599. .pm = &sysmmu_pm_ops,
  600. .suppress_bind_attrs = true,
  601. }
  602. };
  603. static inline void exynos_iommu_set_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
  604. {
  605. dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
  606. DMA_TO_DEVICE);
  607. *ent = cpu_to_le32(val);
  608. dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
  609. DMA_TO_DEVICE);
  610. }
  611. static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
  612. {
  613. struct exynos_iommu_domain *domain;
  614. dma_addr_t handle;
  615. int i;
  616. /* Check if correct PTE offsets are initialized */
  617. BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
  618. domain = kzalloc(sizeof(*domain), GFP_KERNEL);
  619. if (!domain)
  620. return NULL;
  621. if (type == IOMMU_DOMAIN_DMA) {
  622. if (iommu_get_dma_cookie(&domain->domain) != 0)
  623. goto err_pgtable;
  624. } else if (type != IOMMU_DOMAIN_UNMANAGED) {
  625. goto err_pgtable;
  626. }
  627. domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
  628. if (!domain->pgtable)
  629. goto err_dma_cookie;
  630. domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
  631. if (!domain->lv2entcnt)
  632. goto err_counter;
  633. /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
  634. for (i = 0; i < NUM_LV1ENTRIES; i++)
  635. domain->pgtable[i] = ZERO_LV2LINK;
  636. handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
  637. DMA_TO_DEVICE);
  638. /* For mapping page table entries we rely on dma == phys */
  639. BUG_ON(handle != virt_to_phys(domain->pgtable));
  640. if (dma_mapping_error(dma_dev, handle))
  641. goto err_lv2ent;
  642. spin_lock_init(&domain->lock);
  643. spin_lock_init(&domain->pgtablelock);
  644. INIT_LIST_HEAD(&domain->clients);
  645. domain->domain.geometry.aperture_start = 0;
  646. domain->domain.geometry.aperture_end = ~0UL;
  647. domain->domain.geometry.force_aperture = true;
  648. return &domain->domain;
  649. err_lv2ent:
  650. free_pages((unsigned long)domain->lv2entcnt, 1);
  651. err_counter:
  652. free_pages((unsigned long)domain->pgtable, 2);
  653. err_dma_cookie:
  654. if (type == IOMMU_DOMAIN_DMA)
  655. iommu_put_dma_cookie(&domain->domain);
  656. err_pgtable:
  657. kfree(domain);
  658. return NULL;
  659. }
  660. static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
  661. {
  662. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  663. struct sysmmu_drvdata *data, *next;
  664. unsigned long flags;
  665. int i;
  666. WARN_ON(!list_empty(&domain->clients));
  667. spin_lock_irqsave(&domain->lock, flags);
  668. list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
  669. spin_lock(&data->lock);
  670. __sysmmu_disable(data);
  671. data->pgtable = 0;
  672. data->domain = NULL;
  673. list_del_init(&data->domain_node);
  674. spin_unlock(&data->lock);
  675. }
  676. spin_unlock_irqrestore(&domain->lock, flags);
  677. if (iommu_domain->type == IOMMU_DOMAIN_DMA)
  678. iommu_put_dma_cookie(iommu_domain);
  679. dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
  680. DMA_TO_DEVICE);
  681. for (i = 0; i < NUM_LV1ENTRIES; i++)
  682. if (lv1ent_page(domain->pgtable + i)) {
  683. phys_addr_t base = lv2table_base(domain->pgtable + i);
  684. dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
  685. DMA_TO_DEVICE);
  686. kmem_cache_free(lv2table_kmem_cache,
  687. phys_to_virt(base));
  688. }
  689. free_pages((unsigned long)domain->pgtable, 2);
  690. free_pages((unsigned long)domain->lv2entcnt, 1);
  691. kfree(domain);
  692. }
  693. static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
  694. struct device *dev)
  695. {
  696. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  697. struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
  698. phys_addr_t pagetable = virt_to_phys(domain->pgtable);
  699. struct sysmmu_drvdata *data, *next;
  700. unsigned long flags;
  701. if (!has_sysmmu(dev) || owner->domain != iommu_domain)
  702. return;
  703. mutex_lock(&owner->rpm_lock);
  704. list_for_each_entry(data, &owner->controllers, owner_node) {
  705. pm_runtime_get_noresume(data->sysmmu);
  706. if (pm_runtime_active(data->sysmmu))
  707. __sysmmu_disable(data);
  708. pm_runtime_put(data->sysmmu);
  709. }
  710. spin_lock_irqsave(&domain->lock, flags);
  711. list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
  712. spin_lock(&data->lock);
  713. data->pgtable = 0;
  714. data->domain = NULL;
  715. list_del_init(&data->domain_node);
  716. spin_unlock(&data->lock);
  717. }
  718. owner->domain = NULL;
  719. spin_unlock_irqrestore(&domain->lock, flags);
  720. mutex_unlock(&owner->rpm_lock);
  721. dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
  722. &pagetable);
  723. }
  724. static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
  725. struct device *dev)
  726. {
  727. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  728. struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
  729. struct sysmmu_drvdata *data;
  730. phys_addr_t pagetable = virt_to_phys(domain->pgtable);
  731. unsigned long flags;
  732. if (!has_sysmmu(dev))
  733. return -ENODEV;
  734. if (owner->domain)
  735. exynos_iommu_detach_device(owner->domain, dev);
  736. mutex_lock(&owner->rpm_lock);
  737. spin_lock_irqsave(&domain->lock, flags);
  738. list_for_each_entry(data, &owner->controllers, owner_node) {
  739. spin_lock(&data->lock);
  740. data->pgtable = pagetable;
  741. data->domain = domain;
  742. list_add_tail(&data->domain_node, &domain->clients);
  743. spin_unlock(&data->lock);
  744. }
  745. owner->domain = iommu_domain;
  746. spin_unlock_irqrestore(&domain->lock, flags);
  747. list_for_each_entry(data, &owner->controllers, owner_node) {
  748. pm_runtime_get_noresume(data->sysmmu);
  749. if (pm_runtime_active(data->sysmmu))
  750. __sysmmu_enable(data);
  751. pm_runtime_put(data->sysmmu);
  752. }
  753. mutex_unlock(&owner->rpm_lock);
  754. dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
  755. &pagetable);
  756. return 0;
  757. }
  758. static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
  759. sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
  760. {
  761. if (lv1ent_section(sent)) {
  762. WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
  763. return ERR_PTR(-EADDRINUSE);
  764. }
  765. if (lv1ent_fault(sent)) {
  766. dma_addr_t handle;
  767. sysmmu_pte_t *pent;
  768. bool need_flush_flpd_cache = lv1ent_zero(sent);
  769. pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
  770. BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
  771. if (!pent)
  772. return ERR_PTR(-ENOMEM);
  773. exynos_iommu_set_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
  774. kmemleak_ignore(pent);
  775. *pgcounter = NUM_LV2ENTRIES;
  776. handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE,
  777. DMA_TO_DEVICE);
  778. if (dma_mapping_error(dma_dev, handle)) {
  779. kmem_cache_free(lv2table_kmem_cache, pent);
  780. return ERR_PTR(-EADDRINUSE);
  781. }
  782. /*
  783. * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
  784. * FLPD cache may cache the address of zero_l2_table. This
  785. * function replaces the zero_l2_table with new L2 page table
  786. * to write valid mappings.
  787. * Accessing the valid area may cause page fault since FLPD
  788. * cache may still cache zero_l2_table for the valid area
  789. * instead of new L2 page table that has the mapping
  790. * information of the valid area.
  791. * Thus any replacement of zero_l2_table with other valid L2
  792. * page table must involve FLPD cache invalidation for System
  793. * MMU v3.3.
  794. * FLPD cache invalidation is performed with TLB invalidation
  795. * by VPN without blocking. It is safe to invalidate TLB without
  796. * blocking because the target address of TLB invalidation is
  797. * not currently mapped.
  798. */
  799. if (need_flush_flpd_cache) {
  800. struct sysmmu_drvdata *data;
  801. spin_lock(&domain->lock);
  802. list_for_each_entry(data, &domain->clients, domain_node)
  803. sysmmu_tlb_invalidate_flpdcache(data, iova);
  804. spin_unlock(&domain->lock);
  805. }
  806. }
  807. return page_entry(sent, iova);
  808. }
  809. static int lv1set_section(struct exynos_iommu_domain *domain,
  810. sysmmu_pte_t *sent, sysmmu_iova_t iova,
  811. phys_addr_t paddr, int prot, short *pgcnt)
  812. {
  813. if (lv1ent_section(sent)) {
  814. WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
  815. iova);
  816. return -EADDRINUSE;
  817. }
  818. if (lv1ent_page(sent)) {
  819. if (*pgcnt != NUM_LV2ENTRIES) {
  820. WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
  821. iova);
  822. return -EADDRINUSE;
  823. }
  824. kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
  825. *pgcnt = 0;
  826. }
  827. exynos_iommu_set_pte(sent, mk_lv1ent_sect(paddr, prot));
  828. spin_lock(&domain->lock);
  829. if (lv1ent_page_zero(sent)) {
  830. struct sysmmu_drvdata *data;
  831. /*
  832. * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
  833. * entry by speculative prefetch of SLPD which has no mapping.
  834. */
  835. list_for_each_entry(data, &domain->clients, domain_node)
  836. sysmmu_tlb_invalidate_flpdcache(data, iova);
  837. }
  838. spin_unlock(&domain->lock);
  839. return 0;
  840. }
  841. static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
  842. int prot, short *pgcnt)
  843. {
  844. if (size == SPAGE_SIZE) {
  845. if (WARN_ON(!lv2ent_fault(pent)))
  846. return -EADDRINUSE;
  847. exynos_iommu_set_pte(pent, mk_lv2ent_spage(paddr, prot));
  848. *pgcnt -= 1;
  849. } else { /* size == LPAGE_SIZE */
  850. int i;
  851. dma_addr_t pent_base = virt_to_phys(pent);
  852. dma_sync_single_for_cpu(dma_dev, pent_base,
  853. sizeof(*pent) * SPAGES_PER_LPAGE,
  854. DMA_TO_DEVICE);
  855. for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
  856. if (WARN_ON(!lv2ent_fault(pent))) {
  857. if (i > 0)
  858. memset(pent - i, 0, sizeof(*pent) * i);
  859. return -EADDRINUSE;
  860. }
  861. *pent = mk_lv2ent_lpage(paddr, prot);
  862. }
  863. dma_sync_single_for_device(dma_dev, pent_base,
  864. sizeof(*pent) * SPAGES_PER_LPAGE,
  865. DMA_TO_DEVICE);
  866. *pgcnt -= SPAGES_PER_LPAGE;
  867. }
  868. return 0;
  869. }
  870. /*
  871. * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
  872. *
  873. * System MMU v3.x has advanced logic to improve address translation
  874. * performance with caching more page table entries by a page table walk.
  875. * However, the logic has a bug that while caching faulty page table entries,
  876. * System MMU reports page fault if the cached fault entry is hit even though
  877. * the fault entry is updated to a valid entry after the entry is cached.
  878. * To prevent caching faulty page table entries which may be updated to valid
  879. * entries later, the virtual memory manager should care about the workaround
  880. * for the problem. The following describes the workaround.
  881. *
  882. * Any two consecutive I/O virtual address regions must have a hole of 128KiB
  883. * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
  884. *
  885. * Precisely, any start address of I/O virtual region must be aligned with
  886. * the following sizes for System MMU v3.1 and v3.2.
  887. * System MMU v3.1: 128KiB
  888. * System MMU v3.2: 256KiB
  889. *
  890. * Because System MMU v3.3 caches page table entries more aggressively, it needs
  891. * more workarounds.
  892. * - Any two consecutive I/O virtual regions must have a hole of size larger
  893. * than or equal to 128KiB.
  894. * - Start address of an I/O virtual region must be aligned by 128KiB.
  895. */
  896. static int exynos_iommu_map(struct iommu_domain *iommu_domain,
  897. unsigned long l_iova, phys_addr_t paddr, size_t size,
  898. int prot, gfp_t gfp)
  899. {
  900. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  901. sysmmu_pte_t *entry;
  902. sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
  903. unsigned long flags;
  904. int ret = -ENOMEM;
  905. BUG_ON(domain->pgtable == NULL);
  906. prot &= SYSMMU_SUPPORTED_PROT_BITS;
  907. spin_lock_irqsave(&domain->pgtablelock, flags);
  908. entry = section_entry(domain->pgtable, iova);
  909. if (size == SECT_SIZE) {
  910. ret = lv1set_section(domain, entry, iova, paddr, prot,
  911. &domain->lv2entcnt[lv1ent_offset(iova)]);
  912. } else {
  913. sysmmu_pte_t *pent;
  914. pent = alloc_lv2entry(domain, entry, iova,
  915. &domain->lv2entcnt[lv1ent_offset(iova)]);
  916. if (IS_ERR(pent))
  917. ret = PTR_ERR(pent);
  918. else
  919. ret = lv2set_page(pent, paddr, size, prot,
  920. &domain->lv2entcnt[lv1ent_offset(iova)]);
  921. }
  922. if (ret)
  923. pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
  924. __func__, ret, size, iova);
  925. spin_unlock_irqrestore(&domain->pgtablelock, flags);
  926. return ret;
  927. }
  928. static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
  929. sysmmu_iova_t iova, size_t size)
  930. {
  931. struct sysmmu_drvdata *data;
  932. unsigned long flags;
  933. spin_lock_irqsave(&domain->lock, flags);
  934. list_for_each_entry(data, &domain->clients, domain_node)
  935. sysmmu_tlb_invalidate_entry(data, iova, size);
  936. spin_unlock_irqrestore(&domain->lock, flags);
  937. }
  938. static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
  939. unsigned long l_iova, size_t size,
  940. struct iommu_iotlb_gather *gather)
  941. {
  942. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  943. sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
  944. sysmmu_pte_t *ent;
  945. size_t err_pgsize;
  946. unsigned long flags;
  947. BUG_ON(domain->pgtable == NULL);
  948. spin_lock_irqsave(&domain->pgtablelock, flags);
  949. ent = section_entry(domain->pgtable, iova);
  950. if (lv1ent_section(ent)) {
  951. if (WARN_ON(size < SECT_SIZE)) {
  952. err_pgsize = SECT_SIZE;
  953. goto err;
  954. }
  955. /* workaround for h/w bug in System MMU v3.3 */
  956. exynos_iommu_set_pte(ent, ZERO_LV2LINK);
  957. size = SECT_SIZE;
  958. goto done;
  959. }
  960. if (unlikely(lv1ent_fault(ent))) {
  961. if (size > SECT_SIZE)
  962. size = SECT_SIZE;
  963. goto done;
  964. }
  965. /* lv1ent_page(sent) == true here */
  966. ent = page_entry(ent, iova);
  967. if (unlikely(lv2ent_fault(ent))) {
  968. size = SPAGE_SIZE;
  969. goto done;
  970. }
  971. if (lv2ent_small(ent)) {
  972. exynos_iommu_set_pte(ent, 0);
  973. size = SPAGE_SIZE;
  974. domain->lv2entcnt[lv1ent_offset(iova)] += 1;
  975. goto done;
  976. }
  977. /* lv1ent_large(ent) == true here */
  978. if (WARN_ON(size < LPAGE_SIZE)) {
  979. err_pgsize = LPAGE_SIZE;
  980. goto err;
  981. }
  982. dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
  983. sizeof(*ent) * SPAGES_PER_LPAGE,
  984. DMA_TO_DEVICE);
  985. memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
  986. dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
  987. sizeof(*ent) * SPAGES_PER_LPAGE,
  988. DMA_TO_DEVICE);
  989. size = LPAGE_SIZE;
  990. domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
  991. done:
  992. spin_unlock_irqrestore(&domain->pgtablelock, flags);
  993. exynos_iommu_tlb_invalidate_entry(domain, iova, size);
  994. return size;
  995. err:
  996. spin_unlock_irqrestore(&domain->pgtablelock, flags);
  997. pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
  998. __func__, size, iova, err_pgsize);
  999. return 0;
  1000. }
  1001. static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
  1002. dma_addr_t iova)
  1003. {
  1004. struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
  1005. sysmmu_pte_t *entry;
  1006. unsigned long flags;
  1007. phys_addr_t phys = 0;
  1008. spin_lock_irqsave(&domain->pgtablelock, flags);
  1009. entry = section_entry(domain->pgtable, iova);
  1010. if (lv1ent_section(entry)) {
  1011. phys = section_phys(entry) + section_offs(iova);
  1012. } else if (lv1ent_page(entry)) {
  1013. entry = page_entry(entry, iova);
  1014. if (lv2ent_large(entry))
  1015. phys = lpage_phys(entry) + lpage_offs(iova);
  1016. else if (lv2ent_small(entry))
  1017. phys = spage_phys(entry) + spage_offs(iova);
  1018. }
  1019. spin_unlock_irqrestore(&domain->pgtablelock, flags);
  1020. return phys;
  1021. }
  1022. static struct iommu_device *exynos_iommu_probe_device(struct device *dev)
  1023. {
  1024. struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
  1025. struct sysmmu_drvdata *data;
  1026. if (!has_sysmmu(dev))
  1027. return ERR_PTR(-ENODEV);
  1028. list_for_each_entry(data, &owner->controllers, owner_node) {
  1029. /*
  1030. * SYSMMU will be runtime activated via device link
  1031. * (dependency) to its master device, so there are no
  1032. * direct calls to pm_runtime_get/put in this driver.
  1033. */
  1034. data->link = device_link_add(dev, data->sysmmu,
  1035. DL_FLAG_STATELESS |
  1036. DL_FLAG_PM_RUNTIME);
  1037. }
  1038. /* There is always at least one entry, see exynos_iommu_of_xlate() */
  1039. data = list_first_entry(&owner->controllers,
  1040. struct sysmmu_drvdata, owner_node);
  1041. return &data->iommu;
  1042. }
  1043. static void exynos_iommu_release_device(struct device *dev)
  1044. {
  1045. struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
  1046. struct sysmmu_drvdata *data;
  1047. if (!has_sysmmu(dev))
  1048. return;
  1049. if (owner->domain) {
  1050. struct iommu_group *group = iommu_group_get(dev);
  1051. if (group) {
  1052. WARN_ON(owner->domain !=
  1053. iommu_group_default_domain(group));
  1054. exynos_iommu_detach_device(owner->domain, dev);
  1055. iommu_group_put(group);
  1056. }
  1057. }
  1058. list_for_each_entry(data, &owner->controllers, owner_node)
  1059. device_link_del(data->link);
  1060. }
  1061. static int exynos_iommu_of_xlate(struct device *dev,
  1062. struct of_phandle_args *spec)
  1063. {
  1064. struct platform_device *sysmmu = of_find_device_by_node(spec->np);
  1065. struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev);
  1066. struct sysmmu_drvdata *data, *entry;
  1067. if (!sysmmu)
  1068. return -ENODEV;
  1069. data = platform_get_drvdata(sysmmu);
  1070. if (!data) {
  1071. put_device(&sysmmu->dev);
  1072. return -ENODEV;
  1073. }
  1074. if (!owner) {
  1075. owner = kzalloc(sizeof(*owner), GFP_KERNEL);
  1076. if (!owner) {
  1077. put_device(&sysmmu->dev);
  1078. return -ENOMEM;
  1079. }
  1080. INIT_LIST_HEAD(&owner->controllers);
  1081. mutex_init(&owner->rpm_lock);
  1082. dev_iommu_priv_set(dev, owner);
  1083. }
  1084. list_for_each_entry(entry, &owner->controllers, owner_node)
  1085. if (entry == data)
  1086. return 0;
  1087. list_add_tail(&data->owner_node, &owner->controllers);
  1088. data->master = dev;
  1089. return 0;
  1090. }
  1091. static const struct iommu_ops exynos_iommu_ops = {
  1092. .domain_alloc = exynos_iommu_domain_alloc,
  1093. .domain_free = exynos_iommu_domain_free,
  1094. .attach_dev = exynos_iommu_attach_device,
  1095. .detach_dev = exynos_iommu_detach_device,
  1096. .map = exynos_iommu_map,
  1097. .unmap = exynos_iommu_unmap,
  1098. .iova_to_phys = exynos_iommu_iova_to_phys,
  1099. .device_group = generic_device_group,
  1100. .probe_device = exynos_iommu_probe_device,
  1101. .release_device = exynos_iommu_release_device,
  1102. .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
  1103. .of_xlate = exynos_iommu_of_xlate,
  1104. };
  1105. static int __init exynos_iommu_init(void)
  1106. {
  1107. struct device_node *np;
  1108. int ret;
  1109. np = of_find_matching_node(NULL, sysmmu_of_match);
  1110. if (!np)
  1111. return 0;
  1112. of_node_put(np);
  1113. lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
  1114. LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
  1115. if (!lv2table_kmem_cache) {
  1116. pr_err("%s: Failed to create kmem cache\n", __func__);
  1117. return -ENOMEM;
  1118. }
  1119. ret = platform_driver_register(&exynos_sysmmu_driver);
  1120. if (ret) {
  1121. pr_err("%s: Failed to register driver\n", __func__);
  1122. goto err_reg_driver;
  1123. }
  1124. zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
  1125. if (zero_lv2_table == NULL) {
  1126. pr_err("%s: Failed to allocate zero level2 page table\n",
  1127. __func__);
  1128. ret = -ENOMEM;
  1129. goto err_zero_lv2;
  1130. }
  1131. ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
  1132. if (ret) {
  1133. pr_err("%s: Failed to register exynos-iommu driver.\n",
  1134. __func__);
  1135. goto err_set_iommu;
  1136. }
  1137. return 0;
  1138. err_set_iommu:
  1139. kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
  1140. err_zero_lv2:
  1141. platform_driver_unregister(&exynos_sysmmu_driver);
  1142. err_reg_driver:
  1143. kmem_cache_destroy(lv2table_kmem_cache);
  1144. return ret;
  1145. }
  1146. core_initcall(exynos_iommu_init);