sm8250.c 28 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. *
  5. */
  6. #include <linux/device.h>
  7. #include <linux/interconnect.h>
  8. #include <linux/interconnect-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/of_platform.h>
  11. #include <dt-bindings/interconnect/qcom,sm8250.h>
  12. #include "bcm-voter.h"
  13. #include "icc-rpmh.h"
  14. #include "sm8250.h"
  15. DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
  16. DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
  17. DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
  18. DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
  19. DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
  20. DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
  21. DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
  22. DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
  23. DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
  24. DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
  25. DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
  26. DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
  27. DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
  28. DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
  29. DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
  30. DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
  31. DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
  32. DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
  33. DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
  34. DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
  35. DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
  36. DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
  37. DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
  38. DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
  39. DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
  40. DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  41. DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  42. DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
  43. DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
  44. DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  45. DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  46. DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
  47. DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  48. DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
  49. DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
  50. DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
  51. DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
  52. DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
  53. DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
  54. DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
  55. DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  56. DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  57. DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  58. DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  59. DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  60. DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
  61. DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
  62. DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
  63. DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
  64. DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
  65. DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
  66. DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
  67. DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
  68. DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
  69. DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
  70. DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
  71. DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
  72. DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
  73. DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
  74. DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
  75. DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
  76. DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
  77. DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
  78. DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
  79. DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
  80. DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
  81. DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
  82. DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
  83. DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
  84. DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
  85. DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
  86. DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
  87. DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
  88. DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
  89. DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
  90. DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
  91. DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
  92. DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
  93. DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
  94. DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
  95. DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
  96. DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
  97. DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
  98. DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
  99. DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
  100. DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
  101. DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
  102. DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
  103. DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
  104. DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
  105. DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
  106. DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
  107. DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
  108. DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
  109. DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
  110. DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
  111. DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
  112. DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
  113. DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
  114. DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
  115. DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
  116. DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
  117. DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
  118. DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
  119. DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
  120. DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
  121. DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
  122. DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
  123. DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
  124. DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
  125. DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
  126. DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
  127. DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
  128. DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
  129. DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
  130. DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
  131. DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
  132. DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
  133. DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
  134. DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
  135. DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
  136. DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
  137. DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
  138. DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
  139. DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
  140. DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
  141. DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
  142. DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
  143. DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
  144. DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
  145. DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
  146. DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
  147. DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
  148. DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
  149. DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
  150. DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
  151. DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
  152. DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
  153. DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
  154. DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
  155. DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
  156. DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
  157. DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
  158. DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
  159. DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
  160. DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
  161. DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
  162. DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
  163. DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
  164. DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
  165. DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
  166. DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
  167. DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
  168. DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
  169. DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
  170. DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
  171. DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
  172. DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
  173. DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
  174. DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
  175. DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
  176. DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
  177. DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
  178. DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
  179. DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
  180. DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
  181. DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
  182. DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
  183. DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
  184. DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
  185. DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
  186. DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
  187. DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
  188. DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
  189. DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
  190. DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
  191. DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
  192. DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
  193. static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
  194. &bcm_qup0,
  195. &bcm_sn12,
  196. };
  197. static struct qcom_icc_node *aggre1_noc_nodes[] = {
  198. [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
  199. [MASTER_QSPI_0] = &qhm_qspi,
  200. [MASTER_QUP_1] = &qhm_qup1,
  201. [MASTER_QUP_2] = &qhm_qup2,
  202. [MASTER_TSIF] = &qhm_tsif,
  203. [MASTER_PCIE_2] = &xm_pcie3_modem,
  204. [MASTER_SDCC_4] = &xm_sdc4,
  205. [MASTER_UFS_MEM] = &xm_ufs_mem,
  206. [MASTER_USB3] = &xm_usb3_0,
  207. [MASTER_USB3_1] = &xm_usb3_1,
  208. [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
  209. [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
  210. [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
  211. };
  212. static struct qcom_icc_desc sm8250_aggre1_noc = {
  213. .nodes = aggre1_noc_nodes,
  214. .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
  215. .bcms = aggre1_noc_bcms,
  216. .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
  217. };
  218. static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
  219. &bcm_ce0,
  220. &bcm_qup0,
  221. &bcm_sn12,
  222. };
  223. static struct qcom_icc_node *aggre2_noc_nodes[] = {
  224. [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
  225. [MASTER_QDSS_BAM] = &qhm_qdss_bam,
  226. [MASTER_QUP_0] = &qhm_qup0,
  227. [MASTER_CNOC_A2NOC] = &qnm_cnoc,
  228. [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
  229. [MASTER_IPA] = &qxm_ipa,
  230. [MASTER_PCIE] = &xm_pcie3_0,
  231. [MASTER_PCIE_1] = &xm_pcie3_1,
  232. [MASTER_QDSS_ETR] = &xm_qdss_etr,
  233. [MASTER_SDCC_2] = &xm_sdc2,
  234. [MASTER_UFS_CARD] = &xm_ufs_card,
  235. [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
  236. [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
  237. [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
  238. };
  239. static struct qcom_icc_desc sm8250_aggre2_noc = {
  240. .nodes = aggre2_noc_nodes,
  241. .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
  242. .bcms = aggre2_noc_bcms,
  243. .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
  244. };
  245. static struct qcom_icc_bcm *compute_noc_bcms[] = {
  246. &bcm_co0,
  247. &bcm_co2,
  248. };
  249. static struct qcom_icc_node *compute_noc_nodes[] = {
  250. [MASTER_NPU] = &qnm_npu,
  251. [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
  252. };
  253. static struct qcom_icc_desc sm8250_compute_noc = {
  254. .nodes = compute_noc_nodes,
  255. .num_nodes = ARRAY_SIZE(compute_noc_nodes),
  256. .bcms = compute_noc_bcms,
  257. .num_bcms = ARRAY_SIZE(compute_noc_bcms),
  258. };
  259. static struct qcom_icc_bcm *config_noc_bcms[] = {
  260. &bcm_cn0,
  261. };
  262. static struct qcom_icc_node *config_noc_nodes[] = {
  263. [SNOC_CNOC_MAS] = &qnm_snoc,
  264. [MASTER_QDSS_DAP] = &xm_qdss_dap,
  265. [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
  266. [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
  267. [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
  268. [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
  269. [SLAVE_AOSS] = &qhs_aoss,
  270. [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
  271. [SLAVE_CLK_CTL] = &qhs_clk_ctl,
  272. [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
  273. [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
  274. [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
  275. [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
  276. [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
  277. [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
  278. [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
  279. [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
  280. [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
  281. [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
  282. [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
  283. [SLAVE_IPA_CFG] = &qhs_ipa,
  284. [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
  285. [SLAVE_LPASS] = &qhs_lpass_cfg,
  286. [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
  287. [SLAVE_NPU_CFG] = &qhs_npu_cfg,
  288. [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
  289. [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
  290. [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
  291. [SLAVE_PDM] = &qhs_pdm,
  292. [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
  293. [SLAVE_PRNG] = &qhs_prng,
  294. [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
  295. [SLAVE_QSPI_0] = &qhs_qspi,
  296. [SLAVE_QUP_0] = &qhs_qup0,
  297. [SLAVE_QUP_1] = &qhs_qup1,
  298. [SLAVE_QUP_2] = &qhs_qup2,
  299. [SLAVE_SDCC_2] = &qhs_sdc2,
  300. [SLAVE_SDCC_4] = &qhs_sdc4,
  301. [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
  302. [SLAVE_TCSR] = &qhs_tcsr,
  303. [SLAVE_TLMM_NORTH] = &qhs_tlmm0,
  304. [SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
  305. [SLAVE_TLMM_WEST] = &qhs_tlmm2,
  306. [SLAVE_TSIF] = &qhs_tsif,
  307. [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
  308. [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
  309. [SLAVE_USB3] = &qhs_usb3_0,
  310. [SLAVE_USB3_1] = &qhs_usb3_1,
  311. [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
  312. [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
  313. [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
  314. [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
  315. };
  316. static struct qcom_icc_desc sm8250_config_noc = {
  317. .nodes = config_noc_nodes,
  318. .num_nodes = ARRAY_SIZE(config_noc_nodes),
  319. .bcms = config_noc_bcms,
  320. .num_bcms = ARRAY_SIZE(config_noc_bcms),
  321. };
  322. static struct qcom_icc_bcm *dc_noc_bcms[] = {
  323. };
  324. static struct qcom_icc_node *dc_noc_nodes[] = {
  325. [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
  326. [SLAVE_LLCC_CFG] = &qhs_llcc,
  327. [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
  328. };
  329. static struct qcom_icc_desc sm8250_dc_noc = {
  330. .nodes = dc_noc_nodes,
  331. .num_nodes = ARRAY_SIZE(dc_noc_nodes),
  332. .bcms = dc_noc_bcms,
  333. .num_bcms = ARRAY_SIZE(dc_noc_bcms),
  334. };
  335. static struct qcom_icc_bcm *gem_noc_bcms[] = {
  336. &bcm_sh0,
  337. &bcm_sh2,
  338. &bcm_sh3,
  339. &bcm_sh4,
  340. };
  341. static struct qcom_icc_node *gem_noc_nodes[] = {
  342. [MASTER_GPU_TCU] = &alm_gpu_tcu,
  343. [MASTER_SYS_TCU] = &alm_sys_tcu,
  344. [MASTER_AMPSS_M0] = &chm_apps,
  345. [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
  346. [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
  347. [MASTER_GRAPHICS_3D] = &qnm_gpu,
  348. [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
  349. [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
  350. [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
  351. [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
  352. [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
  353. [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
  354. [SLAVE_LLCC] = &qns_llcc,
  355. [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
  356. [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
  357. [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
  358. [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
  359. };
  360. static struct qcom_icc_desc sm8250_gem_noc = {
  361. .nodes = gem_noc_nodes,
  362. .num_nodes = ARRAY_SIZE(gem_noc_nodes),
  363. .bcms = gem_noc_bcms,
  364. .num_bcms = ARRAY_SIZE(gem_noc_bcms),
  365. };
  366. static struct qcom_icc_bcm *ipa_virt_bcms[] = {
  367. &bcm_ip0,
  368. };
  369. static struct qcom_icc_node *ipa_virt_nodes[] = {
  370. [MASTER_IPA_CORE] = &ipa_core_master,
  371. [SLAVE_IPA_CORE] = &ipa_core_slave,
  372. };
  373. static struct qcom_icc_desc sm8250_ipa_virt = {
  374. .nodes = ipa_virt_nodes,
  375. .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
  376. .bcms = ipa_virt_bcms,
  377. .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
  378. };
  379. static struct qcom_icc_bcm *mc_virt_bcms[] = {
  380. &bcm_acv,
  381. &bcm_mc0,
  382. };
  383. static struct qcom_icc_node *mc_virt_nodes[] = {
  384. [MASTER_LLCC] = &llcc_mc,
  385. [SLAVE_EBI_CH0] = &ebi,
  386. };
  387. static struct qcom_icc_desc sm8250_mc_virt = {
  388. .nodes = mc_virt_nodes,
  389. .num_nodes = ARRAY_SIZE(mc_virt_nodes),
  390. .bcms = mc_virt_bcms,
  391. .num_bcms = ARRAY_SIZE(mc_virt_bcms),
  392. };
  393. static struct qcom_icc_bcm *mmss_noc_bcms[] = {
  394. &bcm_mm0,
  395. &bcm_mm1,
  396. &bcm_mm2,
  397. &bcm_mm3,
  398. };
  399. static struct qcom_icc_node *mmss_noc_nodes[] = {
  400. [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
  401. [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
  402. [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
  403. [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
  404. [MASTER_VIDEO_P0] = &qnm_video0,
  405. [MASTER_VIDEO_P1] = &qnm_video1,
  406. [MASTER_VIDEO_PROC] = &qnm_video_cvp,
  407. [MASTER_MDP_PORT0] = &qxm_mdp0,
  408. [MASTER_MDP_PORT1] = &qxm_mdp1,
  409. [MASTER_ROTATOR] = &qxm_rot,
  410. [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
  411. [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
  412. [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
  413. };
  414. static struct qcom_icc_desc sm8250_mmss_noc = {
  415. .nodes = mmss_noc_nodes,
  416. .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
  417. .bcms = mmss_noc_bcms,
  418. .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
  419. };
  420. static struct qcom_icc_bcm *npu_noc_bcms[] = {
  421. };
  422. static struct qcom_icc_node *npu_noc_nodes[] = {
  423. [MASTER_NPU_SYS] = &amm_npu_sys,
  424. [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
  425. [MASTER_NPU_NOC_CFG] = &qhm_cfg,
  426. [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
  427. [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
  428. [SLAVE_NPU_CP] = &qhs_cp,
  429. [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
  430. [SLAVE_NPU_DPM] = &qhs_dpm,
  431. [SLAVE_ISENSE_CFG] = &qhs_isense,
  432. [SLAVE_NPU_LLM_CFG] = &qhs_llm,
  433. [SLAVE_NPU_TCM] = &qhs_tcm,
  434. [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
  435. [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
  436. };
  437. static struct qcom_icc_desc sm8250_npu_noc = {
  438. .nodes = npu_noc_nodes,
  439. .num_nodes = ARRAY_SIZE(npu_noc_nodes),
  440. .bcms = npu_noc_bcms,
  441. .num_bcms = ARRAY_SIZE(npu_noc_bcms),
  442. };
  443. static struct qcom_icc_bcm *system_noc_bcms[] = {
  444. &bcm_sn0,
  445. &bcm_sn1,
  446. &bcm_sn11,
  447. &bcm_sn2,
  448. &bcm_sn3,
  449. &bcm_sn4,
  450. &bcm_sn5,
  451. &bcm_sn6,
  452. &bcm_sn7,
  453. &bcm_sn8,
  454. &bcm_sn9,
  455. };
  456. static struct qcom_icc_node *system_noc_nodes[] = {
  457. [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
  458. [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
  459. [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
  460. [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
  461. [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
  462. [MASTER_PIMEM] = &qxm_pimem,
  463. [MASTER_GIC] = &xm_gic,
  464. [SLAVE_APPSS] = &qhs_apss,
  465. [SNOC_CNOC_SLV] = &qns_cnoc,
  466. [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
  467. [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
  468. [SLAVE_OCIMEM] = &qxs_imem,
  469. [SLAVE_PIMEM] = &qxs_pimem,
  470. [SLAVE_SERVICE_SNOC] = &srvc_snoc,
  471. [SLAVE_PCIE_0] = &xs_pcie_0,
  472. [SLAVE_PCIE_1] = &xs_pcie_1,
  473. [SLAVE_PCIE_2] = &xs_pcie_modem,
  474. [SLAVE_QDSS_STM] = &xs_qdss_stm,
  475. [SLAVE_TCU] = &xs_sys_tcu_cfg,
  476. };
  477. static struct qcom_icc_desc sm8250_system_noc = {
  478. .nodes = system_noc_nodes,
  479. .num_nodes = ARRAY_SIZE(system_noc_nodes),
  480. .bcms = system_noc_bcms,
  481. .num_bcms = ARRAY_SIZE(system_noc_bcms),
  482. };
  483. static int qnoc_probe(struct platform_device *pdev)
  484. {
  485. const struct qcom_icc_desc *desc;
  486. struct icc_onecell_data *data;
  487. struct icc_provider *provider;
  488. struct qcom_icc_node **qnodes;
  489. struct qcom_icc_provider *qp;
  490. struct icc_node *node;
  491. size_t num_nodes, i;
  492. int ret;
  493. desc = device_get_match_data(&pdev->dev);
  494. if (!desc)
  495. return -EINVAL;
  496. qnodes = desc->nodes;
  497. num_nodes = desc->num_nodes;
  498. qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
  499. if (!qp)
  500. return -ENOMEM;
  501. data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
  502. if (!data)
  503. return -ENOMEM;
  504. provider = &qp->provider;
  505. provider->dev = &pdev->dev;
  506. provider->set = qcom_icc_set;
  507. provider->pre_aggregate = qcom_icc_pre_aggregate;
  508. provider->aggregate = qcom_icc_aggregate;
  509. provider->xlate = of_icc_xlate_onecell;
  510. INIT_LIST_HEAD(&provider->nodes);
  511. provider->data = data;
  512. qp->dev = &pdev->dev;
  513. qp->bcms = desc->bcms;
  514. qp->num_bcms = desc->num_bcms;
  515. qp->voter = of_bcm_voter_get(qp->dev, NULL);
  516. if (IS_ERR(qp->voter))
  517. return PTR_ERR(qp->voter);
  518. ret = icc_provider_add(provider);
  519. if (ret) {
  520. dev_err(&pdev->dev, "error adding interconnect provider\n");
  521. return ret;
  522. }
  523. for (i = 0; i < qp->num_bcms; i++)
  524. qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
  525. for (i = 0; i < num_nodes; i++) {
  526. size_t j;
  527. if (!qnodes[i])
  528. continue;
  529. node = icc_node_create(qnodes[i]->id);
  530. if (IS_ERR(node)) {
  531. ret = PTR_ERR(node);
  532. goto err;
  533. }
  534. node->name = qnodes[i]->name;
  535. node->data = qnodes[i];
  536. icc_node_add(node, provider);
  537. for (j = 0; j < qnodes[i]->num_links; j++)
  538. icc_link_create(node, qnodes[i]->links[j]);
  539. data->nodes[i] = node;
  540. }
  541. data->num_nodes = num_nodes;
  542. platform_set_drvdata(pdev, qp);
  543. return 0;
  544. err:
  545. icc_nodes_remove(provider);
  546. icc_provider_del(provider);
  547. return ret;
  548. }
  549. static int qnoc_remove(struct platform_device *pdev)
  550. {
  551. struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
  552. icc_nodes_remove(&qp->provider);
  553. return icc_provider_del(&qp->provider);
  554. }
  555. static const struct of_device_id qnoc_of_match[] = {
  556. { .compatible = "qcom,sm8250-aggre1-noc",
  557. .data = &sm8250_aggre1_noc},
  558. { .compatible = "qcom,sm8250-aggre2-noc",
  559. .data = &sm8250_aggre2_noc},
  560. { .compatible = "qcom,sm8250-compute-noc",
  561. .data = &sm8250_compute_noc},
  562. { .compatible = "qcom,sm8250-config-noc",
  563. .data = &sm8250_config_noc},
  564. { .compatible = "qcom,sm8250-dc-noc",
  565. .data = &sm8250_dc_noc},
  566. { .compatible = "qcom,sm8250-gem-noc",
  567. .data = &sm8250_gem_noc},
  568. { .compatible = "qcom,sm8250-ipa-virt",
  569. .data = &sm8250_ipa_virt},
  570. { .compatible = "qcom,sm8250-mc-virt",
  571. .data = &sm8250_mc_virt},
  572. { .compatible = "qcom,sm8250-mmss-noc",
  573. .data = &sm8250_mmss_noc},
  574. { .compatible = "qcom,sm8250-npu-noc",
  575. .data = &sm8250_npu_noc},
  576. { .compatible = "qcom,sm8250-system-noc",
  577. .data = &sm8250_system_noc},
  578. { }
  579. };
  580. MODULE_DEVICE_TABLE(of, qnoc_of_match);
  581. static struct platform_driver qnoc_driver = {
  582. .probe = qnoc_probe,
  583. .remove = qnoc_remove,
  584. .driver = {
  585. .name = "qnoc-sm8250",
  586. .of_match_table = qnoc_of_match,
  587. .sync_state = icc_sync_state,
  588. },
  589. };
  590. module_platform_driver(qnoc_driver);
  591. MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
  592. MODULE_LICENSE("GPL v2");