sm8150.c 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. *
  5. */
  6. #include <linux/device.h>
  7. #include <linux/interconnect.h>
  8. #include <linux/interconnect-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/of_platform.h>
  11. #include <dt-bindings/interconnect/qcom,sm8150.h>
  12. #include "bcm-voter.h"
  13. #include "icc-rpmh.h"
  14. #include "sm8150.h"
  15. DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
  16. DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
  17. DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
  18. DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
  19. DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
  20. DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
  21. DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
  22. DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
  23. DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
  24. DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
  25. DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
  26. DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
  27. DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
  28. DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
  29. DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
  30. DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
  31. DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
  32. DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
  33. DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
  34. DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
  35. DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
  36. DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  37. DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  38. DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
  39. DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
  40. DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
  41. DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
  42. DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
  43. DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
  44. DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  45. DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  46. DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  47. DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
  48. DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  49. DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  50. DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
  51. DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  52. DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
  53. DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
  54. DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
  55. DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
  56. DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
  57. DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
  58. DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
  59. DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  60. DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  61. DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  62. DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  63. DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
  64. DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  65. DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  66. DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  67. DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
  68. DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
  69. DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
  70. DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
  71. DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
  72. DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
  73. DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
  74. DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
  75. DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
  76. DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
  77. DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
  78. DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
  79. DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
  80. DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
  81. DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
  82. DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
  83. DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
  84. DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
  85. DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
  86. DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
  87. DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
  88. DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
  89. DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
  90. DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
  91. DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
  92. DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
  93. DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
  94. DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
  95. DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
  96. DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
  97. DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
  98. DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
  99. DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
  100. DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
  101. DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
  102. DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
  103. DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
  104. DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
  105. DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
  106. DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
  107. DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
  108. DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
  109. DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
  110. DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
  111. DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
  112. DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
  113. DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
  114. DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
  115. DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
  116. DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
  117. DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
  118. DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
  119. DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
  120. DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
  121. DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
  122. DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
  123. DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
  124. DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
  125. DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
  126. DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
  127. DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
  128. DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
  129. DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
  130. DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
  131. DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
  132. DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
  133. DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
  134. DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
  135. DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
  136. DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
  137. DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
  138. DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
  139. DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
  140. DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
  141. DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
  142. DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
  143. DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
  144. DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
  145. DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
  146. DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
  147. DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
  148. DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
  149. DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
  150. DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
  151. DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
  152. DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
  153. DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
  154. DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
  155. DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
  156. DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
  157. DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
  158. DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
  159. DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
  160. DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
  161. DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
  162. DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
  163. DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
  164. DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
  165. DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
  166. DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
  167. DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
  168. DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
  169. DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
  170. DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
  171. DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
  172. DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
  173. DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
  174. DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
  175. DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
  176. DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
  177. DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
  178. DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
  179. DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
  180. DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
  181. DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
  182. DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
  183. DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
  184. static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
  185. &bcm_qup0,
  186. &bcm_sn3,
  187. };
  188. static struct qcom_icc_node *aggre1_noc_nodes[] = {
  189. [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
  190. [MASTER_QUP_0] = &qhm_qup0,
  191. [MASTER_EMAC] = &xm_emac,
  192. [MASTER_UFS_MEM] = &xm_ufs_mem,
  193. [MASTER_USB3] = &xm_usb3_0,
  194. [MASTER_USB3_1] = &xm_usb3_1,
  195. [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
  196. [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
  197. };
  198. static struct qcom_icc_desc sm8150_aggre1_noc = {
  199. .nodes = aggre1_noc_nodes,
  200. .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
  201. .bcms = aggre1_noc_bcms,
  202. .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
  203. };
  204. static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
  205. &bcm_ce0,
  206. &bcm_qup0,
  207. &bcm_sn14,
  208. &bcm_sn3,
  209. };
  210. static struct qcom_icc_node *aggre2_noc_nodes[] = {
  211. [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
  212. [MASTER_QDSS_BAM] = &qhm_qdss_bam,
  213. [MASTER_QSPI] = &qhm_qspi,
  214. [MASTER_QUP_1] = &qhm_qup1,
  215. [MASTER_QUP_2] = &qhm_qup2,
  216. [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
  217. [MASTER_TSIF] = &qhm_tsif,
  218. [MASTER_CNOC_A2NOC] = &qnm_cnoc,
  219. [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
  220. [MASTER_IPA] = &qxm_ipa,
  221. [MASTER_PCIE] = &xm_pcie3_0,
  222. [MASTER_PCIE_1] = &xm_pcie3_1,
  223. [MASTER_QDSS_ETR] = &xm_qdss_etr,
  224. [MASTER_SDCC_2] = &xm_sdc2,
  225. [MASTER_SDCC_4] = &xm_sdc4,
  226. [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
  227. [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
  228. [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
  229. };
  230. static struct qcom_icc_desc sm8150_aggre2_noc = {
  231. .nodes = aggre2_noc_nodes,
  232. .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
  233. .bcms = aggre2_noc_bcms,
  234. .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
  235. };
  236. static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
  237. &bcm_mm1,
  238. };
  239. static struct qcom_icc_node *camnoc_virt_nodes[] = {
  240. [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
  241. [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
  242. [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
  243. [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
  244. };
  245. static struct qcom_icc_desc sm8150_camnoc_virt = {
  246. .nodes = camnoc_virt_nodes,
  247. .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
  248. .bcms = camnoc_virt_bcms,
  249. .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
  250. };
  251. static struct qcom_icc_bcm *compute_noc_bcms[] = {
  252. &bcm_co0,
  253. &bcm_co1,
  254. };
  255. static struct qcom_icc_node *compute_noc_nodes[] = {
  256. [MASTER_NPU] = &qnm_npu,
  257. [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
  258. };
  259. static struct qcom_icc_desc sm8150_compute_noc = {
  260. .nodes = compute_noc_nodes,
  261. .num_nodes = ARRAY_SIZE(compute_noc_nodes),
  262. .bcms = compute_noc_bcms,
  263. .num_bcms = ARRAY_SIZE(compute_noc_bcms),
  264. };
  265. static struct qcom_icc_bcm *config_noc_bcms[] = {
  266. &bcm_cn0,
  267. };
  268. static struct qcom_icc_node *config_noc_nodes[] = {
  269. [MASTER_SPDM] = &qhm_spdm,
  270. [SNOC_CNOC_MAS] = &qnm_snoc,
  271. [MASTER_QDSS_DAP] = &xm_qdss_dap,
  272. [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
  273. [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
  274. [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
  275. [SLAVE_AOP] = &qhs_aop,
  276. [SLAVE_AOSS] = &qhs_aoss,
  277. [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
  278. [SLAVE_CLK_CTL] = &qhs_clk_ctl,
  279. [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
  280. [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
  281. [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
  282. [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
  283. [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
  284. [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
  285. [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
  286. [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
  287. [SLAVE_GLM] = &qhs_glm,
  288. [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
  289. [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
  290. [SLAVE_IPA_CFG] = &qhs_ipa,
  291. [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
  292. [SLAVE_NPU_CFG] = &qhs_npu_cfg,
  293. [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
  294. [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
  295. [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
  296. [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
  297. [SLAVE_PRNG] = &qhs_prng,
  298. [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
  299. [SLAVE_QSPI] = &qhs_qspi,
  300. [SLAVE_QUP_2] = &qhs_qupv3_east,
  301. [SLAVE_QUP_1] = &qhs_qupv3_north,
  302. [SLAVE_QUP_0] = &qhs_qupv3_south,
  303. [SLAVE_SDCC_2] = &qhs_sdc2,
  304. [SLAVE_SDCC_4] = &qhs_sdc4,
  305. [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
  306. [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
  307. [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
  308. [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
  309. [SLAVE_TCSR] = &qhs_tcsr,
  310. [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
  311. [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
  312. [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
  313. [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
  314. [SLAVE_TSIF] = &qhs_tsif,
  315. [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
  316. [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
  317. [SLAVE_USB3] = &qhs_usb3_0,
  318. [SLAVE_USB3_1] = &qhs_usb3_1,
  319. [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
  320. [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
  321. [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
  322. [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
  323. };
  324. static struct qcom_icc_desc sm8150_config_noc = {
  325. .nodes = config_noc_nodes,
  326. .num_nodes = ARRAY_SIZE(config_noc_nodes),
  327. .bcms = config_noc_bcms,
  328. .num_bcms = ARRAY_SIZE(config_noc_bcms),
  329. };
  330. static struct qcom_icc_bcm *dc_noc_bcms[] = {
  331. };
  332. static struct qcom_icc_node *dc_noc_nodes[] = {
  333. [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
  334. [SLAVE_LLCC_CFG] = &qhs_llcc,
  335. [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
  336. };
  337. static struct qcom_icc_desc sm8150_dc_noc = {
  338. .nodes = dc_noc_nodes,
  339. .num_nodes = ARRAY_SIZE(dc_noc_nodes),
  340. .bcms = dc_noc_bcms,
  341. .num_bcms = ARRAY_SIZE(dc_noc_bcms),
  342. };
  343. static struct qcom_icc_bcm *gem_noc_bcms[] = {
  344. &bcm_sh0,
  345. &bcm_sh2,
  346. &bcm_sh3,
  347. &bcm_sh4,
  348. &bcm_sh5,
  349. };
  350. static struct qcom_icc_node *gem_noc_nodes[] = {
  351. [MASTER_AMPSS_M0] = &acm_apps,
  352. [MASTER_GPU_TCU] = &acm_gpu_tcu,
  353. [MASTER_SYS_TCU] = &acm_sys_tcu,
  354. [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
  355. [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
  356. [MASTER_GRAPHICS_3D] = &qnm_gpu,
  357. [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
  358. [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
  359. [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
  360. [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
  361. [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
  362. [MASTER_ECC] = &qxm_ecc,
  363. [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
  364. [SLAVE_ECC] = &qns_ecc,
  365. [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
  366. [SLAVE_LLCC] = &qns_llcc,
  367. [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
  368. };
  369. static struct qcom_icc_desc sm8150_gem_noc = {
  370. .nodes = gem_noc_nodes,
  371. .num_nodes = ARRAY_SIZE(gem_noc_nodes),
  372. .bcms = gem_noc_bcms,
  373. .num_bcms = ARRAY_SIZE(gem_noc_bcms),
  374. };
  375. static struct qcom_icc_bcm *ipa_virt_bcms[] = {
  376. &bcm_ip0,
  377. };
  378. static struct qcom_icc_node *ipa_virt_nodes[] = {
  379. [MASTER_IPA_CORE] = &ipa_core_master,
  380. [SLAVE_IPA_CORE] = &ipa_core_slave,
  381. };
  382. static struct qcom_icc_desc sm8150_ipa_virt = {
  383. .nodes = ipa_virt_nodes,
  384. .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
  385. .bcms = ipa_virt_bcms,
  386. .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
  387. };
  388. static struct qcom_icc_bcm *mc_virt_bcms[] = {
  389. &bcm_acv,
  390. &bcm_mc0,
  391. };
  392. static struct qcom_icc_node *mc_virt_nodes[] = {
  393. [MASTER_LLCC] = &llcc_mc,
  394. [SLAVE_EBI_CH0] = &ebi,
  395. };
  396. static struct qcom_icc_desc sm8150_mc_virt = {
  397. .nodes = mc_virt_nodes,
  398. .num_nodes = ARRAY_SIZE(mc_virt_nodes),
  399. .bcms = mc_virt_bcms,
  400. .num_bcms = ARRAY_SIZE(mc_virt_bcms),
  401. };
  402. static struct qcom_icc_bcm *mmss_noc_bcms[] = {
  403. &bcm_mm0,
  404. &bcm_mm1,
  405. &bcm_mm2,
  406. &bcm_mm3,
  407. };
  408. static struct qcom_icc_node *mmss_noc_nodes[] = {
  409. [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
  410. [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
  411. [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
  412. [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
  413. [MASTER_MDP_PORT0] = &qxm_mdp0,
  414. [MASTER_MDP_PORT1] = &qxm_mdp1,
  415. [MASTER_ROTATOR] = &qxm_rot,
  416. [MASTER_VIDEO_P0] = &qxm_venus0,
  417. [MASTER_VIDEO_P1] = &qxm_venus1,
  418. [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
  419. [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
  420. [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
  421. [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
  422. };
  423. static struct qcom_icc_desc sm8150_mmss_noc = {
  424. .nodes = mmss_noc_nodes,
  425. .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
  426. .bcms = mmss_noc_bcms,
  427. .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
  428. };
  429. static struct qcom_icc_bcm *system_noc_bcms[] = {
  430. &bcm_sn0,
  431. &bcm_sn1,
  432. &bcm_sn11,
  433. &bcm_sn12,
  434. &bcm_sn15,
  435. &bcm_sn2,
  436. &bcm_sn3,
  437. &bcm_sn4,
  438. &bcm_sn5,
  439. &bcm_sn8,
  440. &bcm_sn9,
  441. };
  442. static struct qcom_icc_node *system_noc_nodes[] = {
  443. [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
  444. [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
  445. [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
  446. [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
  447. [MASTER_PIMEM] = &qxm_pimem,
  448. [MASTER_GIC] = &xm_gic,
  449. [SLAVE_APPSS] = &qhs_apss,
  450. [SNOC_CNOC_SLV] = &qns_cnoc,
  451. [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
  452. [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
  453. [SLAVE_OCIMEM] = &qxs_imem,
  454. [SLAVE_PIMEM] = &qxs_pimem,
  455. [SLAVE_SERVICE_SNOC] = &srvc_snoc,
  456. [SLAVE_PCIE_0] = &xs_pcie_0,
  457. [SLAVE_PCIE_1] = &xs_pcie_1,
  458. [SLAVE_QDSS_STM] = &xs_qdss_stm,
  459. [SLAVE_TCU] = &xs_sys_tcu_cfg,
  460. };
  461. static struct qcom_icc_desc sm8150_system_noc = {
  462. .nodes = system_noc_nodes,
  463. .num_nodes = ARRAY_SIZE(system_noc_nodes),
  464. .bcms = system_noc_bcms,
  465. .num_bcms = ARRAY_SIZE(system_noc_bcms),
  466. };
  467. static int qnoc_probe(struct platform_device *pdev)
  468. {
  469. const struct qcom_icc_desc *desc;
  470. struct icc_onecell_data *data;
  471. struct icc_provider *provider;
  472. struct qcom_icc_node **qnodes;
  473. struct qcom_icc_provider *qp;
  474. struct icc_node *node;
  475. size_t num_nodes, i;
  476. int ret;
  477. desc = device_get_match_data(&pdev->dev);
  478. if (!desc)
  479. return -EINVAL;
  480. qnodes = desc->nodes;
  481. num_nodes = desc->num_nodes;
  482. qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
  483. if (!qp)
  484. return -ENOMEM;
  485. data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
  486. if (!data)
  487. return -ENOMEM;
  488. provider = &qp->provider;
  489. provider->dev = &pdev->dev;
  490. provider->set = qcom_icc_set;
  491. provider->pre_aggregate = qcom_icc_pre_aggregate;
  492. provider->aggregate = qcom_icc_aggregate;
  493. provider->xlate = of_icc_xlate_onecell;
  494. INIT_LIST_HEAD(&provider->nodes);
  495. provider->data = data;
  496. qp->dev = &pdev->dev;
  497. qp->bcms = desc->bcms;
  498. qp->num_bcms = desc->num_bcms;
  499. qp->voter = of_bcm_voter_get(qp->dev, NULL);
  500. if (IS_ERR(qp->voter))
  501. return PTR_ERR(qp->voter);
  502. ret = icc_provider_add(provider);
  503. if (ret) {
  504. dev_err(&pdev->dev, "error adding interconnect provider\n");
  505. return ret;
  506. }
  507. for (i = 0; i < qp->num_bcms; i++)
  508. qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
  509. for (i = 0; i < num_nodes; i++) {
  510. size_t j;
  511. if (!qnodes[i])
  512. continue;
  513. node = icc_node_create(qnodes[i]->id);
  514. if (IS_ERR(node)) {
  515. ret = PTR_ERR(node);
  516. goto err;
  517. }
  518. node->name = qnodes[i]->name;
  519. node->data = qnodes[i];
  520. icc_node_add(node, provider);
  521. for (j = 0; j < qnodes[i]->num_links; j++)
  522. icc_link_create(node, qnodes[i]->links[j]);
  523. data->nodes[i] = node;
  524. }
  525. data->num_nodes = num_nodes;
  526. platform_set_drvdata(pdev, qp);
  527. return 0;
  528. err:
  529. icc_nodes_remove(provider);
  530. icc_provider_del(provider);
  531. return ret;
  532. }
  533. static int qnoc_remove(struct platform_device *pdev)
  534. {
  535. struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
  536. icc_nodes_remove(&qp->provider);
  537. return icc_provider_del(&qp->provider);
  538. }
  539. static const struct of_device_id qnoc_of_match[] = {
  540. { .compatible = "qcom,sm8150-aggre1-noc",
  541. .data = &sm8150_aggre1_noc},
  542. { .compatible = "qcom,sm8150-aggre2-noc",
  543. .data = &sm8150_aggre2_noc},
  544. { .compatible = "qcom,sm8150-camnoc-virt",
  545. .data = &sm8150_camnoc_virt},
  546. { .compatible = "qcom,sm8150-compute-noc",
  547. .data = &sm8150_compute_noc},
  548. { .compatible = "qcom,sm8150-config-noc",
  549. .data = &sm8150_config_noc},
  550. { .compatible = "qcom,sm8150-dc-noc",
  551. .data = &sm8150_dc_noc},
  552. { .compatible = "qcom,sm8150-gem-noc",
  553. .data = &sm8150_gem_noc},
  554. { .compatible = "qcom,sm8150-ipa-virt",
  555. .data = &sm8150_ipa_virt},
  556. { .compatible = "qcom,sm8150-mc-virt",
  557. .data = &sm8150_mc_virt},
  558. { .compatible = "qcom,sm8150-mmss-noc",
  559. .data = &sm8150_mmss_noc},
  560. { .compatible = "qcom,sm8150-system-noc",
  561. .data = &sm8150_system_noc},
  562. { }
  563. };
  564. MODULE_DEVICE_TABLE(of, qnoc_of_match);
  565. static struct platform_driver qnoc_driver = {
  566. .probe = qnoc_probe,
  567. .remove = qnoc_remove,
  568. .driver = {
  569. .name = "qnoc-sm8150",
  570. .of_match_table = qnoc_of_match,
  571. .sync_state = icc_sync_state,
  572. },
  573. };
  574. module_platform_driver(qnoc_driver);
  575. MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
  576. MODULE_LICENSE("GPL v2");