sc7180.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. *
  5. */
  6. #include <linux/device.h>
  7. #include <linux/interconnect.h>
  8. #include <linux/interconnect-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/of_platform.h>
  11. #include <dt-bindings/interconnect/qcom,sc7180.h>
  12. #include "bcm-voter.h"
  13. #include "icc-rpmh.h"
  14. #include "sc7180.h"
  15. DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
  16. DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
  17. DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
  18. DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  19. DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  20. DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  21. DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
  22. DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
  23. DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
  24. DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  25. DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  26. DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  27. DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  28. DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  29. DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  30. DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  31. DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
  32. DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
  33. DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
  34. SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
  35. DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
  36. SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
  37. DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
  38. DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  39. DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  40. DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
  41. DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  42. DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
  43. DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  44. DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
  45. DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
  46. DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  47. DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
  48. DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
  49. DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
  50. DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  51. DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  52. DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  53. DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  54. DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  55. DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  56. DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  57. DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
  58. DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
  59. DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
  60. DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
  61. DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
  62. DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
  63. DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
  64. DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
  65. DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
  66. DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
  67. DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
  68. DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
  69. DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
  70. DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
  71. DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
  72. DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
  73. DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
  74. DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
  75. DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
  76. DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
  77. DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
  78. DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
  79. DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
  80. DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
  81. DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
  82. DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
  83. DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
  84. DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
  85. DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
  86. DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
  87. DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
  88. DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
  89. DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
  90. DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
  91. DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
  92. DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
  93. DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
  94. DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
  95. DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
  96. DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
  97. DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
  98. DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
  99. DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
  100. DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
  101. DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
  102. DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
  103. DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
  104. DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
  105. DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
  106. DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
  107. DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
  108. DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
  109. DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
  110. DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
  111. DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
  112. DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
  113. DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
  114. DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
  115. DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
  116. DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
  117. DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
  118. DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
  119. DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
  120. DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
  121. DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
  122. DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
  123. DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
  124. DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
  125. DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
  126. DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
  127. DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
  128. DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
  129. DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
  130. DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
  131. DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
  132. DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
  133. DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
  134. DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
  135. DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
  136. DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
  137. DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
  138. DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
  139. DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
  140. DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
  141. DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
  142. DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
  143. DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
  144. DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
  145. DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
  146. DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
  147. DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
  148. DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
  149. DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
  150. DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
  151. DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
  152. DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
  153. DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
  154. DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
  155. DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
  156. DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
  157. DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
  158. DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
  159. DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
  160. DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
  161. DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
  162. DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
  163. DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
  164. DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
  165. DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
  166. DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
  167. DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
  168. DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
  169. DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
  170. DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
  171. DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
  172. DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
  173. DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
  174. DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
  175. DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
  176. DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
  177. DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
  178. DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
  179. static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
  180. &bcm_cn1,
  181. };
  182. static struct qcom_icc_node *aggre1_noc_nodes[] = {
  183. [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
  184. [MASTER_QSPI] = &qhm_qspi,
  185. [MASTER_QUP_0] = &qhm_qup_0,
  186. [MASTER_SDCC_2] = &xm_sdc2,
  187. [MASTER_EMMC] = &xm_emmc,
  188. [MASTER_UFS_MEM] = &xm_ufs_mem,
  189. [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
  190. [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
  191. };
  192. static struct qcom_icc_desc sc7180_aggre1_noc = {
  193. .nodes = aggre1_noc_nodes,
  194. .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
  195. .bcms = aggre1_noc_bcms,
  196. .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
  197. };
  198. static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
  199. &bcm_ce0,
  200. };
  201. static struct qcom_icc_node *aggre2_noc_nodes[] = {
  202. [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
  203. [MASTER_QDSS_BAM] = &qhm_qdss_bam,
  204. [MASTER_QUP_1] = &qhm_qup_1,
  205. [MASTER_USB3] = &qhm_usb3,
  206. [MASTER_CRYPTO] = &qxm_crypto,
  207. [MASTER_IPA] = &qxm_ipa,
  208. [MASTER_QDSS_ETR] = &xm_qdss_etr,
  209. [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
  210. [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
  211. };
  212. static struct qcom_icc_desc sc7180_aggre2_noc = {
  213. .nodes = aggre2_noc_nodes,
  214. .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
  215. .bcms = aggre2_noc_bcms,
  216. .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
  217. };
  218. static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
  219. &bcm_mm1,
  220. };
  221. static struct qcom_icc_node *camnoc_virt_nodes[] = {
  222. [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
  223. [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
  224. [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
  225. [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
  226. };
  227. static struct qcom_icc_desc sc7180_camnoc_virt = {
  228. .nodes = camnoc_virt_nodes,
  229. .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
  230. .bcms = camnoc_virt_bcms,
  231. .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
  232. };
  233. static struct qcom_icc_bcm *compute_noc_bcms[] = {
  234. &bcm_co0,
  235. &bcm_co2,
  236. &bcm_co3,
  237. };
  238. static struct qcom_icc_node *compute_noc_nodes[] = {
  239. [MASTER_NPU] = &qnm_npu,
  240. [MASTER_NPU_PROC] = &qxm_npu_dsp,
  241. [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
  242. };
  243. static struct qcom_icc_desc sc7180_compute_noc = {
  244. .nodes = compute_noc_nodes,
  245. .num_nodes = ARRAY_SIZE(compute_noc_nodes),
  246. .bcms = compute_noc_bcms,
  247. .num_bcms = ARRAY_SIZE(compute_noc_bcms),
  248. };
  249. static struct qcom_icc_bcm *config_noc_bcms[] = {
  250. &bcm_cn0,
  251. &bcm_cn1,
  252. };
  253. static struct qcom_icc_node *config_noc_nodes[] = {
  254. [MASTER_SNOC_CNOC] = &qnm_snoc,
  255. [MASTER_QDSS_DAP] = &xm_qdss_dap,
  256. [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
  257. [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
  258. [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
  259. [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
  260. [SLAVE_AOP] = &qhs_aop,
  261. [SLAVE_AOSS] = &qhs_aoss,
  262. [SLAVE_BOOT_ROM] = &qhs_boot_rom,
  263. [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
  264. [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
  265. [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
  266. [SLAVE_CLK_CTL] = &qhs_clk_ctl,
  267. [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
  268. [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
  269. [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
  270. [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
  271. [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
  272. [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
  273. [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
  274. [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
  275. [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
  276. [SLAVE_GLM] = &qhs_glm,
  277. [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
  278. [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
  279. [SLAVE_IPA_CFG] = &qhs_ipa,
  280. [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
  281. [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
  282. [SLAVE_NPU_CFG] = &qhs_npu_cfg,
  283. [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
  284. [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
  285. [SLAVE_PDM] = &qhs_pdm,
  286. [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
  287. [SLAVE_PRNG] = &qhs_prng,
  288. [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
  289. [SLAVE_QM_CFG] = &qhs_qm_cfg,
  290. [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
  291. [SLAVE_QSPI_0] = &qhs_qspi,
  292. [SLAVE_QUP_0] = &qhs_qup0,
  293. [SLAVE_QUP_1] = &qhs_qup1,
  294. [SLAVE_SDCC_2] = &qhs_sdc2,
  295. [SLAVE_SECURITY] = &qhs_security,
  296. [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
  297. [SLAVE_TCSR] = &qhs_tcsr,
  298. [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
  299. [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
  300. [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
  301. [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
  302. [SLAVE_USB3] = &qhs_usb3,
  303. [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
  304. [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
  305. [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
  306. [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
  307. };
  308. static struct qcom_icc_desc sc7180_config_noc = {
  309. .nodes = config_noc_nodes,
  310. .num_nodes = ARRAY_SIZE(config_noc_nodes),
  311. .bcms = config_noc_bcms,
  312. .num_bcms = ARRAY_SIZE(config_noc_bcms),
  313. };
  314. static struct qcom_icc_node *dc_noc_nodes[] = {
  315. [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
  316. [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
  317. [SLAVE_LLCC_CFG] = &qhs_llcc,
  318. };
  319. static struct qcom_icc_desc sc7180_dc_noc = {
  320. .nodes = dc_noc_nodes,
  321. .num_nodes = ARRAY_SIZE(dc_noc_nodes),
  322. };
  323. static struct qcom_icc_bcm *gem_noc_bcms[] = {
  324. &bcm_sh0,
  325. &bcm_sh2,
  326. &bcm_sh3,
  327. &bcm_sh4,
  328. };
  329. static struct qcom_icc_node *gem_noc_nodes[] = {
  330. [MASTER_APPSS_PROC] = &acm_apps0,
  331. [MASTER_SYS_TCU] = &acm_sys_tcu,
  332. [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
  333. [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
  334. [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
  335. [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
  336. [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
  337. [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
  338. [MASTER_GFX3D] = &qxm_gpu,
  339. [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
  340. [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
  341. [SLAVE_LLCC] = &qns_llcc,
  342. [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
  343. };
  344. static struct qcom_icc_desc sc7180_gem_noc = {
  345. .nodes = gem_noc_nodes,
  346. .num_nodes = ARRAY_SIZE(gem_noc_nodes),
  347. .bcms = gem_noc_bcms,
  348. .num_bcms = ARRAY_SIZE(gem_noc_bcms),
  349. };
  350. static struct qcom_icc_bcm *ipa_virt_bcms[] = {
  351. &bcm_ip0,
  352. };
  353. static struct qcom_icc_node *ipa_virt_nodes[] = {
  354. [MASTER_IPA_CORE] = &ipa_core_master,
  355. [SLAVE_IPA_CORE] = &ipa_core_slave,
  356. };
  357. static struct qcom_icc_desc sc7180_ipa_virt = {
  358. .nodes = ipa_virt_nodes,
  359. .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
  360. .bcms = ipa_virt_bcms,
  361. .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
  362. };
  363. static struct qcom_icc_bcm *mc_virt_bcms[] = {
  364. &bcm_acv,
  365. &bcm_mc0,
  366. };
  367. static struct qcom_icc_node *mc_virt_nodes[] = {
  368. [MASTER_LLCC] = &llcc_mc,
  369. [SLAVE_EBI1] = &ebi,
  370. };
  371. static struct qcom_icc_desc sc7180_mc_virt = {
  372. .nodes = mc_virt_nodes,
  373. .num_nodes = ARRAY_SIZE(mc_virt_nodes),
  374. .bcms = mc_virt_bcms,
  375. .num_bcms = ARRAY_SIZE(mc_virt_bcms),
  376. };
  377. static struct qcom_icc_bcm *mmss_noc_bcms[] = {
  378. &bcm_mm0,
  379. &bcm_mm1,
  380. &bcm_mm2,
  381. };
  382. static struct qcom_icc_node *mmss_noc_nodes[] = {
  383. [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
  384. [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
  385. [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
  386. [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
  387. [MASTER_MDP0] = &qxm_mdp0,
  388. [MASTER_ROTATOR] = &qxm_rot,
  389. [MASTER_VIDEO_P0] = &qxm_venus0,
  390. [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
  391. [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
  392. [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
  393. [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
  394. };
  395. static struct qcom_icc_desc sc7180_mmss_noc = {
  396. .nodes = mmss_noc_nodes,
  397. .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
  398. .bcms = mmss_noc_bcms,
  399. .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
  400. };
  401. static struct qcom_icc_node *npu_noc_nodes[] = {
  402. [MASTER_NPU_SYS] = &amm_npu_sys,
  403. [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
  404. [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
  405. [SLAVE_NPU_CP] = &qhs_cp,
  406. [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
  407. [SLAVE_NPU_DPM] = &qhs_dpm,
  408. [SLAVE_ISENSE_CFG] = &qhs_isense,
  409. [SLAVE_NPU_LLM_CFG] = &qhs_llm,
  410. [SLAVE_NPU_TCM] = &qhs_tcm,
  411. [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
  412. [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
  413. };
  414. static struct qcom_icc_desc sc7180_npu_noc = {
  415. .nodes = npu_noc_nodes,
  416. .num_nodes = ARRAY_SIZE(npu_noc_nodes),
  417. };
  418. static struct qcom_icc_bcm *qup_virt_bcms[] = {
  419. &bcm_qup0,
  420. };
  421. static struct qcom_icc_node *qup_virt_nodes[] = {
  422. [MASTER_QUP_CORE_0] = &qup_core_master_1,
  423. [MASTER_QUP_CORE_1] = &qup_core_master_2,
  424. [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
  425. [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
  426. };
  427. static struct qcom_icc_desc sc7180_qup_virt = {
  428. .nodes = qup_virt_nodes,
  429. .num_nodes = ARRAY_SIZE(qup_virt_nodes),
  430. .bcms = qup_virt_bcms,
  431. .num_bcms = ARRAY_SIZE(qup_virt_bcms),
  432. };
  433. static struct qcom_icc_bcm *system_noc_bcms[] = {
  434. &bcm_sn0,
  435. &bcm_sn1,
  436. &bcm_sn2,
  437. &bcm_sn3,
  438. &bcm_sn4,
  439. &bcm_sn7,
  440. &bcm_sn9,
  441. &bcm_sn12,
  442. };
  443. static struct qcom_icc_node *system_noc_nodes[] = {
  444. [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
  445. [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
  446. [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
  447. [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
  448. [MASTER_PIMEM] = &qxm_pimem,
  449. [SLAVE_APPSS] = &qhs_apss,
  450. [SLAVE_SNOC_CNOC] = &qns_cnoc,
  451. [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
  452. [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
  453. [SLAVE_IMEM] = &qxs_imem,
  454. [SLAVE_PIMEM] = &qxs_pimem,
  455. [SLAVE_SERVICE_SNOC] = &srvc_snoc,
  456. [SLAVE_QDSS_STM] = &xs_qdss_stm,
  457. [SLAVE_TCU] = &xs_sys_tcu_cfg,
  458. };
  459. static struct qcom_icc_desc sc7180_system_noc = {
  460. .nodes = system_noc_nodes,
  461. .num_nodes = ARRAY_SIZE(system_noc_nodes),
  462. .bcms = system_noc_bcms,
  463. .num_bcms = ARRAY_SIZE(system_noc_bcms),
  464. };
  465. static int qnoc_probe(struct platform_device *pdev)
  466. {
  467. const struct qcom_icc_desc *desc;
  468. struct icc_onecell_data *data;
  469. struct icc_provider *provider;
  470. struct qcom_icc_node **qnodes;
  471. struct qcom_icc_provider *qp;
  472. struct icc_node *node;
  473. size_t num_nodes, i;
  474. int ret;
  475. desc = device_get_match_data(&pdev->dev);
  476. if (!desc)
  477. return -EINVAL;
  478. qnodes = desc->nodes;
  479. num_nodes = desc->num_nodes;
  480. qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
  481. if (!qp)
  482. return -ENOMEM;
  483. data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
  484. if (!data)
  485. return -ENOMEM;
  486. provider = &qp->provider;
  487. provider->dev = &pdev->dev;
  488. provider->set = qcom_icc_set;
  489. provider->pre_aggregate = qcom_icc_pre_aggregate;
  490. provider->aggregate = qcom_icc_aggregate;
  491. provider->xlate_extended = qcom_icc_xlate_extended;
  492. INIT_LIST_HEAD(&provider->nodes);
  493. provider->data = data;
  494. qp->dev = &pdev->dev;
  495. qp->bcms = desc->bcms;
  496. qp->num_bcms = desc->num_bcms;
  497. qp->voter = of_bcm_voter_get(qp->dev, NULL);
  498. if (IS_ERR(qp->voter))
  499. return PTR_ERR(qp->voter);
  500. ret = icc_provider_add(provider);
  501. if (ret) {
  502. dev_err(&pdev->dev, "error adding interconnect provider\n");
  503. return ret;
  504. }
  505. for (i = 0; i < qp->num_bcms; i++)
  506. qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
  507. for (i = 0; i < num_nodes; i++) {
  508. size_t j;
  509. if (!qnodes[i])
  510. continue;
  511. node = icc_node_create(qnodes[i]->id);
  512. if (IS_ERR(node)) {
  513. ret = PTR_ERR(node);
  514. goto err;
  515. }
  516. node->name = qnodes[i]->name;
  517. node->data = qnodes[i];
  518. icc_node_add(node, provider);
  519. for (j = 0; j < qnodes[i]->num_links; j++)
  520. icc_link_create(node, qnodes[i]->links[j]);
  521. data->nodes[i] = node;
  522. }
  523. data->num_nodes = num_nodes;
  524. platform_set_drvdata(pdev, qp);
  525. return 0;
  526. err:
  527. icc_nodes_remove(provider);
  528. icc_provider_del(provider);
  529. return ret;
  530. }
  531. static int qnoc_remove(struct platform_device *pdev)
  532. {
  533. struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
  534. icc_nodes_remove(&qp->provider);
  535. return icc_provider_del(&qp->provider);
  536. }
  537. static const struct of_device_id qnoc_of_match[] = {
  538. { .compatible = "qcom,sc7180-aggre1-noc",
  539. .data = &sc7180_aggre1_noc},
  540. { .compatible = "qcom,sc7180-aggre2-noc",
  541. .data = &sc7180_aggre2_noc},
  542. { .compatible = "qcom,sc7180-camnoc-virt",
  543. .data = &sc7180_camnoc_virt},
  544. { .compatible = "qcom,sc7180-compute-noc",
  545. .data = &sc7180_compute_noc},
  546. { .compatible = "qcom,sc7180-config-noc",
  547. .data = &sc7180_config_noc},
  548. { .compatible = "qcom,sc7180-dc-noc",
  549. .data = &sc7180_dc_noc},
  550. { .compatible = "qcom,sc7180-gem-noc",
  551. .data = &sc7180_gem_noc},
  552. { .compatible = "qcom,sc7180-ipa-virt",
  553. .data = &sc7180_ipa_virt},
  554. { .compatible = "qcom,sc7180-mc-virt",
  555. .data = &sc7180_mc_virt},
  556. { .compatible = "qcom,sc7180-mmss-noc",
  557. .data = &sc7180_mmss_noc},
  558. { .compatible = "qcom,sc7180-npu-noc",
  559. .data = &sc7180_npu_noc},
  560. { .compatible = "qcom,sc7180-qup-virt",
  561. .data = &sc7180_qup_virt},
  562. { .compatible = "qcom,sc7180-system-noc",
  563. .data = &sc7180_system_noc},
  564. { }
  565. };
  566. MODULE_DEVICE_TABLE(of, qnoc_of_match);
  567. static struct platform_driver qnoc_driver = {
  568. .probe = qnoc_probe,
  569. .remove = qnoc_remove,
  570. .driver = {
  571. .name = "qnoc-sc7180",
  572. .of_match_table = qnoc_of_match,
  573. .sync_state = icc_sync_state,
  574. },
  575. };
  576. module_platform_driver(qnoc_driver);
  577. MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
  578. MODULE_LICENSE("GPL v2");