sun4i-ps2.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Allwinner A10 PS2 host controller
  4. *
  5. * Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
  6. * Aaron.maoye <leafy.myeh@newbietech.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/serio.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/errno.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/clk.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/platform_device.h>
  17. #define DRIVER_NAME "sun4i-ps2"
  18. /* register offset definitions */
  19. #define PS2_REG_GCTL 0x00 /* PS2 Module Global Control Reg */
  20. #define PS2_REG_DATA 0x04 /* PS2 Module Data Reg */
  21. #define PS2_REG_LCTL 0x08 /* PS2 Module Line Control Reg */
  22. #define PS2_REG_LSTS 0x0C /* PS2 Module Line Status Reg */
  23. #define PS2_REG_FCTL 0x10 /* PS2 Module FIFO Control Reg */
  24. #define PS2_REG_FSTS 0x14 /* PS2 Module FIFO Status Reg */
  25. #define PS2_REG_CLKDR 0x18 /* PS2 Module Clock Divider Reg*/
  26. /* PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
  27. #define PS2_GCTL_INTFLAG BIT(4)
  28. #define PS2_GCTL_INTEN BIT(3)
  29. #define PS2_GCTL_RESET BIT(2)
  30. #define PS2_GCTL_MASTER BIT(1)
  31. #define PS2_GCTL_BUSEN BIT(0)
  32. /* PS2 LINE CONTROL REGISTER */
  33. #define PS2_LCTL_NOACK BIT(18)
  34. #define PS2_LCTL_TXDTOEN BIT(8)
  35. #define PS2_LCTL_STOPERREN BIT(3)
  36. #define PS2_LCTL_ACKERREN BIT(2)
  37. #define PS2_LCTL_PARERREN BIT(1)
  38. #define PS2_LCTL_RXDTOEN BIT(0)
  39. /* PS2 LINE STATUS REGISTER */
  40. #define PS2_LSTS_TXTDO BIT(8)
  41. #define PS2_LSTS_STOPERR BIT(3)
  42. #define PS2_LSTS_ACKERR BIT(2)
  43. #define PS2_LSTS_PARERR BIT(1)
  44. #define PS2_LSTS_RXTDO BIT(0)
  45. #define PS2_LINE_ERROR_BIT \
  46. (PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
  47. PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
  48. /* PS2 FIFO CONTROL REGISTER */
  49. #define PS2_FCTL_TXRST BIT(17)
  50. #define PS2_FCTL_RXRST BIT(16)
  51. #define PS2_FCTL_TXUFIEN BIT(10)
  52. #define PS2_FCTL_TXOFIEN BIT(9)
  53. #define PS2_FCTL_TXRDYIEN BIT(8)
  54. #define PS2_FCTL_RXUFIEN BIT(2)
  55. #define PS2_FCTL_RXOFIEN BIT(1)
  56. #define PS2_FCTL_RXRDYIEN BIT(0)
  57. /* PS2 FIFO STATUS REGISTER */
  58. #define PS2_FSTS_TXUF BIT(10)
  59. #define PS2_FSTS_TXOF BIT(9)
  60. #define PS2_FSTS_TXRDY BIT(8)
  61. #define PS2_FSTS_RXUF BIT(2)
  62. #define PS2_FSTS_RXOF BIT(1)
  63. #define PS2_FSTS_RXRDY BIT(0)
  64. #define PS2_FIFO_ERROR_BIT \
  65. (PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
  66. #define PS2_SAMPLE_CLK 1000000
  67. #define PS2_SCLK 125000
  68. struct sun4i_ps2data {
  69. struct serio *serio;
  70. struct device *dev;
  71. /* IO mapping base */
  72. void __iomem *reg_base;
  73. /* clock management */
  74. struct clk *clk;
  75. /* irq */
  76. spinlock_t lock;
  77. int irq;
  78. };
  79. static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
  80. {
  81. struct sun4i_ps2data *drvdata = dev_id;
  82. u32 intr_status;
  83. u32 fifo_status;
  84. unsigned char byte;
  85. unsigned int rxflags = 0;
  86. u32 rval;
  87. spin_lock(&drvdata->lock);
  88. /* Get the PS/2 interrupts and clear them */
  89. intr_status = readl(drvdata->reg_base + PS2_REG_LSTS);
  90. fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS);
  91. /* Check line status register */
  92. if (intr_status & PS2_LINE_ERROR_BIT) {
  93. rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
  94. rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
  95. rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
  96. rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
  97. PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
  98. writel(rval, drvdata->reg_base + PS2_REG_LSTS);
  99. }
  100. /* Check FIFO status register */
  101. if (fifo_status & PS2_FIFO_ERROR_BIT) {
  102. rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
  103. PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
  104. writel(rval, drvdata->reg_base + PS2_REG_FSTS);
  105. }
  106. rval = (fifo_status >> 16) & 0x3;
  107. while (rval--) {
  108. byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
  109. serio_interrupt(drvdata->serio, byte, rxflags);
  110. }
  111. writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
  112. writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
  113. spin_unlock(&drvdata->lock);
  114. return IRQ_HANDLED;
  115. }
  116. static int sun4i_ps2_open(struct serio *serio)
  117. {
  118. struct sun4i_ps2data *drvdata = serio->port_data;
  119. u32 src_clk = 0;
  120. u32 clk_scdf;
  121. u32 clk_pcdf;
  122. u32 rval;
  123. unsigned long flags;
  124. /* Set line control and enable interrupt */
  125. rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
  126. | PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
  127. writel(rval, drvdata->reg_base + PS2_REG_LCTL);
  128. /* Reset FIFO */
  129. rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
  130. | PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
  131. | PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
  132. writel(rval, drvdata->reg_base + PS2_REG_FCTL);
  133. src_clk = clk_get_rate(drvdata->clk);
  134. /* Set clock divider register */
  135. clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
  136. clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
  137. rval = (clk_scdf << 8) | clk_pcdf;
  138. writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
  139. /* Set global control register */
  140. rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
  141. | PS2_GCTL_BUSEN;
  142. spin_lock_irqsave(&drvdata->lock, flags);
  143. writel(rval, drvdata->reg_base + PS2_REG_GCTL);
  144. spin_unlock_irqrestore(&drvdata->lock, flags);
  145. return 0;
  146. }
  147. static void sun4i_ps2_close(struct serio *serio)
  148. {
  149. struct sun4i_ps2data *drvdata = serio->port_data;
  150. u32 rval;
  151. /* Shut off the interrupt */
  152. rval = readl(drvdata->reg_base + PS2_REG_GCTL);
  153. writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
  154. synchronize_irq(drvdata->irq);
  155. }
  156. static int sun4i_ps2_write(struct serio *serio, unsigned char val)
  157. {
  158. unsigned long expire = jiffies + msecs_to_jiffies(10000);
  159. struct sun4i_ps2data *drvdata = serio->port_data;
  160. do {
  161. if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
  162. writel(val, drvdata->reg_base + PS2_REG_DATA);
  163. return 0;
  164. }
  165. } while (time_before(jiffies, expire));
  166. return SERIO_TIMEOUT;
  167. }
  168. static int sun4i_ps2_probe(struct platform_device *pdev)
  169. {
  170. struct resource *res; /* IO mem resources */
  171. struct sun4i_ps2data *drvdata;
  172. struct serio *serio;
  173. struct device *dev = &pdev->dev;
  174. int error;
  175. drvdata = kzalloc(sizeof(struct sun4i_ps2data), GFP_KERNEL);
  176. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  177. if (!drvdata || !serio) {
  178. error = -ENOMEM;
  179. goto err_free_mem;
  180. }
  181. spin_lock_init(&drvdata->lock);
  182. /* IO */
  183. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  184. if (!res) {
  185. dev_err(dev, "failed to locate registers\n");
  186. error = -ENXIO;
  187. goto err_free_mem;
  188. }
  189. drvdata->reg_base = ioremap(res->start, resource_size(res));
  190. if (!drvdata->reg_base) {
  191. dev_err(dev, "failed to map registers\n");
  192. error = -ENOMEM;
  193. goto err_free_mem;
  194. }
  195. drvdata->clk = clk_get(dev, NULL);
  196. if (IS_ERR(drvdata->clk)) {
  197. error = PTR_ERR(drvdata->clk);
  198. dev_err(dev, "couldn't get clock %d\n", error);
  199. goto err_ioremap;
  200. }
  201. error = clk_prepare_enable(drvdata->clk);
  202. if (error) {
  203. dev_err(dev, "failed to enable clock %d\n", error);
  204. goto err_clk;
  205. }
  206. serio->id.type = SERIO_8042;
  207. serio->write = sun4i_ps2_write;
  208. serio->open = sun4i_ps2_open;
  209. serio->close = sun4i_ps2_close;
  210. serio->port_data = drvdata;
  211. serio->dev.parent = dev;
  212. strlcpy(serio->name, dev_name(dev), sizeof(serio->name));
  213. strlcpy(serio->phys, dev_name(dev), sizeof(serio->phys));
  214. /* shutoff interrupt */
  215. writel(0, drvdata->reg_base + PS2_REG_GCTL);
  216. /* Get IRQ for the device */
  217. drvdata->irq = platform_get_irq(pdev, 0);
  218. if (drvdata->irq < 0) {
  219. error = drvdata->irq;
  220. goto err_disable_clk;
  221. }
  222. drvdata->serio = serio;
  223. drvdata->dev = dev;
  224. error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
  225. DRIVER_NAME, drvdata);
  226. if (error) {
  227. dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
  228. drvdata->irq, error);
  229. goto err_disable_clk;
  230. }
  231. serio_register_port(serio);
  232. platform_set_drvdata(pdev, drvdata);
  233. return 0; /* success */
  234. err_disable_clk:
  235. clk_disable_unprepare(drvdata->clk);
  236. err_clk:
  237. clk_put(drvdata->clk);
  238. err_ioremap:
  239. iounmap(drvdata->reg_base);
  240. err_free_mem:
  241. kfree(serio);
  242. kfree(drvdata);
  243. return error;
  244. }
  245. static int sun4i_ps2_remove(struct platform_device *pdev)
  246. {
  247. struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
  248. serio_unregister_port(drvdata->serio);
  249. free_irq(drvdata->irq, drvdata);
  250. clk_disable_unprepare(drvdata->clk);
  251. clk_put(drvdata->clk);
  252. iounmap(drvdata->reg_base);
  253. kfree(drvdata);
  254. return 0;
  255. }
  256. static const struct of_device_id sun4i_ps2_match[] = {
  257. { .compatible = "allwinner,sun4i-a10-ps2", },
  258. { },
  259. };
  260. MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
  261. static struct platform_driver sun4i_ps2_driver = {
  262. .probe = sun4i_ps2_probe,
  263. .remove = sun4i_ps2_remove,
  264. .driver = {
  265. .name = DRIVER_NAME,
  266. .of_match_table = sun4i_ps2_match,
  267. },
  268. };
  269. module_platform_driver(sun4i_ps2_driver);
  270. MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
  271. MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
  272. MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
  273. MODULE_LICENSE("GPL v2");