i8042.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * i8042 keyboard and mouse controller driver for Linux
  4. *
  5. * Copyright (c) 1999-2004 Vojtech Pavlik
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/types.h>
  9. #include <linux/delay.h>
  10. #include <linux/module.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/ioport.h>
  13. #include <linux/init.h>
  14. #include <linux/serio.h>
  15. #include <linux/err.h>
  16. #include <linux/rcupdate.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/i8042.h>
  19. #include <linux/slab.h>
  20. #include <linux/suspend.h>
  21. #include <linux/property.h>
  22. #include <asm/io.h>
  23. MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
  24. MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
  25. MODULE_LICENSE("GPL");
  26. static bool i8042_nokbd;
  27. module_param_named(nokbd, i8042_nokbd, bool, 0);
  28. MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
  29. static bool i8042_noaux;
  30. module_param_named(noaux, i8042_noaux, bool, 0);
  31. MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
  32. static bool i8042_nomux;
  33. module_param_named(nomux, i8042_nomux, bool, 0);
  34. MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
  35. static bool i8042_unlock;
  36. module_param_named(unlock, i8042_unlock, bool, 0);
  37. MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
  38. static bool i8042_probe_defer;
  39. module_param_named(probe_defer, i8042_probe_defer, bool, 0);
  40. MODULE_PARM_DESC(probe_defer, "Allow deferred probing.");
  41. enum i8042_controller_reset_mode {
  42. I8042_RESET_NEVER,
  43. I8042_RESET_ALWAYS,
  44. I8042_RESET_ON_S2RAM,
  45. #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM
  46. };
  47. static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT;
  48. static int i8042_set_reset(const char *val, const struct kernel_param *kp)
  49. {
  50. enum i8042_controller_reset_mode *arg = kp->arg;
  51. int error;
  52. bool reset;
  53. if (val) {
  54. error = kstrtobool(val, &reset);
  55. if (error)
  56. return error;
  57. } else {
  58. reset = true;
  59. }
  60. *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER;
  61. return 0;
  62. }
  63. static const struct kernel_param_ops param_ops_reset_param = {
  64. .flags = KERNEL_PARAM_OPS_FL_NOARG,
  65. .set = i8042_set_reset,
  66. };
  67. #define param_check_reset_param(name, p) \
  68. __param_check(name, p, enum i8042_controller_reset_mode)
  69. module_param_named(reset, i8042_reset, reset_param, 0);
  70. MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both");
  71. static bool i8042_direct;
  72. module_param_named(direct, i8042_direct, bool, 0);
  73. MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
  74. static bool i8042_dumbkbd;
  75. module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
  76. MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
  77. static bool i8042_noloop;
  78. module_param_named(noloop, i8042_noloop, bool, 0);
  79. MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
  80. static bool i8042_notimeout;
  81. module_param_named(notimeout, i8042_notimeout, bool, 0);
  82. MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
  83. static bool i8042_kbdreset;
  84. module_param_named(kbdreset, i8042_kbdreset, bool, 0);
  85. MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
  86. #ifdef CONFIG_X86
  87. static bool i8042_dritek;
  88. module_param_named(dritek, i8042_dritek, bool, 0);
  89. MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
  90. #endif
  91. #ifdef CONFIG_PNP
  92. static bool i8042_nopnp;
  93. module_param_named(nopnp, i8042_nopnp, bool, 0);
  94. MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
  95. #endif
  96. #define DEBUG
  97. #ifdef DEBUG
  98. static bool i8042_debug;
  99. module_param_named(debug, i8042_debug, bool, 0600);
  100. MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
  101. static bool i8042_unmask_kbd_data;
  102. module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600);
  103. MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]");
  104. #endif
  105. static bool i8042_present;
  106. static bool i8042_bypass_aux_irq_test;
  107. static char i8042_kbd_firmware_id[128];
  108. static char i8042_aux_firmware_id[128];
  109. static struct fwnode_handle *i8042_kbd_fwnode;
  110. #include "i8042.h"
  111. /*
  112. * i8042_lock protects serialization between i8042_command and
  113. * the interrupt handler.
  114. */
  115. static DEFINE_SPINLOCK(i8042_lock);
  116. /*
  117. * Writers to AUX and KBD ports as well as users issuing i8042_command
  118. * directly should acquire i8042_mutex (by means of calling
  119. * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
  120. * they do not disturb each other (unfortunately in many i8042
  121. * implementations write to one of the ports will immediately abort
  122. * command that is being processed by another port).
  123. */
  124. static DEFINE_MUTEX(i8042_mutex);
  125. struct i8042_port {
  126. struct serio *serio;
  127. int irq;
  128. bool exists;
  129. bool driver_bound;
  130. signed char mux;
  131. };
  132. #define I8042_KBD_PORT_NO 0
  133. #define I8042_AUX_PORT_NO 1
  134. #define I8042_MUX_PORT_NO 2
  135. #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
  136. static struct i8042_port i8042_ports[I8042_NUM_PORTS];
  137. static unsigned char i8042_initial_ctr;
  138. static unsigned char i8042_ctr;
  139. static bool i8042_mux_present;
  140. static bool i8042_kbd_irq_registered;
  141. static bool i8042_aux_irq_registered;
  142. static unsigned char i8042_suppress_kbd_ack;
  143. static struct platform_device *i8042_platform_device;
  144. static struct notifier_block i8042_kbd_bind_notifier_block;
  145. static irqreturn_t i8042_interrupt(int irq, void *dev_id);
  146. static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
  147. struct serio *serio);
  148. void i8042_lock_chip(void)
  149. {
  150. mutex_lock(&i8042_mutex);
  151. }
  152. EXPORT_SYMBOL(i8042_lock_chip);
  153. void i8042_unlock_chip(void)
  154. {
  155. mutex_unlock(&i8042_mutex);
  156. }
  157. EXPORT_SYMBOL(i8042_unlock_chip);
  158. int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
  159. struct serio *serio))
  160. {
  161. unsigned long flags;
  162. int ret = 0;
  163. spin_lock_irqsave(&i8042_lock, flags);
  164. if (i8042_platform_filter) {
  165. ret = -EBUSY;
  166. goto out;
  167. }
  168. i8042_platform_filter = filter;
  169. out:
  170. spin_unlock_irqrestore(&i8042_lock, flags);
  171. return ret;
  172. }
  173. EXPORT_SYMBOL(i8042_install_filter);
  174. int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
  175. struct serio *port))
  176. {
  177. unsigned long flags;
  178. int ret = 0;
  179. spin_lock_irqsave(&i8042_lock, flags);
  180. if (i8042_platform_filter != filter) {
  181. ret = -EINVAL;
  182. goto out;
  183. }
  184. i8042_platform_filter = NULL;
  185. out:
  186. spin_unlock_irqrestore(&i8042_lock, flags);
  187. return ret;
  188. }
  189. EXPORT_SYMBOL(i8042_remove_filter);
  190. /*
  191. * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
  192. * be ready for reading values from it / writing values to it.
  193. * Called always with i8042_lock held.
  194. */
  195. static int i8042_wait_read(void)
  196. {
  197. int i = 0;
  198. while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
  199. udelay(50);
  200. i++;
  201. }
  202. return -(i == I8042_CTL_TIMEOUT);
  203. }
  204. static int i8042_wait_write(void)
  205. {
  206. int i = 0;
  207. while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
  208. udelay(50);
  209. i++;
  210. }
  211. return -(i == I8042_CTL_TIMEOUT);
  212. }
  213. /*
  214. * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
  215. * of the i8042 down the toilet.
  216. */
  217. static int i8042_flush(void)
  218. {
  219. unsigned long flags;
  220. unsigned char data, str;
  221. int count = 0;
  222. int retval = 0;
  223. spin_lock_irqsave(&i8042_lock, flags);
  224. while ((str = i8042_read_status()) & I8042_STR_OBF) {
  225. if (count++ < I8042_BUFFER_SIZE) {
  226. udelay(50);
  227. data = i8042_read_data();
  228. dbg("%02x <- i8042 (flush, %s)\n",
  229. data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
  230. } else {
  231. retval = -EIO;
  232. break;
  233. }
  234. }
  235. spin_unlock_irqrestore(&i8042_lock, flags);
  236. return retval;
  237. }
  238. /*
  239. * i8042_command() executes a command on the i8042. It also sends the input
  240. * parameter(s) of the commands to it, and receives the output value(s). The
  241. * parameters are to be stored in the param array, and the output is placed
  242. * into the same array. The number of the parameters and output values is
  243. * encoded in bits 8-11 of the command number.
  244. */
  245. static int __i8042_command(unsigned char *param, int command)
  246. {
  247. int i, error;
  248. if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
  249. return -1;
  250. error = i8042_wait_write();
  251. if (error)
  252. return error;
  253. dbg("%02x -> i8042 (command)\n", command & 0xff);
  254. i8042_write_command(command & 0xff);
  255. for (i = 0; i < ((command >> 12) & 0xf); i++) {
  256. error = i8042_wait_write();
  257. if (error) {
  258. dbg(" -- i8042 (wait write timeout)\n");
  259. return error;
  260. }
  261. dbg("%02x -> i8042 (parameter)\n", param[i]);
  262. i8042_write_data(param[i]);
  263. }
  264. for (i = 0; i < ((command >> 8) & 0xf); i++) {
  265. error = i8042_wait_read();
  266. if (error) {
  267. dbg(" -- i8042 (wait read timeout)\n");
  268. return error;
  269. }
  270. if (command == I8042_CMD_AUX_LOOP &&
  271. !(i8042_read_status() & I8042_STR_AUXDATA)) {
  272. dbg(" -- i8042 (auxerr)\n");
  273. return -1;
  274. }
  275. param[i] = i8042_read_data();
  276. dbg("%02x <- i8042 (return)\n", param[i]);
  277. }
  278. return 0;
  279. }
  280. int i8042_command(unsigned char *param, int command)
  281. {
  282. unsigned long flags;
  283. int retval;
  284. if (!i8042_present)
  285. return -1;
  286. spin_lock_irqsave(&i8042_lock, flags);
  287. retval = __i8042_command(param, command);
  288. spin_unlock_irqrestore(&i8042_lock, flags);
  289. return retval;
  290. }
  291. EXPORT_SYMBOL(i8042_command);
  292. /*
  293. * i8042_kbd_write() sends a byte out through the keyboard interface.
  294. */
  295. static int i8042_kbd_write(struct serio *port, unsigned char c)
  296. {
  297. unsigned long flags;
  298. int retval = 0;
  299. spin_lock_irqsave(&i8042_lock, flags);
  300. if (!(retval = i8042_wait_write())) {
  301. dbg("%02x -> i8042 (kbd-data)\n", c);
  302. i8042_write_data(c);
  303. }
  304. spin_unlock_irqrestore(&i8042_lock, flags);
  305. return retval;
  306. }
  307. /*
  308. * i8042_aux_write() sends a byte out through the aux interface.
  309. */
  310. static int i8042_aux_write(struct serio *serio, unsigned char c)
  311. {
  312. struct i8042_port *port = serio->port_data;
  313. return i8042_command(&c, port->mux == -1 ?
  314. I8042_CMD_AUX_SEND :
  315. I8042_CMD_MUX_SEND + port->mux);
  316. }
  317. /*
  318. * i8042_port_close attempts to clear AUX or KBD port state by disabling
  319. * and then re-enabling it.
  320. */
  321. static void i8042_port_close(struct serio *serio)
  322. {
  323. int irq_bit;
  324. int disable_bit;
  325. const char *port_name;
  326. if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
  327. irq_bit = I8042_CTR_AUXINT;
  328. disable_bit = I8042_CTR_AUXDIS;
  329. port_name = "AUX";
  330. } else {
  331. irq_bit = I8042_CTR_KBDINT;
  332. disable_bit = I8042_CTR_KBDDIS;
  333. port_name = "KBD";
  334. }
  335. i8042_ctr &= ~irq_bit;
  336. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  337. pr_warn("Can't write CTR while closing %s port\n", port_name);
  338. udelay(50);
  339. i8042_ctr &= ~disable_bit;
  340. i8042_ctr |= irq_bit;
  341. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  342. pr_err("Can't reactivate %s port\n", port_name);
  343. /*
  344. * See if there is any data appeared while we were messing with
  345. * port state.
  346. */
  347. i8042_interrupt(0, NULL);
  348. }
  349. /*
  350. * i8042_start() is called by serio core when port is about to finish
  351. * registering. It will mark port as existing so i8042_interrupt can
  352. * start sending data through it.
  353. */
  354. static int i8042_start(struct serio *serio)
  355. {
  356. struct i8042_port *port = serio->port_data;
  357. device_set_wakeup_capable(&serio->dev, true);
  358. /*
  359. * On platforms using suspend-to-idle, allow the keyboard to
  360. * wake up the system from sleep by enabling keyboard wakeups
  361. * by default. This is consistent with keyboard wakeup
  362. * behavior on many platforms using suspend-to-RAM (ACPI S3)
  363. * by default.
  364. */
  365. if (pm_suspend_default_s2idle() &&
  366. serio == i8042_ports[I8042_KBD_PORT_NO].serio) {
  367. device_set_wakeup_enable(&serio->dev, true);
  368. }
  369. spin_lock_irq(&i8042_lock);
  370. port->exists = true;
  371. spin_unlock_irq(&i8042_lock);
  372. return 0;
  373. }
  374. /*
  375. * i8042_stop() marks serio port as non-existing so i8042_interrupt
  376. * will not try to send data to the port that is about to go away.
  377. * The function is called by serio core as part of unregister procedure.
  378. */
  379. static void i8042_stop(struct serio *serio)
  380. {
  381. struct i8042_port *port = serio->port_data;
  382. spin_lock_irq(&i8042_lock);
  383. port->exists = false;
  384. port->serio = NULL;
  385. spin_unlock_irq(&i8042_lock);
  386. /*
  387. * We need to make sure that interrupt handler finishes using
  388. * our serio port before we return from this function.
  389. * We synchronize with both AUX and KBD IRQs because there is
  390. * a (very unlikely) chance that AUX IRQ is raised for KBD port
  391. * and vice versa.
  392. */
  393. synchronize_irq(I8042_AUX_IRQ);
  394. synchronize_irq(I8042_KBD_IRQ);
  395. }
  396. /*
  397. * i8042_filter() filters out unwanted bytes from the input data stream.
  398. * It is called from i8042_interrupt and thus is running with interrupts
  399. * off and i8042_lock held.
  400. */
  401. static bool i8042_filter(unsigned char data, unsigned char str,
  402. struct serio *serio)
  403. {
  404. if (unlikely(i8042_suppress_kbd_ack)) {
  405. if ((~str & I8042_STR_AUXDATA) &&
  406. (data == 0xfa || data == 0xfe)) {
  407. i8042_suppress_kbd_ack--;
  408. dbg("Extra keyboard ACK - filtered out\n");
  409. return true;
  410. }
  411. }
  412. if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
  413. dbg("Filtered out by platform filter\n");
  414. return true;
  415. }
  416. return false;
  417. }
  418. /*
  419. * i8042_interrupt() is the most important function in this driver -
  420. * it handles the interrupts from the i8042, and sends incoming bytes
  421. * to the upper layers.
  422. */
  423. static irqreturn_t i8042_interrupt(int irq, void *dev_id)
  424. {
  425. struct i8042_port *port;
  426. struct serio *serio;
  427. unsigned long flags;
  428. unsigned char str, data;
  429. unsigned int dfl;
  430. unsigned int port_no;
  431. bool filtered;
  432. int ret = 1;
  433. spin_lock_irqsave(&i8042_lock, flags);
  434. str = i8042_read_status();
  435. if (unlikely(~str & I8042_STR_OBF)) {
  436. spin_unlock_irqrestore(&i8042_lock, flags);
  437. if (irq)
  438. dbg("Interrupt %d, without any data\n", irq);
  439. ret = 0;
  440. goto out;
  441. }
  442. data = i8042_read_data();
  443. if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
  444. static unsigned long last_transmit;
  445. static unsigned char last_str;
  446. dfl = 0;
  447. if (str & I8042_STR_MUXERR) {
  448. dbg("MUX error, status is %02x, data is %02x\n",
  449. str, data);
  450. /*
  451. * When MUXERR condition is signalled the data register can only contain
  452. * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
  453. * it is not always the case. Some KBCs also report 0xfc when there is
  454. * nothing connected to the port while others sometimes get confused which
  455. * port the data came from and signal error leaving the data intact. They
  456. * _do not_ revert to legacy mode (actually I've never seen KBC reverting
  457. * to legacy mode yet, when we see one we'll add proper handling).
  458. * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
  459. * rest assume that the data came from the same serio last byte
  460. * was transmitted (if transmission happened not too long ago).
  461. */
  462. switch (data) {
  463. default:
  464. if (time_before(jiffies, last_transmit + HZ/10)) {
  465. str = last_str;
  466. break;
  467. }
  468. fallthrough; /* report timeout */
  469. case 0xfc:
  470. case 0xfd:
  471. case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
  472. case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
  473. }
  474. }
  475. port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
  476. last_str = str;
  477. last_transmit = jiffies;
  478. } else {
  479. dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
  480. ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
  481. port_no = (str & I8042_STR_AUXDATA) ?
  482. I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
  483. }
  484. port = &i8042_ports[port_no];
  485. serio = port->exists ? port->serio : NULL;
  486. filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n",
  487. port_no, irq,
  488. dfl & SERIO_PARITY ? ", bad parity" : "",
  489. dfl & SERIO_TIMEOUT ? ", timeout" : "");
  490. filtered = i8042_filter(data, str, serio);
  491. spin_unlock_irqrestore(&i8042_lock, flags);
  492. if (likely(serio && !filtered))
  493. serio_interrupt(serio, data, dfl);
  494. out:
  495. return IRQ_RETVAL(ret);
  496. }
  497. /*
  498. * i8042_enable_kbd_port enables keyboard port on chip
  499. */
  500. static int i8042_enable_kbd_port(void)
  501. {
  502. i8042_ctr &= ~I8042_CTR_KBDDIS;
  503. i8042_ctr |= I8042_CTR_KBDINT;
  504. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  505. i8042_ctr &= ~I8042_CTR_KBDINT;
  506. i8042_ctr |= I8042_CTR_KBDDIS;
  507. pr_err("Failed to enable KBD port\n");
  508. return -EIO;
  509. }
  510. return 0;
  511. }
  512. /*
  513. * i8042_enable_aux_port enables AUX (mouse) port on chip
  514. */
  515. static int i8042_enable_aux_port(void)
  516. {
  517. i8042_ctr &= ~I8042_CTR_AUXDIS;
  518. i8042_ctr |= I8042_CTR_AUXINT;
  519. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  520. i8042_ctr &= ~I8042_CTR_AUXINT;
  521. i8042_ctr |= I8042_CTR_AUXDIS;
  522. pr_err("Failed to enable AUX port\n");
  523. return -EIO;
  524. }
  525. return 0;
  526. }
  527. /*
  528. * i8042_enable_mux_ports enables 4 individual AUX ports after
  529. * the controller has been switched into Multiplexed mode
  530. */
  531. static int i8042_enable_mux_ports(void)
  532. {
  533. unsigned char param;
  534. int i;
  535. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  536. i8042_command(&param, I8042_CMD_MUX_PFX + i);
  537. i8042_command(&param, I8042_CMD_AUX_ENABLE);
  538. }
  539. return i8042_enable_aux_port();
  540. }
  541. /*
  542. * i8042_set_mux_mode checks whether the controller has an
  543. * active multiplexor and puts the chip into Multiplexed (true)
  544. * or Legacy (false) mode.
  545. */
  546. static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
  547. {
  548. unsigned char param, val;
  549. /*
  550. * Get rid of bytes in the queue.
  551. */
  552. i8042_flush();
  553. /*
  554. * Internal loopback test - send three bytes, they should come back from the
  555. * mouse interface, the last should be version.
  556. */
  557. param = val = 0xf0;
  558. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != val)
  559. return -1;
  560. param = val = multiplex ? 0x56 : 0xf6;
  561. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != val)
  562. return -1;
  563. param = val = multiplex ? 0xa4 : 0xa5;
  564. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == val)
  565. return -1;
  566. /*
  567. * Workaround for interference with USB Legacy emulation
  568. * that causes a v10.12 MUX to be found.
  569. */
  570. if (param == 0xac)
  571. return -1;
  572. if (mux_version)
  573. *mux_version = param;
  574. return 0;
  575. }
  576. /*
  577. * i8042_check_mux() checks whether the controller supports the PS/2 Active
  578. * Multiplexing specification by Synaptics, Phoenix, Insyde and
  579. * LCS/Telegraphics.
  580. */
  581. static int i8042_check_mux(void)
  582. {
  583. unsigned char mux_version;
  584. if (i8042_set_mux_mode(true, &mux_version))
  585. return -1;
  586. pr_info("Detected active multiplexing controller, rev %d.%d\n",
  587. (mux_version >> 4) & 0xf, mux_version & 0xf);
  588. /*
  589. * Disable all muxed ports by disabling AUX.
  590. */
  591. i8042_ctr |= I8042_CTR_AUXDIS;
  592. i8042_ctr &= ~I8042_CTR_AUXINT;
  593. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  594. pr_err("Failed to disable AUX port, can't use MUX\n");
  595. return -EIO;
  596. }
  597. i8042_mux_present = true;
  598. return 0;
  599. }
  600. /*
  601. * The following is used to test AUX IRQ delivery.
  602. */
  603. static struct completion i8042_aux_irq_delivered;
  604. static bool i8042_irq_being_tested;
  605. static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id)
  606. {
  607. unsigned long flags;
  608. unsigned char str, data;
  609. int ret = 0;
  610. spin_lock_irqsave(&i8042_lock, flags);
  611. str = i8042_read_status();
  612. if (str & I8042_STR_OBF) {
  613. data = i8042_read_data();
  614. dbg("%02x <- i8042 (aux_test_irq, %s)\n",
  615. data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
  616. if (i8042_irq_being_tested &&
  617. data == 0xa5 && (str & I8042_STR_AUXDATA))
  618. complete(&i8042_aux_irq_delivered);
  619. ret = 1;
  620. }
  621. spin_unlock_irqrestore(&i8042_lock, flags);
  622. return IRQ_RETVAL(ret);
  623. }
  624. /*
  625. * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
  626. * verifies success by readinng CTR. Used when testing for presence of AUX
  627. * port.
  628. */
  629. static int i8042_toggle_aux(bool on)
  630. {
  631. unsigned char param;
  632. int i;
  633. if (i8042_command(&param,
  634. on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
  635. return -1;
  636. /* some chips need some time to set the I8042_CTR_AUXDIS bit */
  637. for (i = 0; i < 100; i++) {
  638. udelay(50);
  639. if (i8042_command(&param, I8042_CMD_CTL_RCTR))
  640. return -1;
  641. if (!(param & I8042_CTR_AUXDIS) == on)
  642. return 0;
  643. }
  644. return -1;
  645. }
  646. /*
  647. * i8042_check_aux() applies as much paranoia as it can at detecting
  648. * the presence of an AUX interface.
  649. */
  650. static int i8042_check_aux(void)
  651. {
  652. int retval = -1;
  653. bool irq_registered = false;
  654. bool aux_loop_broken = false;
  655. unsigned long flags;
  656. unsigned char param;
  657. /*
  658. * Get rid of bytes in the queue.
  659. */
  660. i8042_flush();
  661. /*
  662. * Internal loopback test - filters out AT-type i8042's. Unfortunately
  663. * SiS screwed up and their 5597 doesn't support the LOOP command even
  664. * though it has an AUX port.
  665. */
  666. param = 0x5a;
  667. retval = i8042_command(&param, I8042_CMD_AUX_LOOP);
  668. if (retval || param != 0x5a) {
  669. /*
  670. * External connection test - filters out AT-soldered PS/2 i8042's
  671. * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
  672. * 0xfa - no error on some notebooks which ignore the spec
  673. * Because it's common for chipsets to return error on perfectly functioning
  674. * AUX ports, we test for this only when the LOOP command failed.
  675. */
  676. if (i8042_command(&param, I8042_CMD_AUX_TEST) ||
  677. (param && param != 0xfa && param != 0xff))
  678. return -1;
  679. /*
  680. * If AUX_LOOP completed without error but returned unexpected data
  681. * mark it as broken
  682. */
  683. if (!retval)
  684. aux_loop_broken = true;
  685. }
  686. /*
  687. * Bit assignment test - filters out PS/2 i8042's in AT mode
  688. */
  689. if (i8042_toggle_aux(false)) {
  690. pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
  691. pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
  692. }
  693. if (i8042_toggle_aux(true))
  694. return -1;
  695. /*
  696. * Reset keyboard (needed on some laptops to successfully detect
  697. * touchpad, e.g., some Gigabyte laptop models with Elantech
  698. * touchpads).
  699. */
  700. if (i8042_kbdreset) {
  701. pr_warn("Attempting to reset device connected to KBD port\n");
  702. i8042_kbd_write(NULL, (unsigned char) 0xff);
  703. }
  704. /*
  705. * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
  706. * used it for a PCI card or somethig else.
  707. */
  708. if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
  709. /*
  710. * Without LOOP command we can't test AUX IRQ delivery. Assume the port
  711. * is working and hope we are right.
  712. */
  713. retval = 0;
  714. goto out;
  715. }
  716. if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
  717. "i8042", i8042_platform_device))
  718. goto out;
  719. irq_registered = true;
  720. if (i8042_enable_aux_port())
  721. goto out;
  722. spin_lock_irqsave(&i8042_lock, flags);
  723. init_completion(&i8042_aux_irq_delivered);
  724. i8042_irq_being_tested = true;
  725. param = 0xa5;
  726. retval = __i8042_command(&param, I8042_CMD_AUX_LOOP & 0xf0ff);
  727. spin_unlock_irqrestore(&i8042_lock, flags);
  728. if (retval)
  729. goto out;
  730. if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
  731. msecs_to_jiffies(250)) == 0) {
  732. /*
  733. * AUX IRQ was never delivered so we need to flush the controller to
  734. * get rid of the byte we put there; otherwise keyboard may not work.
  735. */
  736. dbg(" -- i8042 (aux irq test timeout)\n");
  737. i8042_flush();
  738. retval = -1;
  739. }
  740. out:
  741. /*
  742. * Disable the interface.
  743. */
  744. i8042_ctr |= I8042_CTR_AUXDIS;
  745. i8042_ctr &= ~I8042_CTR_AUXINT;
  746. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  747. retval = -1;
  748. if (irq_registered)
  749. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  750. return retval;
  751. }
  752. static int i8042_controller_check(void)
  753. {
  754. if (i8042_flush()) {
  755. pr_info("No controller found\n");
  756. return -ENODEV;
  757. }
  758. return 0;
  759. }
  760. static int i8042_controller_selftest(void)
  761. {
  762. unsigned char param;
  763. int i = 0;
  764. /*
  765. * We try this 5 times; on some really fragile systems this does not
  766. * take the first time...
  767. */
  768. do {
  769. if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
  770. pr_err("i8042 controller selftest timeout\n");
  771. return -ENODEV;
  772. }
  773. if (param == I8042_RET_CTL_TEST)
  774. return 0;
  775. dbg("i8042 controller selftest: %#x != %#x\n",
  776. param, I8042_RET_CTL_TEST);
  777. msleep(50);
  778. } while (i++ < 5);
  779. #ifdef CONFIG_X86
  780. /*
  781. * On x86, we don't fail entire i8042 initialization if controller
  782. * reset fails in hopes that keyboard port will still be functional
  783. * and user will still get a working keyboard. This is especially
  784. * important on netbooks. On other arches we trust hardware more.
  785. */
  786. pr_info("giving up on controller selftest, continuing anyway...\n");
  787. return 0;
  788. #else
  789. pr_err("i8042 controller selftest failed\n");
  790. return -EIO;
  791. #endif
  792. }
  793. /*
  794. * i8042_controller init initializes the i8042 controller, and,
  795. * most importantly, sets it into non-xlated mode if that's
  796. * desired.
  797. */
  798. static int i8042_controller_init(void)
  799. {
  800. unsigned long flags;
  801. int n = 0;
  802. unsigned char ctr[2];
  803. /*
  804. * Save the CTR for restore on unload / reboot.
  805. */
  806. do {
  807. if (n >= 10) {
  808. pr_err("Unable to get stable CTR read\n");
  809. return -EIO;
  810. }
  811. if (n != 0)
  812. udelay(50);
  813. if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
  814. pr_err("Can't read CTR while initializing i8042\n");
  815. return i8042_probe_defer ? -EPROBE_DEFER : -EIO;
  816. }
  817. } while (n < 2 || ctr[0] != ctr[1]);
  818. i8042_initial_ctr = i8042_ctr = ctr[0];
  819. /*
  820. * Disable the keyboard interface and interrupt.
  821. */
  822. i8042_ctr |= I8042_CTR_KBDDIS;
  823. i8042_ctr &= ~I8042_CTR_KBDINT;
  824. /*
  825. * Handle keylock.
  826. */
  827. spin_lock_irqsave(&i8042_lock, flags);
  828. if (~i8042_read_status() & I8042_STR_KEYLOCK) {
  829. if (i8042_unlock)
  830. i8042_ctr |= I8042_CTR_IGNKEYLOCK;
  831. else
  832. pr_warn("Warning: Keylock active\n");
  833. }
  834. spin_unlock_irqrestore(&i8042_lock, flags);
  835. /*
  836. * If the chip is configured into nontranslated mode by the BIOS, don't
  837. * bother enabling translating and be happy.
  838. */
  839. if (~i8042_ctr & I8042_CTR_XLATE)
  840. i8042_direct = true;
  841. /*
  842. * Set nontranslated mode for the kbd interface if requested by an option.
  843. * After this the kbd interface becomes a simple serial in/out, like the aux
  844. * interface is. We don't do this by default, since it can confuse notebook
  845. * BIOSes.
  846. */
  847. if (i8042_direct)
  848. i8042_ctr &= ~I8042_CTR_XLATE;
  849. /*
  850. * Write CTR back.
  851. */
  852. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  853. pr_err("Can't write CTR while initializing i8042\n");
  854. return -EIO;
  855. }
  856. /*
  857. * Flush whatever accumulated while we were disabling keyboard port.
  858. */
  859. i8042_flush();
  860. return 0;
  861. }
  862. /*
  863. * Reset the controller and reset CRT to the original value set by BIOS.
  864. */
  865. static void i8042_controller_reset(bool s2r_wants_reset)
  866. {
  867. i8042_flush();
  868. /*
  869. * Disable both KBD and AUX interfaces so they don't get in the way
  870. */
  871. i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
  872. i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
  873. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  874. pr_warn("Can't write CTR while resetting\n");
  875. /*
  876. * Disable MUX mode if present.
  877. */
  878. if (i8042_mux_present)
  879. i8042_set_mux_mode(false, NULL);
  880. /*
  881. * Reset the controller if requested.
  882. */
  883. if (i8042_reset == I8042_RESET_ALWAYS ||
  884. (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
  885. i8042_controller_selftest();
  886. }
  887. /*
  888. * Restore the original control register setting.
  889. */
  890. if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
  891. pr_warn("Can't restore CTR\n");
  892. }
  893. /*
  894. * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
  895. * when kernel panics. Flashing LEDs is useful for users running X who may
  896. * not see the console and will help distinguishing panics from "real"
  897. * lockups.
  898. *
  899. * Note that DELAY has a limit of 10ms so we will not get stuck here
  900. * waiting for KBC to free up even if KBD interrupt is off
  901. */
  902. #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
  903. static long i8042_panic_blink(int state)
  904. {
  905. long delay = 0;
  906. char led;
  907. led = (state) ? 0x01 | 0x04 : 0;
  908. while (i8042_read_status() & I8042_STR_IBF)
  909. DELAY;
  910. dbg("%02x -> i8042 (panic blink)\n", 0xed);
  911. i8042_suppress_kbd_ack = 2;
  912. i8042_write_data(0xed); /* set leds */
  913. DELAY;
  914. while (i8042_read_status() & I8042_STR_IBF)
  915. DELAY;
  916. DELAY;
  917. dbg("%02x -> i8042 (panic blink)\n", led);
  918. i8042_write_data(led);
  919. DELAY;
  920. return delay;
  921. }
  922. #undef DELAY
  923. #ifdef CONFIG_X86
  924. static void i8042_dritek_enable(void)
  925. {
  926. unsigned char param = 0x90;
  927. int error;
  928. error = i8042_command(&param, 0x1059);
  929. if (error)
  930. pr_warn("Failed to enable DRITEK extension: %d\n", error);
  931. }
  932. #endif
  933. #ifdef CONFIG_PM
  934. /*
  935. * Here we try to reset everything back to a state we had
  936. * before suspending.
  937. */
  938. static int i8042_controller_resume(bool s2r_wants_reset)
  939. {
  940. int error;
  941. error = i8042_controller_check();
  942. if (error)
  943. return error;
  944. if (i8042_reset == I8042_RESET_ALWAYS ||
  945. (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
  946. error = i8042_controller_selftest();
  947. if (error)
  948. return error;
  949. }
  950. /*
  951. * Restore original CTR value and disable all ports
  952. */
  953. i8042_ctr = i8042_initial_ctr;
  954. if (i8042_direct)
  955. i8042_ctr &= ~I8042_CTR_XLATE;
  956. i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
  957. i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
  958. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  959. pr_warn("Can't write CTR to resume, retrying...\n");
  960. msleep(50);
  961. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  962. pr_err("CTR write retry failed\n");
  963. return -EIO;
  964. }
  965. }
  966. #ifdef CONFIG_X86
  967. if (i8042_dritek)
  968. i8042_dritek_enable();
  969. #endif
  970. if (i8042_mux_present) {
  971. if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
  972. pr_warn("failed to resume active multiplexor, mouse won't work\n");
  973. } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
  974. i8042_enable_aux_port();
  975. if (i8042_ports[I8042_KBD_PORT_NO].serio)
  976. i8042_enable_kbd_port();
  977. i8042_interrupt(0, NULL);
  978. return 0;
  979. }
  980. /*
  981. * Here we try to restore the original BIOS settings to avoid
  982. * upsetting it.
  983. */
  984. static int i8042_pm_suspend(struct device *dev)
  985. {
  986. int i;
  987. if (pm_suspend_via_firmware())
  988. i8042_controller_reset(true);
  989. /* Set up serio interrupts for system wakeup. */
  990. for (i = 0; i < I8042_NUM_PORTS; i++) {
  991. struct serio *serio = i8042_ports[i].serio;
  992. if (serio && device_may_wakeup(&serio->dev))
  993. enable_irq_wake(i8042_ports[i].irq);
  994. }
  995. return 0;
  996. }
  997. static int i8042_pm_resume_noirq(struct device *dev)
  998. {
  999. if (!pm_resume_via_firmware())
  1000. i8042_interrupt(0, NULL);
  1001. return 0;
  1002. }
  1003. static int i8042_pm_resume(struct device *dev)
  1004. {
  1005. bool want_reset;
  1006. int i;
  1007. for (i = 0; i < I8042_NUM_PORTS; i++) {
  1008. struct serio *serio = i8042_ports[i].serio;
  1009. if (serio && device_may_wakeup(&serio->dev))
  1010. disable_irq_wake(i8042_ports[i].irq);
  1011. }
  1012. /*
  1013. * If platform firmware was not going to be involved in suspend, we did
  1014. * not restore the controller state to whatever it had been at boot
  1015. * time, so we do not need to do anything.
  1016. */
  1017. if (!pm_suspend_via_firmware())
  1018. return 0;
  1019. /*
  1020. * We only need to reset the controller if we are resuming after handing
  1021. * off control to the platform firmware, otherwise we can simply restore
  1022. * the mode.
  1023. */
  1024. want_reset = pm_resume_via_firmware();
  1025. return i8042_controller_resume(want_reset);
  1026. }
  1027. static int i8042_pm_thaw(struct device *dev)
  1028. {
  1029. i8042_interrupt(0, NULL);
  1030. return 0;
  1031. }
  1032. static int i8042_pm_reset(struct device *dev)
  1033. {
  1034. i8042_controller_reset(false);
  1035. return 0;
  1036. }
  1037. static int i8042_pm_restore(struct device *dev)
  1038. {
  1039. return i8042_controller_resume(false);
  1040. }
  1041. static const struct dev_pm_ops i8042_pm_ops = {
  1042. .suspend = i8042_pm_suspend,
  1043. .resume_noirq = i8042_pm_resume_noirq,
  1044. .resume = i8042_pm_resume,
  1045. .thaw = i8042_pm_thaw,
  1046. .poweroff = i8042_pm_reset,
  1047. .restore = i8042_pm_restore,
  1048. };
  1049. #endif /* CONFIG_PM */
  1050. /*
  1051. * We need to reset the 8042 back to original mode on system shutdown,
  1052. * because otherwise BIOSes will be confused.
  1053. */
  1054. static void i8042_shutdown(struct platform_device *dev)
  1055. {
  1056. i8042_controller_reset(false);
  1057. }
  1058. static int i8042_create_kbd_port(void)
  1059. {
  1060. struct serio *serio;
  1061. struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
  1062. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  1063. if (!serio)
  1064. return -ENOMEM;
  1065. serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
  1066. serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
  1067. serio->start = i8042_start;
  1068. serio->stop = i8042_stop;
  1069. serio->close = i8042_port_close;
  1070. serio->ps2_cmd_mutex = &i8042_mutex;
  1071. serio->port_data = port;
  1072. serio->dev.parent = &i8042_platform_device->dev;
  1073. strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
  1074. strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
  1075. strlcpy(serio->firmware_id, i8042_kbd_firmware_id,
  1076. sizeof(serio->firmware_id));
  1077. set_primary_fwnode(&serio->dev, i8042_kbd_fwnode);
  1078. port->serio = serio;
  1079. port->irq = I8042_KBD_IRQ;
  1080. return 0;
  1081. }
  1082. static int i8042_create_aux_port(int idx)
  1083. {
  1084. struct serio *serio;
  1085. int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
  1086. struct i8042_port *port = &i8042_ports[port_no];
  1087. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  1088. if (!serio)
  1089. return -ENOMEM;
  1090. serio->id.type = SERIO_8042;
  1091. serio->write = i8042_aux_write;
  1092. serio->start = i8042_start;
  1093. serio->stop = i8042_stop;
  1094. serio->ps2_cmd_mutex = &i8042_mutex;
  1095. serio->port_data = port;
  1096. serio->dev.parent = &i8042_platform_device->dev;
  1097. if (idx < 0) {
  1098. strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
  1099. strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
  1100. strlcpy(serio->firmware_id, i8042_aux_firmware_id,
  1101. sizeof(serio->firmware_id));
  1102. serio->close = i8042_port_close;
  1103. } else {
  1104. snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
  1105. snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
  1106. strlcpy(serio->firmware_id, i8042_aux_firmware_id,
  1107. sizeof(serio->firmware_id));
  1108. }
  1109. port->serio = serio;
  1110. port->mux = idx;
  1111. port->irq = I8042_AUX_IRQ;
  1112. return 0;
  1113. }
  1114. static void i8042_free_kbd_port(void)
  1115. {
  1116. kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
  1117. i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
  1118. }
  1119. static void i8042_free_aux_ports(void)
  1120. {
  1121. int i;
  1122. for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
  1123. kfree(i8042_ports[i].serio);
  1124. i8042_ports[i].serio = NULL;
  1125. }
  1126. }
  1127. static void i8042_register_ports(void)
  1128. {
  1129. int i;
  1130. for (i = 0; i < I8042_NUM_PORTS; i++) {
  1131. struct serio *serio = i8042_ports[i].serio;
  1132. if (!serio)
  1133. continue;
  1134. printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
  1135. serio->name,
  1136. (unsigned long) I8042_DATA_REG,
  1137. (unsigned long) I8042_COMMAND_REG,
  1138. i8042_ports[i].irq);
  1139. serio_register_port(serio);
  1140. }
  1141. }
  1142. static void i8042_unregister_ports(void)
  1143. {
  1144. int i;
  1145. for (i = 0; i < I8042_NUM_PORTS; i++) {
  1146. if (i8042_ports[i].serio) {
  1147. serio_unregister_port(i8042_ports[i].serio);
  1148. i8042_ports[i].serio = NULL;
  1149. }
  1150. }
  1151. }
  1152. static void i8042_free_irqs(void)
  1153. {
  1154. if (i8042_aux_irq_registered)
  1155. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  1156. if (i8042_kbd_irq_registered)
  1157. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  1158. i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
  1159. }
  1160. static int i8042_setup_aux(void)
  1161. {
  1162. int (*aux_enable)(void);
  1163. int error;
  1164. int i;
  1165. if (i8042_check_aux())
  1166. return -ENODEV;
  1167. if (i8042_nomux || i8042_check_mux()) {
  1168. error = i8042_create_aux_port(-1);
  1169. if (error)
  1170. goto err_free_ports;
  1171. aux_enable = i8042_enable_aux_port;
  1172. } else {
  1173. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  1174. error = i8042_create_aux_port(i);
  1175. if (error)
  1176. goto err_free_ports;
  1177. }
  1178. aux_enable = i8042_enable_mux_ports;
  1179. }
  1180. error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
  1181. "i8042", i8042_platform_device);
  1182. if (error)
  1183. goto err_free_ports;
  1184. error = aux_enable();
  1185. if (error)
  1186. goto err_free_irq;
  1187. i8042_aux_irq_registered = true;
  1188. return 0;
  1189. err_free_irq:
  1190. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  1191. err_free_ports:
  1192. i8042_free_aux_ports();
  1193. return error;
  1194. }
  1195. static int i8042_setup_kbd(void)
  1196. {
  1197. int error;
  1198. error = i8042_create_kbd_port();
  1199. if (error)
  1200. return error;
  1201. error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
  1202. "i8042", i8042_platform_device);
  1203. if (error)
  1204. goto err_free_port;
  1205. error = i8042_enable_kbd_port();
  1206. if (error)
  1207. goto err_free_irq;
  1208. i8042_kbd_irq_registered = true;
  1209. return 0;
  1210. err_free_irq:
  1211. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  1212. err_free_port:
  1213. i8042_free_kbd_port();
  1214. return error;
  1215. }
  1216. static int i8042_kbd_bind_notifier(struct notifier_block *nb,
  1217. unsigned long action, void *data)
  1218. {
  1219. struct device *dev = data;
  1220. struct serio *serio = to_serio_port(dev);
  1221. struct i8042_port *port = serio->port_data;
  1222. if (serio != i8042_ports[I8042_KBD_PORT_NO].serio)
  1223. return 0;
  1224. switch (action) {
  1225. case BUS_NOTIFY_BOUND_DRIVER:
  1226. port->driver_bound = true;
  1227. break;
  1228. case BUS_NOTIFY_UNBIND_DRIVER:
  1229. port->driver_bound = false;
  1230. break;
  1231. }
  1232. return 0;
  1233. }
  1234. static int i8042_probe(struct platform_device *dev)
  1235. {
  1236. int error;
  1237. i8042_platform_device = dev;
  1238. if (i8042_reset == I8042_RESET_ALWAYS) {
  1239. error = i8042_controller_selftest();
  1240. if (error)
  1241. return error;
  1242. }
  1243. error = i8042_controller_init();
  1244. if (error)
  1245. return error;
  1246. #ifdef CONFIG_X86
  1247. if (i8042_dritek)
  1248. i8042_dritek_enable();
  1249. #endif
  1250. if (!i8042_noaux) {
  1251. error = i8042_setup_aux();
  1252. if (error && error != -ENODEV && error != -EBUSY)
  1253. goto out_fail;
  1254. }
  1255. if (!i8042_nokbd) {
  1256. error = i8042_setup_kbd();
  1257. if (error)
  1258. goto out_fail;
  1259. }
  1260. /*
  1261. * Ok, everything is ready, let's register all serio ports
  1262. */
  1263. i8042_register_ports();
  1264. return 0;
  1265. out_fail:
  1266. i8042_free_aux_ports(); /* in case KBD failed but AUX not */
  1267. i8042_free_irqs();
  1268. i8042_controller_reset(false);
  1269. i8042_platform_device = NULL;
  1270. return error;
  1271. }
  1272. static int i8042_remove(struct platform_device *dev)
  1273. {
  1274. i8042_unregister_ports();
  1275. i8042_free_irqs();
  1276. i8042_controller_reset(false);
  1277. i8042_platform_device = NULL;
  1278. return 0;
  1279. }
  1280. static struct platform_driver i8042_driver = {
  1281. .driver = {
  1282. .name = "i8042",
  1283. #ifdef CONFIG_PM
  1284. .pm = &i8042_pm_ops,
  1285. #endif
  1286. },
  1287. .probe = i8042_probe,
  1288. .remove = i8042_remove,
  1289. .shutdown = i8042_shutdown,
  1290. };
  1291. static struct notifier_block i8042_kbd_bind_notifier_block = {
  1292. .notifier_call = i8042_kbd_bind_notifier,
  1293. };
  1294. static int __init i8042_init(void)
  1295. {
  1296. int err;
  1297. dbg_init();
  1298. err = i8042_platform_init();
  1299. if (err)
  1300. return (err == -ENODEV) ? 0 : err;
  1301. err = i8042_controller_check();
  1302. if (err)
  1303. goto err_platform_exit;
  1304. /* Set this before creating the dev to allow i8042_command to work right away */
  1305. i8042_present = true;
  1306. err = platform_driver_register(&i8042_driver);
  1307. if (err)
  1308. goto err_platform_exit;
  1309. i8042_platform_device = platform_device_alloc("i8042", -1);
  1310. if (!i8042_platform_device) {
  1311. err = -ENOMEM;
  1312. goto err_unregister_driver;
  1313. }
  1314. err = platform_device_add(i8042_platform_device);
  1315. if (err)
  1316. goto err_free_device;
  1317. bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
  1318. panic_blink = i8042_panic_blink;
  1319. return 0;
  1320. err_free_device:
  1321. platform_device_put(i8042_platform_device);
  1322. err_unregister_driver:
  1323. platform_driver_unregister(&i8042_driver);
  1324. err_platform_exit:
  1325. i8042_platform_exit();
  1326. return err;
  1327. }
  1328. static void __exit i8042_exit(void)
  1329. {
  1330. if (!i8042_present)
  1331. return;
  1332. platform_device_unregister(i8042_platform_device);
  1333. platform_driver_unregister(&i8042_driver);
  1334. i8042_platform_exit();
  1335. bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
  1336. panic_blink = NULL;
  1337. }
  1338. module_init(i8042_init);
  1339. module_exit(i8042_exit);