rmi_f34v7.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016, Zodiac Inflight Innovations
  4. * Copyright (c) 2007-2016, Synaptics Incorporated
  5. * Copyright (C) 2012 Alexandra Chin <alexandra.chin@tw.synaptics.com>
  6. * Copyright (C) 2012 Scott Lin <scott.lin@tw.synaptics.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/kernel.h>
  10. #include <linux/rmi.h>
  11. #include <linux/firmware.h>
  12. #include <linux/delay.h>
  13. #include <linux/slab.h>
  14. #include <linux/jiffies.h>
  15. #include <asm/unaligned.h>
  16. #include "rmi_driver.h"
  17. #include "rmi_f34.h"
  18. static int rmi_f34v7_read_flash_status(struct f34_data *f34)
  19. {
  20. u8 status;
  21. u8 command;
  22. int ret;
  23. ret = rmi_read_block(f34->fn->rmi_dev,
  24. f34->fn->fd.data_base_addr + f34->v7.off.flash_status,
  25. &status,
  26. sizeof(status));
  27. if (ret < 0) {
  28. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  29. "%s: Error %d reading flash status\n", __func__, ret);
  30. return ret;
  31. }
  32. f34->v7.in_bl_mode = status >> 7;
  33. f34->v7.flash_status = status & 0x1f;
  34. if (f34->v7.flash_status != 0x00) {
  35. dev_err(&f34->fn->dev, "%s: status=%d, command=0x%02x\n",
  36. __func__, f34->v7.flash_status, f34->v7.command);
  37. }
  38. ret = rmi_read_block(f34->fn->rmi_dev,
  39. f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd,
  40. &command,
  41. sizeof(command));
  42. if (ret < 0) {
  43. dev_err(&f34->fn->dev, "%s: Failed to read flash command\n",
  44. __func__);
  45. return ret;
  46. }
  47. f34->v7.command = command;
  48. return 0;
  49. }
  50. static int rmi_f34v7_wait_for_idle(struct f34_data *f34, int timeout_ms)
  51. {
  52. unsigned long timeout;
  53. timeout = msecs_to_jiffies(timeout_ms);
  54. if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) {
  55. dev_warn(&f34->fn->dev, "%s: Timed out waiting for idle status\n",
  56. __func__);
  57. return -ETIMEDOUT;
  58. }
  59. return 0;
  60. }
  61. static int rmi_f34v7_write_command_single_transaction(struct f34_data *f34,
  62. u8 cmd)
  63. {
  64. int ret;
  65. u8 base;
  66. struct f34v7_data_1_5 data_1_5;
  67. base = f34->fn->fd.data_base_addr;
  68. memset(&data_1_5, 0, sizeof(data_1_5));
  69. switch (cmd) {
  70. case v7_CMD_ERASE_ALL:
  71. data_1_5.partition_id = CORE_CODE_PARTITION;
  72. data_1_5.command = CMD_V7_ERASE_AP;
  73. break;
  74. case v7_CMD_ERASE_UI_FIRMWARE:
  75. data_1_5.partition_id = CORE_CODE_PARTITION;
  76. data_1_5.command = CMD_V7_ERASE;
  77. break;
  78. case v7_CMD_ERASE_BL_CONFIG:
  79. data_1_5.partition_id = GLOBAL_PARAMETERS_PARTITION;
  80. data_1_5.command = CMD_V7_ERASE;
  81. break;
  82. case v7_CMD_ERASE_UI_CONFIG:
  83. data_1_5.partition_id = CORE_CONFIG_PARTITION;
  84. data_1_5.command = CMD_V7_ERASE;
  85. break;
  86. case v7_CMD_ERASE_DISP_CONFIG:
  87. data_1_5.partition_id = DISPLAY_CONFIG_PARTITION;
  88. data_1_5.command = CMD_V7_ERASE;
  89. break;
  90. case v7_CMD_ERASE_FLASH_CONFIG:
  91. data_1_5.partition_id = FLASH_CONFIG_PARTITION;
  92. data_1_5.command = CMD_V7_ERASE;
  93. break;
  94. case v7_CMD_ERASE_GUEST_CODE:
  95. data_1_5.partition_id = GUEST_CODE_PARTITION;
  96. data_1_5.command = CMD_V7_ERASE;
  97. break;
  98. case v7_CMD_ENABLE_FLASH_PROG:
  99. data_1_5.partition_id = BOOTLOADER_PARTITION;
  100. data_1_5.command = CMD_V7_ENTER_BL;
  101. break;
  102. }
  103. data_1_5.payload[0] = f34->bootloader_id[0];
  104. data_1_5.payload[1] = f34->bootloader_id[1];
  105. ret = rmi_write_block(f34->fn->rmi_dev,
  106. base + f34->v7.off.partition_id,
  107. &data_1_5, sizeof(data_1_5));
  108. if (ret < 0) {
  109. dev_err(&f34->fn->dev,
  110. "%s: Failed to write single transaction command\n",
  111. __func__);
  112. return ret;
  113. }
  114. return 0;
  115. }
  116. static int rmi_f34v7_write_command(struct f34_data *f34, u8 cmd)
  117. {
  118. int ret;
  119. u8 base;
  120. u8 command;
  121. base = f34->fn->fd.data_base_addr;
  122. switch (cmd) {
  123. case v7_CMD_WRITE_FW:
  124. case v7_CMD_WRITE_CONFIG:
  125. case v7_CMD_WRITE_GUEST_CODE:
  126. command = CMD_V7_WRITE;
  127. break;
  128. case v7_CMD_READ_CONFIG:
  129. command = CMD_V7_READ;
  130. break;
  131. case v7_CMD_ERASE_ALL:
  132. command = CMD_V7_ERASE_AP;
  133. break;
  134. case v7_CMD_ERASE_UI_FIRMWARE:
  135. case v7_CMD_ERASE_BL_CONFIG:
  136. case v7_CMD_ERASE_UI_CONFIG:
  137. case v7_CMD_ERASE_DISP_CONFIG:
  138. case v7_CMD_ERASE_FLASH_CONFIG:
  139. case v7_CMD_ERASE_GUEST_CODE:
  140. command = CMD_V7_ERASE;
  141. break;
  142. case v7_CMD_ENABLE_FLASH_PROG:
  143. command = CMD_V7_ENTER_BL;
  144. break;
  145. default:
  146. dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
  147. __func__, cmd);
  148. return -EINVAL;
  149. }
  150. f34->v7.command = command;
  151. switch (cmd) {
  152. case v7_CMD_ERASE_ALL:
  153. case v7_CMD_ERASE_UI_FIRMWARE:
  154. case v7_CMD_ERASE_BL_CONFIG:
  155. case v7_CMD_ERASE_UI_CONFIG:
  156. case v7_CMD_ERASE_DISP_CONFIG:
  157. case v7_CMD_ERASE_FLASH_CONFIG:
  158. case v7_CMD_ERASE_GUEST_CODE:
  159. case v7_CMD_ENABLE_FLASH_PROG:
  160. ret = rmi_f34v7_write_command_single_transaction(f34, cmd);
  161. if (ret < 0)
  162. return ret;
  163. else
  164. return 0;
  165. default:
  166. break;
  167. }
  168. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: writing cmd %02X\n",
  169. __func__, command);
  170. ret = rmi_write_block(f34->fn->rmi_dev,
  171. base + f34->v7.off.flash_cmd,
  172. &command, sizeof(command));
  173. if (ret < 0) {
  174. dev_err(&f34->fn->dev, "%s: Failed to write flash command\n",
  175. __func__);
  176. return ret;
  177. }
  178. return 0;
  179. }
  180. static int rmi_f34v7_write_partition_id(struct f34_data *f34, u8 cmd)
  181. {
  182. int ret;
  183. u8 base;
  184. u8 partition;
  185. base = f34->fn->fd.data_base_addr;
  186. switch (cmd) {
  187. case v7_CMD_WRITE_FW:
  188. partition = CORE_CODE_PARTITION;
  189. break;
  190. case v7_CMD_WRITE_CONFIG:
  191. case v7_CMD_READ_CONFIG:
  192. if (f34->v7.config_area == v7_UI_CONFIG_AREA)
  193. partition = CORE_CONFIG_PARTITION;
  194. else if (f34->v7.config_area == v7_DP_CONFIG_AREA)
  195. partition = DISPLAY_CONFIG_PARTITION;
  196. else if (f34->v7.config_area == v7_PM_CONFIG_AREA)
  197. partition = GUEST_SERIALIZATION_PARTITION;
  198. else if (f34->v7.config_area == v7_BL_CONFIG_AREA)
  199. partition = GLOBAL_PARAMETERS_PARTITION;
  200. else if (f34->v7.config_area == v7_FLASH_CONFIG_AREA)
  201. partition = FLASH_CONFIG_PARTITION;
  202. break;
  203. case v7_CMD_WRITE_GUEST_CODE:
  204. partition = GUEST_CODE_PARTITION;
  205. break;
  206. case v7_CMD_ERASE_ALL:
  207. partition = CORE_CODE_PARTITION;
  208. break;
  209. case v7_CMD_ERASE_BL_CONFIG:
  210. partition = GLOBAL_PARAMETERS_PARTITION;
  211. break;
  212. case v7_CMD_ERASE_UI_CONFIG:
  213. partition = CORE_CONFIG_PARTITION;
  214. break;
  215. case v7_CMD_ERASE_DISP_CONFIG:
  216. partition = DISPLAY_CONFIG_PARTITION;
  217. break;
  218. case v7_CMD_ERASE_FLASH_CONFIG:
  219. partition = FLASH_CONFIG_PARTITION;
  220. break;
  221. case v7_CMD_ERASE_GUEST_CODE:
  222. partition = GUEST_CODE_PARTITION;
  223. break;
  224. case v7_CMD_ENABLE_FLASH_PROG:
  225. partition = BOOTLOADER_PARTITION;
  226. break;
  227. default:
  228. dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
  229. __func__, cmd);
  230. return -EINVAL;
  231. }
  232. ret = rmi_write_block(f34->fn->rmi_dev,
  233. base + f34->v7.off.partition_id,
  234. &partition, sizeof(partition));
  235. if (ret < 0) {
  236. dev_err(&f34->fn->dev, "%s: Failed to write partition ID\n",
  237. __func__);
  238. return ret;
  239. }
  240. return 0;
  241. }
  242. static int rmi_f34v7_read_partition_table(struct f34_data *f34)
  243. {
  244. int ret;
  245. unsigned long timeout;
  246. u8 base;
  247. __le16 length;
  248. u16 block_number = 0;
  249. base = f34->fn->fd.data_base_addr;
  250. f34->v7.config_area = v7_FLASH_CONFIG_AREA;
  251. ret = rmi_f34v7_write_partition_id(f34, v7_CMD_READ_CONFIG);
  252. if (ret < 0)
  253. return ret;
  254. ret = rmi_write_block(f34->fn->rmi_dev,
  255. base + f34->v7.off.block_number,
  256. &block_number, sizeof(block_number));
  257. if (ret < 0) {
  258. dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
  259. __func__);
  260. return ret;
  261. }
  262. put_unaligned_le16(f34->v7.flash_config_length, &length);
  263. ret = rmi_write_block(f34->fn->rmi_dev,
  264. base + f34->v7.off.transfer_length,
  265. &length, sizeof(length));
  266. if (ret < 0) {
  267. dev_err(&f34->fn->dev, "%s: Failed to write transfer length\n",
  268. __func__);
  269. return ret;
  270. }
  271. init_completion(&f34->v7.cmd_done);
  272. ret = rmi_f34v7_write_command(f34, v7_CMD_READ_CONFIG);
  273. if (ret < 0) {
  274. dev_err(&f34->fn->dev, "%s: Failed to write command\n",
  275. __func__);
  276. return ret;
  277. }
  278. timeout = msecs_to_jiffies(F34_WRITE_WAIT_MS);
  279. while (time_before(jiffies, timeout)) {
  280. usleep_range(5000, 6000);
  281. rmi_f34v7_read_flash_status(f34);
  282. if (f34->v7.command == v7_CMD_IDLE &&
  283. f34->v7.flash_status == 0x00) {
  284. break;
  285. }
  286. }
  287. ret = rmi_read_block(f34->fn->rmi_dev,
  288. base + f34->v7.off.payload,
  289. f34->v7.read_config_buf,
  290. f34->v7.partition_table_bytes);
  291. if (ret < 0) {
  292. dev_err(&f34->fn->dev, "%s: Failed to read block data\n",
  293. __func__);
  294. return ret;
  295. }
  296. return 0;
  297. }
  298. static void rmi_f34v7_parse_partition_table(struct f34_data *f34,
  299. const void *partition_table,
  300. struct block_count *blkcount,
  301. struct physical_address *phyaddr)
  302. {
  303. int i;
  304. int index;
  305. u16 partition_length;
  306. u16 physical_address;
  307. const struct partition_table *ptable;
  308. for (i = 0; i < f34->v7.partitions; i++) {
  309. index = i * 8 + 2;
  310. ptable = partition_table + index;
  311. partition_length = le16_to_cpu(ptable->partition_length);
  312. physical_address = le16_to_cpu(ptable->start_physical_address);
  313. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  314. "%s: Partition entry %d: %*ph\n",
  315. __func__, i, sizeof(struct partition_table), ptable);
  316. switch (ptable->partition_id & 0x1f) {
  317. case CORE_CODE_PARTITION:
  318. blkcount->ui_firmware = partition_length;
  319. phyaddr->ui_firmware = physical_address;
  320. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  321. "%s: Core code block count: %d\n",
  322. __func__, blkcount->ui_firmware);
  323. break;
  324. case CORE_CONFIG_PARTITION:
  325. blkcount->ui_config = partition_length;
  326. phyaddr->ui_config = physical_address;
  327. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  328. "%s: Core config block count: %d\n",
  329. __func__, blkcount->ui_config);
  330. break;
  331. case DISPLAY_CONFIG_PARTITION:
  332. blkcount->dp_config = partition_length;
  333. phyaddr->dp_config = physical_address;
  334. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  335. "%s: Display config block count: %d\n",
  336. __func__, blkcount->dp_config);
  337. break;
  338. case FLASH_CONFIG_PARTITION:
  339. blkcount->fl_config = partition_length;
  340. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  341. "%s: Flash config block count: %d\n",
  342. __func__, blkcount->fl_config);
  343. break;
  344. case GUEST_CODE_PARTITION:
  345. blkcount->guest_code = partition_length;
  346. phyaddr->guest_code = physical_address;
  347. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  348. "%s: Guest code block count: %d\n",
  349. __func__, blkcount->guest_code);
  350. break;
  351. case GUEST_SERIALIZATION_PARTITION:
  352. blkcount->pm_config = partition_length;
  353. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  354. "%s: Guest serialization block count: %d\n",
  355. __func__, blkcount->pm_config);
  356. break;
  357. case GLOBAL_PARAMETERS_PARTITION:
  358. blkcount->bl_config = partition_length;
  359. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  360. "%s: Global parameters block count: %d\n",
  361. __func__, blkcount->bl_config);
  362. break;
  363. case DEVICE_CONFIG_PARTITION:
  364. blkcount->lockdown = partition_length;
  365. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  366. "%s: Device config block count: %d\n",
  367. __func__, blkcount->lockdown);
  368. break;
  369. }
  370. }
  371. }
  372. static int rmi_f34v7_read_queries_bl_version(struct f34_data *f34)
  373. {
  374. int ret;
  375. u8 base;
  376. int offset;
  377. u8 query_0;
  378. struct f34v7_query_1_7 query_1_7;
  379. base = f34->fn->fd.query_base_addr;
  380. ret = rmi_read_block(f34->fn->rmi_dev,
  381. base,
  382. &query_0,
  383. sizeof(query_0));
  384. if (ret < 0) {
  385. dev_err(&f34->fn->dev,
  386. "%s: Failed to read query 0\n", __func__);
  387. return ret;
  388. }
  389. offset = (query_0 & 0x7) + 1;
  390. ret = rmi_read_block(f34->fn->rmi_dev,
  391. base + offset,
  392. &query_1_7,
  393. sizeof(query_1_7));
  394. if (ret < 0) {
  395. dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
  396. __func__);
  397. return ret;
  398. }
  399. f34->bootloader_id[0] = query_1_7.bl_minor_revision;
  400. f34->bootloader_id[1] = query_1_7.bl_major_revision;
  401. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Bootloader V%d.%d\n",
  402. f34->bootloader_id[1], f34->bootloader_id[0]);
  403. return 0;
  404. }
  405. static int rmi_f34v7_read_queries(struct f34_data *f34)
  406. {
  407. int ret;
  408. int i;
  409. u8 base;
  410. int offset;
  411. u8 *ptable;
  412. u8 query_0;
  413. struct f34v7_query_1_7 query_1_7;
  414. base = f34->fn->fd.query_base_addr;
  415. ret = rmi_read_block(f34->fn->rmi_dev,
  416. base,
  417. &query_0,
  418. sizeof(query_0));
  419. if (ret < 0) {
  420. dev_err(&f34->fn->dev,
  421. "%s: Failed to read query 0\n", __func__);
  422. return ret;
  423. }
  424. offset = (query_0 & 0x07) + 1;
  425. ret = rmi_read_block(f34->fn->rmi_dev,
  426. base + offset,
  427. &query_1_7,
  428. sizeof(query_1_7));
  429. if (ret < 0) {
  430. dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
  431. __func__);
  432. return ret;
  433. }
  434. f34->bootloader_id[0] = query_1_7.bl_minor_revision;
  435. f34->bootloader_id[1] = query_1_7.bl_major_revision;
  436. f34->v7.block_size = le16_to_cpu(query_1_7.block_size);
  437. f34->v7.flash_config_length =
  438. le16_to_cpu(query_1_7.flash_config_length);
  439. f34->v7.payload_length = le16_to_cpu(query_1_7.payload_length);
  440. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.block_size = %d\n",
  441. __func__, f34->v7.block_size);
  442. f34->v7.off.flash_status = V7_FLASH_STATUS_OFFSET;
  443. f34->v7.off.partition_id = V7_PARTITION_ID_OFFSET;
  444. f34->v7.off.block_number = V7_BLOCK_NUMBER_OFFSET;
  445. f34->v7.off.transfer_length = V7_TRANSFER_LENGTH_OFFSET;
  446. f34->v7.off.flash_cmd = V7_COMMAND_OFFSET;
  447. f34->v7.off.payload = V7_PAYLOAD_OFFSET;
  448. f34->v7.has_display_cfg = query_1_7.partition_support[1] & HAS_DISP_CFG;
  449. f34->v7.has_guest_code =
  450. query_1_7.partition_support[1] & HAS_GUEST_CODE;
  451. if (query_0 & HAS_CONFIG_ID) {
  452. u8 f34_ctrl[CONFIG_ID_SIZE];
  453. ret = rmi_read_block(f34->fn->rmi_dev,
  454. f34->fn->fd.control_base_addr,
  455. f34_ctrl,
  456. sizeof(f34_ctrl));
  457. if (ret)
  458. return ret;
  459. /* Eat leading zeros */
  460. for (i = 0; i < sizeof(f34_ctrl) - 1 && !f34_ctrl[i]; i++)
  461. /* Empty */;
  462. snprintf(f34->configuration_id, sizeof(f34->configuration_id),
  463. "%*phN", (int)sizeof(f34_ctrl) - i, f34_ctrl + i);
  464. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Configuration ID: %s\n",
  465. f34->configuration_id);
  466. }
  467. f34->v7.partitions = 0;
  468. for (i = 0; i < sizeof(query_1_7.partition_support); i++)
  469. f34->v7.partitions += hweight8(query_1_7.partition_support[i]);
  470. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: Supported partitions: %*ph\n",
  471. __func__, sizeof(query_1_7.partition_support),
  472. query_1_7.partition_support);
  473. f34->v7.partition_table_bytes = f34->v7.partitions * 8 + 2;
  474. f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
  475. f34->v7.partition_table_bytes,
  476. GFP_KERNEL);
  477. if (!f34->v7.read_config_buf) {
  478. f34->v7.read_config_buf_size = 0;
  479. return -ENOMEM;
  480. }
  481. f34->v7.read_config_buf_size = f34->v7.partition_table_bytes;
  482. ptable = f34->v7.read_config_buf;
  483. ret = rmi_f34v7_read_partition_table(f34);
  484. if (ret < 0) {
  485. dev_err(&f34->fn->dev, "%s: Failed to read partition table\n",
  486. __func__);
  487. return ret;
  488. }
  489. rmi_f34v7_parse_partition_table(f34, ptable,
  490. &f34->v7.blkcount, &f34->v7.phyaddr);
  491. return 0;
  492. }
  493. static int rmi_f34v7_check_ui_firmware_size(struct f34_data *f34)
  494. {
  495. u16 block_count;
  496. block_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
  497. f34->update_size += block_count;
  498. if (block_count != f34->v7.blkcount.ui_firmware) {
  499. dev_err(&f34->fn->dev,
  500. "UI firmware size mismatch: %d != %d\n",
  501. block_count, f34->v7.blkcount.ui_firmware);
  502. return -EINVAL;
  503. }
  504. return 0;
  505. }
  506. static int rmi_f34v7_check_ui_config_size(struct f34_data *f34)
  507. {
  508. u16 block_count;
  509. block_count = f34->v7.img.ui_config.size / f34->v7.block_size;
  510. f34->update_size += block_count;
  511. if (block_count != f34->v7.blkcount.ui_config) {
  512. dev_err(&f34->fn->dev, "UI config size mismatch\n");
  513. return -EINVAL;
  514. }
  515. return 0;
  516. }
  517. static int rmi_f34v7_check_dp_config_size(struct f34_data *f34)
  518. {
  519. u16 block_count;
  520. block_count = f34->v7.img.dp_config.size / f34->v7.block_size;
  521. f34->update_size += block_count;
  522. if (block_count != f34->v7.blkcount.dp_config) {
  523. dev_err(&f34->fn->dev, "Display config size mismatch\n");
  524. return -EINVAL;
  525. }
  526. return 0;
  527. }
  528. static int rmi_f34v7_check_guest_code_size(struct f34_data *f34)
  529. {
  530. u16 block_count;
  531. block_count = f34->v7.img.guest_code.size / f34->v7.block_size;
  532. f34->update_size += block_count;
  533. if (block_count != f34->v7.blkcount.guest_code) {
  534. dev_err(&f34->fn->dev, "Guest code size mismatch\n");
  535. return -EINVAL;
  536. }
  537. return 0;
  538. }
  539. static int rmi_f34v7_check_bl_config_size(struct f34_data *f34)
  540. {
  541. u16 block_count;
  542. block_count = f34->v7.img.bl_config.size / f34->v7.block_size;
  543. f34->update_size += block_count;
  544. if (block_count != f34->v7.blkcount.bl_config) {
  545. dev_err(&f34->fn->dev, "Bootloader config size mismatch\n");
  546. return -EINVAL;
  547. }
  548. return 0;
  549. }
  550. static int rmi_f34v7_erase_config(struct f34_data *f34)
  551. {
  552. int ret;
  553. dev_info(&f34->fn->dev, "Erasing config...\n");
  554. init_completion(&f34->v7.cmd_done);
  555. switch (f34->v7.config_area) {
  556. case v7_UI_CONFIG_AREA:
  557. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_CONFIG);
  558. if (ret < 0)
  559. return ret;
  560. break;
  561. case v7_DP_CONFIG_AREA:
  562. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_DISP_CONFIG);
  563. if (ret < 0)
  564. return ret;
  565. break;
  566. case v7_BL_CONFIG_AREA:
  567. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_BL_CONFIG);
  568. if (ret < 0)
  569. return ret;
  570. break;
  571. }
  572. ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
  573. if (ret < 0)
  574. return ret;
  575. return 0;
  576. }
  577. static int rmi_f34v7_erase_guest_code(struct f34_data *f34)
  578. {
  579. int ret;
  580. dev_info(&f34->fn->dev, "Erasing guest code...\n");
  581. init_completion(&f34->v7.cmd_done);
  582. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_GUEST_CODE);
  583. if (ret < 0)
  584. return ret;
  585. ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
  586. if (ret < 0)
  587. return ret;
  588. return 0;
  589. }
  590. static int rmi_f34v7_erase_all(struct f34_data *f34)
  591. {
  592. int ret;
  593. dev_info(&f34->fn->dev, "Erasing firmware...\n");
  594. init_completion(&f34->v7.cmd_done);
  595. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_FIRMWARE);
  596. if (ret < 0)
  597. return ret;
  598. ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
  599. if (ret < 0)
  600. return ret;
  601. f34->v7.config_area = v7_UI_CONFIG_AREA;
  602. ret = rmi_f34v7_erase_config(f34);
  603. if (ret < 0)
  604. return ret;
  605. if (f34->v7.has_display_cfg) {
  606. f34->v7.config_area = v7_DP_CONFIG_AREA;
  607. ret = rmi_f34v7_erase_config(f34);
  608. if (ret < 0)
  609. return ret;
  610. }
  611. if (f34->v7.new_partition_table && f34->v7.has_guest_code) {
  612. ret = rmi_f34v7_erase_guest_code(f34);
  613. if (ret < 0)
  614. return ret;
  615. }
  616. return 0;
  617. }
  618. static int rmi_f34v7_read_blocks(struct f34_data *f34,
  619. u16 block_cnt, u8 command)
  620. {
  621. int ret;
  622. u8 base;
  623. __le16 length;
  624. u16 transfer;
  625. u16 max_transfer;
  626. u16 remaining = block_cnt;
  627. u16 block_number = 0;
  628. u16 index = 0;
  629. base = f34->fn->fd.data_base_addr;
  630. ret = rmi_f34v7_write_partition_id(f34, command);
  631. if (ret < 0)
  632. return ret;
  633. ret = rmi_write_block(f34->fn->rmi_dev,
  634. base + f34->v7.off.block_number,
  635. &block_number, sizeof(block_number));
  636. if (ret < 0) {
  637. dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
  638. __func__);
  639. return ret;
  640. }
  641. max_transfer = min(f34->v7.payload_length,
  642. (u16)(PAGE_SIZE / f34->v7.block_size));
  643. do {
  644. transfer = min(remaining, max_transfer);
  645. put_unaligned_le16(transfer, &length);
  646. ret = rmi_write_block(f34->fn->rmi_dev,
  647. base + f34->v7.off.transfer_length,
  648. &length, sizeof(length));
  649. if (ret < 0) {
  650. dev_err(&f34->fn->dev,
  651. "%s: Write transfer length fail (%d remaining)\n",
  652. __func__, remaining);
  653. return ret;
  654. }
  655. init_completion(&f34->v7.cmd_done);
  656. ret = rmi_f34v7_write_command(f34, command);
  657. if (ret < 0)
  658. return ret;
  659. ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
  660. if (ret < 0)
  661. return ret;
  662. ret = rmi_read_block(f34->fn->rmi_dev,
  663. base + f34->v7.off.payload,
  664. &f34->v7.read_config_buf[index],
  665. transfer * f34->v7.block_size);
  666. if (ret < 0) {
  667. dev_err(&f34->fn->dev,
  668. "%s: Read block failed (%d blks remaining)\n",
  669. __func__, remaining);
  670. return ret;
  671. }
  672. index += (transfer * f34->v7.block_size);
  673. remaining -= transfer;
  674. } while (remaining);
  675. return 0;
  676. }
  677. static int rmi_f34v7_write_f34v7_blocks(struct f34_data *f34,
  678. const void *block_ptr, u16 block_cnt,
  679. u8 command)
  680. {
  681. int ret;
  682. u8 base;
  683. __le16 length;
  684. u16 transfer;
  685. u16 max_transfer;
  686. u16 remaining = block_cnt;
  687. u16 block_number = 0;
  688. base = f34->fn->fd.data_base_addr;
  689. ret = rmi_f34v7_write_partition_id(f34, command);
  690. if (ret < 0)
  691. return ret;
  692. ret = rmi_write_block(f34->fn->rmi_dev,
  693. base + f34->v7.off.block_number,
  694. &block_number, sizeof(block_number));
  695. if (ret < 0) {
  696. dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
  697. __func__);
  698. return ret;
  699. }
  700. if (f34->v7.payload_length > (PAGE_SIZE / f34->v7.block_size))
  701. max_transfer = PAGE_SIZE / f34->v7.block_size;
  702. else
  703. max_transfer = f34->v7.payload_length;
  704. do {
  705. transfer = min(remaining, max_transfer);
  706. put_unaligned_le16(transfer, &length);
  707. init_completion(&f34->v7.cmd_done);
  708. ret = rmi_write_block(f34->fn->rmi_dev,
  709. base + f34->v7.off.transfer_length,
  710. &length, sizeof(length));
  711. if (ret < 0) {
  712. dev_err(&f34->fn->dev,
  713. "%s: Write transfer length fail (%d remaining)\n",
  714. __func__, remaining);
  715. return ret;
  716. }
  717. ret = rmi_f34v7_write_command(f34, command);
  718. if (ret < 0)
  719. return ret;
  720. ret = rmi_write_block(f34->fn->rmi_dev,
  721. base + f34->v7.off.payload,
  722. block_ptr, transfer * f34->v7.block_size);
  723. if (ret < 0) {
  724. dev_err(&f34->fn->dev,
  725. "%s: Failed writing data (%d blks remaining)\n",
  726. __func__, remaining);
  727. return ret;
  728. }
  729. ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
  730. if (ret < 0)
  731. return ret;
  732. block_ptr += (transfer * f34->v7.block_size);
  733. remaining -= transfer;
  734. f34->update_progress += transfer;
  735. f34->update_status = (f34->update_progress * 100) /
  736. f34->update_size;
  737. } while (remaining);
  738. return 0;
  739. }
  740. static int rmi_f34v7_write_config(struct f34_data *f34)
  741. {
  742. return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.config_data,
  743. f34->v7.config_block_count,
  744. v7_CMD_WRITE_CONFIG);
  745. }
  746. static int rmi_f34v7_write_ui_config(struct f34_data *f34)
  747. {
  748. f34->v7.config_area = v7_UI_CONFIG_AREA;
  749. f34->v7.config_data = f34->v7.img.ui_config.data;
  750. f34->v7.config_size = f34->v7.img.ui_config.size;
  751. f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
  752. return rmi_f34v7_write_config(f34);
  753. }
  754. static int rmi_f34v7_write_dp_config(struct f34_data *f34)
  755. {
  756. f34->v7.config_area = v7_DP_CONFIG_AREA;
  757. f34->v7.config_data = f34->v7.img.dp_config.data;
  758. f34->v7.config_size = f34->v7.img.dp_config.size;
  759. f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
  760. return rmi_f34v7_write_config(f34);
  761. }
  762. static int rmi_f34v7_write_guest_code(struct f34_data *f34)
  763. {
  764. return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.guest_code.data,
  765. f34->v7.img.guest_code.size /
  766. f34->v7.block_size,
  767. v7_CMD_WRITE_GUEST_CODE);
  768. }
  769. static int rmi_f34v7_write_flash_config(struct f34_data *f34)
  770. {
  771. int ret;
  772. f34->v7.config_area = v7_FLASH_CONFIG_AREA;
  773. f34->v7.config_data = f34->v7.img.fl_config.data;
  774. f34->v7.config_size = f34->v7.img.fl_config.size;
  775. f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
  776. if (f34->v7.config_block_count != f34->v7.blkcount.fl_config) {
  777. dev_err(&f34->fn->dev, "%s: Flash config size mismatch\n",
  778. __func__);
  779. return -EINVAL;
  780. }
  781. init_completion(&f34->v7.cmd_done);
  782. ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_FLASH_CONFIG);
  783. if (ret < 0)
  784. return ret;
  785. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  786. "%s: Erase flash config command written\n", __func__);
  787. ret = rmi_f34v7_wait_for_idle(f34, F34_WRITE_WAIT_MS);
  788. if (ret < 0)
  789. return ret;
  790. ret = rmi_f34v7_write_config(f34);
  791. if (ret < 0)
  792. return ret;
  793. return 0;
  794. }
  795. static int rmi_f34v7_write_partition_table(struct f34_data *f34)
  796. {
  797. u16 block_count;
  798. int ret;
  799. block_count = f34->v7.blkcount.bl_config;
  800. f34->v7.config_area = v7_BL_CONFIG_AREA;
  801. f34->v7.config_size = f34->v7.block_size * block_count;
  802. devm_kfree(&f34->fn->dev, f34->v7.read_config_buf);
  803. f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
  804. f34->v7.config_size, GFP_KERNEL);
  805. if (!f34->v7.read_config_buf) {
  806. f34->v7.read_config_buf_size = 0;
  807. return -ENOMEM;
  808. }
  809. f34->v7.read_config_buf_size = f34->v7.config_size;
  810. ret = rmi_f34v7_read_blocks(f34, block_count, v7_CMD_READ_CONFIG);
  811. if (ret < 0)
  812. return ret;
  813. ret = rmi_f34v7_erase_config(f34);
  814. if (ret < 0)
  815. return ret;
  816. ret = rmi_f34v7_write_flash_config(f34);
  817. if (ret < 0)
  818. return ret;
  819. f34->v7.config_area = v7_BL_CONFIG_AREA;
  820. f34->v7.config_data = f34->v7.read_config_buf;
  821. f34->v7.config_size = f34->v7.img.bl_config.size;
  822. f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
  823. ret = rmi_f34v7_write_config(f34);
  824. if (ret < 0)
  825. return ret;
  826. return 0;
  827. }
  828. static int rmi_f34v7_write_firmware(struct f34_data *f34)
  829. {
  830. u16 blk_count;
  831. blk_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
  832. return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.ui_firmware.data,
  833. blk_count, v7_CMD_WRITE_FW);
  834. }
  835. static void rmi_f34v7_compare_partition_tables(struct f34_data *f34)
  836. {
  837. if (f34->v7.phyaddr.ui_firmware != f34->v7.img.phyaddr.ui_firmware) {
  838. f34->v7.new_partition_table = true;
  839. return;
  840. }
  841. if (f34->v7.phyaddr.ui_config != f34->v7.img.phyaddr.ui_config) {
  842. f34->v7.new_partition_table = true;
  843. return;
  844. }
  845. if (f34->v7.has_display_cfg &&
  846. f34->v7.phyaddr.dp_config != f34->v7.img.phyaddr.dp_config) {
  847. f34->v7.new_partition_table = true;
  848. return;
  849. }
  850. if (f34->v7.has_guest_code &&
  851. f34->v7.phyaddr.guest_code != f34->v7.img.phyaddr.guest_code) {
  852. f34->v7.new_partition_table = true;
  853. return;
  854. }
  855. f34->v7.new_partition_table = false;
  856. }
  857. static void rmi_f34v7_parse_img_header_10_bl_container(struct f34_data *f34,
  858. const void *image)
  859. {
  860. int i;
  861. int num_of_containers;
  862. unsigned int addr;
  863. unsigned int container_id;
  864. unsigned int length;
  865. const void *content;
  866. const struct container_descriptor *descriptor;
  867. num_of_containers = f34->v7.img.bootloader.size / 4 - 1;
  868. for (i = 1; i <= num_of_containers; i++) {
  869. addr = get_unaligned_le32(f34->v7.img.bootloader.data + i * 4);
  870. descriptor = image + addr;
  871. container_id = le16_to_cpu(descriptor->container_id);
  872. content = image + le32_to_cpu(descriptor->content_address);
  873. length = le32_to_cpu(descriptor->content_length);
  874. switch (container_id) {
  875. case BL_CONFIG_CONTAINER:
  876. case GLOBAL_PARAMETERS_CONTAINER:
  877. f34->v7.img.bl_config.data = content;
  878. f34->v7.img.bl_config.size = length;
  879. break;
  880. case BL_LOCKDOWN_INFO_CONTAINER:
  881. case DEVICE_CONFIG_CONTAINER:
  882. f34->v7.img.lockdown.data = content;
  883. f34->v7.img.lockdown.size = length;
  884. break;
  885. default:
  886. break;
  887. }
  888. }
  889. }
  890. static void rmi_f34v7_parse_image_header_10(struct f34_data *f34)
  891. {
  892. unsigned int i;
  893. unsigned int num_of_containers;
  894. unsigned int addr;
  895. unsigned int offset;
  896. unsigned int container_id;
  897. unsigned int length;
  898. const void *image = f34->v7.image;
  899. const u8 *content;
  900. const struct container_descriptor *descriptor;
  901. const struct image_header_10 *header = image;
  902. f34->v7.img.checksum = le32_to_cpu(header->checksum);
  903. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.img.checksum=%X\n",
  904. __func__, f34->v7.img.checksum);
  905. /* address of top level container */
  906. offset = le32_to_cpu(header->top_level_container_start_addr);
  907. descriptor = image + offset;
  908. /* address of top level container content */
  909. offset = le32_to_cpu(descriptor->content_address);
  910. num_of_containers = le32_to_cpu(descriptor->content_length) / 4;
  911. for (i = 0; i < num_of_containers; i++) {
  912. addr = get_unaligned_le32(image + offset);
  913. offset += 4;
  914. descriptor = image + addr;
  915. container_id = le16_to_cpu(descriptor->container_id);
  916. content = image + le32_to_cpu(descriptor->content_address);
  917. length = le32_to_cpu(descriptor->content_length);
  918. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  919. "%s: container_id=%d, length=%d\n", __func__,
  920. container_id, length);
  921. switch (container_id) {
  922. case UI_CONTAINER:
  923. case CORE_CODE_CONTAINER:
  924. f34->v7.img.ui_firmware.data = content;
  925. f34->v7.img.ui_firmware.size = length;
  926. break;
  927. case UI_CONFIG_CONTAINER:
  928. case CORE_CONFIG_CONTAINER:
  929. f34->v7.img.ui_config.data = content;
  930. f34->v7.img.ui_config.size = length;
  931. break;
  932. case BL_CONTAINER:
  933. f34->v7.img.bl_version = *content;
  934. f34->v7.img.bootloader.data = content;
  935. f34->v7.img.bootloader.size = length;
  936. rmi_f34v7_parse_img_header_10_bl_container(f34, image);
  937. break;
  938. case GUEST_CODE_CONTAINER:
  939. f34->v7.img.contains_guest_code = true;
  940. f34->v7.img.guest_code.data = content;
  941. f34->v7.img.guest_code.size = length;
  942. break;
  943. case DISPLAY_CONFIG_CONTAINER:
  944. f34->v7.img.contains_display_cfg = true;
  945. f34->v7.img.dp_config.data = content;
  946. f34->v7.img.dp_config.size = length;
  947. break;
  948. case FLASH_CONFIG_CONTAINER:
  949. f34->v7.img.contains_flash_config = true;
  950. f34->v7.img.fl_config.data = content;
  951. f34->v7.img.fl_config.size = length;
  952. break;
  953. case GENERAL_INFORMATION_CONTAINER:
  954. f34->v7.img.contains_firmware_id = true;
  955. f34->v7.img.firmware_id =
  956. get_unaligned_le32(content + 4);
  957. break;
  958. default:
  959. break;
  960. }
  961. }
  962. }
  963. static int rmi_f34v7_parse_image_info(struct f34_data *f34)
  964. {
  965. const struct image_header_10 *header = f34->v7.image;
  966. memset(&f34->v7.img, 0x00, sizeof(f34->v7.img));
  967. rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
  968. "%s: header->major_header_version = %d\n",
  969. __func__, header->major_header_version);
  970. switch (header->major_header_version) {
  971. case IMAGE_HEADER_VERSION_10:
  972. rmi_f34v7_parse_image_header_10(f34);
  973. break;
  974. default:
  975. dev_err(&f34->fn->dev, "Unsupported image file format %02X\n",
  976. header->major_header_version);
  977. return -EINVAL;
  978. }
  979. if (!f34->v7.img.contains_flash_config) {
  980. dev_err(&f34->fn->dev, "%s: No flash config in fw image\n",
  981. __func__);
  982. return -EINVAL;
  983. }
  984. rmi_f34v7_parse_partition_table(f34, f34->v7.img.fl_config.data,
  985. &f34->v7.img.blkcount, &f34->v7.img.phyaddr);
  986. rmi_f34v7_compare_partition_tables(f34);
  987. return 0;
  988. }
  989. int rmi_f34v7_do_reflash(struct f34_data *f34, const struct firmware *fw)
  990. {
  991. int ret;
  992. f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev,
  993. f34->fn->irq_mask);
  994. rmi_f34v7_read_queries_bl_version(f34);
  995. f34->v7.image = fw->data;
  996. f34->update_progress = 0;
  997. f34->update_size = 0;
  998. ret = rmi_f34v7_parse_image_info(f34);
  999. if (ret < 0)
  1000. goto fail;
  1001. if (!f34->v7.new_partition_table) {
  1002. ret = rmi_f34v7_check_ui_firmware_size(f34);
  1003. if (ret < 0)
  1004. goto fail;
  1005. ret = rmi_f34v7_check_ui_config_size(f34);
  1006. if (ret < 0)
  1007. goto fail;
  1008. if (f34->v7.has_display_cfg &&
  1009. f34->v7.img.contains_display_cfg) {
  1010. ret = rmi_f34v7_check_dp_config_size(f34);
  1011. if (ret < 0)
  1012. goto fail;
  1013. }
  1014. if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
  1015. ret = rmi_f34v7_check_guest_code_size(f34);
  1016. if (ret < 0)
  1017. goto fail;
  1018. }
  1019. } else {
  1020. ret = rmi_f34v7_check_bl_config_size(f34);
  1021. if (ret < 0)
  1022. goto fail;
  1023. }
  1024. ret = rmi_f34v7_erase_all(f34);
  1025. if (ret < 0)
  1026. goto fail;
  1027. if (f34->v7.new_partition_table) {
  1028. ret = rmi_f34v7_write_partition_table(f34);
  1029. if (ret < 0)
  1030. goto fail;
  1031. dev_info(&f34->fn->dev, "%s: Partition table programmed\n",
  1032. __func__);
  1033. }
  1034. dev_info(&f34->fn->dev, "Writing firmware (%d bytes)...\n",
  1035. f34->v7.img.ui_firmware.size);
  1036. ret = rmi_f34v7_write_firmware(f34);
  1037. if (ret < 0)
  1038. goto fail;
  1039. dev_info(&f34->fn->dev, "Writing config (%d bytes)...\n",
  1040. f34->v7.img.ui_config.size);
  1041. f34->v7.config_area = v7_UI_CONFIG_AREA;
  1042. ret = rmi_f34v7_write_ui_config(f34);
  1043. if (ret < 0)
  1044. goto fail;
  1045. if (f34->v7.has_display_cfg && f34->v7.img.contains_display_cfg) {
  1046. dev_info(&f34->fn->dev, "Writing display config...\n");
  1047. ret = rmi_f34v7_write_dp_config(f34);
  1048. if (ret < 0)
  1049. goto fail;
  1050. }
  1051. if (f34->v7.new_partition_table) {
  1052. if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
  1053. dev_info(&f34->fn->dev, "Writing guest code...\n");
  1054. ret = rmi_f34v7_write_guest_code(f34);
  1055. if (ret < 0)
  1056. goto fail;
  1057. }
  1058. }
  1059. fail:
  1060. return ret;
  1061. }
  1062. static int rmi_f34v7_enter_flash_prog(struct f34_data *f34)
  1063. {
  1064. int ret;
  1065. f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
  1066. ret = rmi_f34v7_read_flash_status(f34);
  1067. if (ret < 0)
  1068. return ret;
  1069. if (f34->v7.in_bl_mode)
  1070. return 0;
  1071. init_completion(&f34->v7.cmd_done);
  1072. ret = rmi_f34v7_write_command(f34, v7_CMD_ENABLE_FLASH_PROG);
  1073. if (ret < 0)
  1074. return ret;
  1075. ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
  1076. if (ret < 0)
  1077. return ret;
  1078. return 0;
  1079. }
  1080. int rmi_f34v7_start_reflash(struct f34_data *f34, const struct firmware *fw)
  1081. {
  1082. int ret = 0;
  1083. f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
  1084. f34->v7.config_area = v7_UI_CONFIG_AREA;
  1085. f34->v7.image = fw->data;
  1086. ret = rmi_f34v7_parse_image_info(f34);
  1087. if (ret < 0)
  1088. goto exit;
  1089. if (!f34->v7.force_update && f34->v7.new_partition_table) {
  1090. dev_err(&f34->fn->dev, "%s: Partition table mismatch\n",
  1091. __func__);
  1092. ret = -EINVAL;
  1093. goto exit;
  1094. }
  1095. dev_info(&f34->fn->dev, "Firmware image OK\n");
  1096. ret = rmi_f34v7_read_flash_status(f34);
  1097. if (ret < 0)
  1098. goto exit;
  1099. if (f34->v7.in_bl_mode) {
  1100. dev_info(&f34->fn->dev, "%s: Device in bootloader mode\n",
  1101. __func__);
  1102. }
  1103. rmi_f34v7_enter_flash_prog(f34);
  1104. return 0;
  1105. exit:
  1106. return ret;
  1107. }
  1108. int rmi_f34v7_probe(struct f34_data *f34)
  1109. {
  1110. int ret;
  1111. /* Read bootloader version */
  1112. ret = rmi_read_block(f34->fn->rmi_dev,
  1113. f34->fn->fd.query_base_addr + V7_BOOTLOADER_ID_OFFSET,
  1114. f34->bootloader_id,
  1115. sizeof(f34->bootloader_id));
  1116. if (ret < 0) {
  1117. dev_err(&f34->fn->dev, "%s: Failed to read bootloader ID\n",
  1118. __func__);
  1119. return ret;
  1120. }
  1121. if (f34->bootloader_id[1] == '5') {
  1122. f34->bl_version = 5;
  1123. } else if (f34->bootloader_id[1] == '6') {
  1124. f34->bl_version = 6;
  1125. } else if (f34->bootloader_id[1] == 7) {
  1126. f34->bl_version = 7;
  1127. } else if (f34->bootloader_id[1] == 8) {
  1128. f34->bl_version = 8;
  1129. } else {
  1130. dev_err(&f34->fn->dev,
  1131. "%s: Unrecognized bootloader version: %d (%c) %d (%c)\n",
  1132. __func__,
  1133. f34->bootloader_id[0], f34->bootloader_id[0],
  1134. f34->bootloader_id[1], f34->bootloader_id[1]);
  1135. return -EINVAL;
  1136. }
  1137. memset(&f34->v7.blkcount, 0x00, sizeof(f34->v7.blkcount));
  1138. memset(&f34->v7.phyaddr, 0x00, sizeof(f34->v7.phyaddr));
  1139. init_completion(&f34->v7.cmd_done);
  1140. ret = rmi_f34v7_read_queries(f34);
  1141. if (ret < 0)
  1142. return ret;
  1143. f34->v7.force_update = true;
  1144. return 0;
  1145. }